linux/drivers/gpu/drm/radeon/si_dpm.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/math64.h>
#include <linux/pci.h>
#include <linux/seq_file.h>

#include "atom.h"
#include "evergreen.h"
#include "r600_dpm.h"
#include "rv770.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "ni_dpm.h"
#include "si_dpm.h"
#include "si.h"
#include "sid.h"
#include "vce.h"

#define MC_CG_ARB_FREQ_F0 …
#define MC_CG_ARB_FREQ_F1 …
#define MC_CG_ARB_FREQ_F2 …
#define MC_CG_ARB_FREQ_F3 …

#define SMC_RAM_END …

#define SCLK_MIN_DEEPSLEEP_FREQ …

static const struct si_cac_config_reg cac_weights_tahiti[] = …;

static const struct si_cac_config_reg lcac_tahiti[] = …;

static const struct si_cac_config_reg cac_override_tahiti[] = …;

static const struct si_powertune_data powertune_data_tahiti = …;

static const struct si_dte_data dte_data_tahiti = …;

static const struct si_dte_data dte_data_tahiti_pro = …;

static const struct si_dte_data dte_data_new_zealand = …;

static const struct si_dte_data dte_data_aruba_pro = …;

static const struct si_dte_data dte_data_malta = …;

static struct si_cac_config_reg cac_weights_pitcairn[] = …;

static const struct si_cac_config_reg lcac_pitcairn[] = …;

static const struct si_cac_config_reg cac_override_pitcairn[] = …;

static const struct si_powertune_data powertune_data_pitcairn = …;

static const struct si_dte_data dte_data_pitcairn = …;

static const struct si_dte_data dte_data_curacao_xt = …;

static const struct si_dte_data dte_data_curacao_pro = …;

static const struct si_dte_data dte_data_neptune_xt = …;

static const struct si_cac_config_reg cac_weights_chelsea_pro[] = …;

static const struct si_cac_config_reg cac_weights_chelsea_xt[] = …;

static const struct si_cac_config_reg cac_weights_heathrow[] = …;

static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = …;

static const struct si_cac_config_reg cac_weights_cape_verde[] = …;

static const struct si_cac_config_reg lcac_cape_verde[] = …;

static const struct si_cac_config_reg cac_override_cape_verde[] = …;

static const struct si_powertune_data powertune_data_cape_verde = …;

static const struct si_dte_data dte_data_cape_verde = …;

static const struct si_dte_data dte_data_venus_xtx = …;

static const struct si_dte_data dte_data_venus_xt = …;

static const struct si_dte_data dte_data_venus_pro = …;

static struct si_cac_config_reg cac_weights_oland[] = …;

static const struct si_cac_config_reg cac_weights_mars_pro[] = …;

static const struct si_cac_config_reg cac_weights_mars_xt[] = …;

static const struct si_cac_config_reg cac_weights_oland_pro[] = …;

static const struct si_cac_config_reg cac_weights_oland_xt[] = …;

static const struct si_cac_config_reg lcac_oland[] = …;

static const struct si_cac_config_reg lcac_mars_pro[] = …;

static const struct si_cac_config_reg cac_override_oland[] = …;

static const struct si_powertune_data powertune_data_oland = …;

static const struct si_powertune_data powertune_data_mars_pro = …;

static const struct si_dte_data dte_data_oland = …;

static const struct si_dte_data dte_data_mars_pro = …;

static const struct si_dte_data dte_data_sun_xt = …;


static const struct si_cac_config_reg cac_weights_hainan[] = …;

static const struct si_powertune_data powertune_data_hainan = …;

static int si_populate_voltage_value(struct radeon_device *rdev,
				     const struct atom_voltage_table *table,
				     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
static int si_get_std_voltage_value(struct radeon_device *rdev,
				    SISLANDS_SMC_VOLTAGE_VALUE *voltage,
				    u16 *std_voltage);
static int si_write_smc_soft_register(struct radeon_device *rdev,
				      u16 reg_offset, u32 value);
static int si_convert_power_level_to_smc(struct radeon_device *rdev,
					 struct rv7xx_pl *pl,
					 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
static int si_calculate_sclk_params(struct radeon_device *rdev,
				    u32 engine_clock,
				    SISLANDS_SMC_SCLK_VALUE *sclk);

static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);

static struct si_power_info *si_get_pi(struct radeon_device *rdev)
{ … }

static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
						     u16 v, s32 t, u32 ileakage, u32 *leakage)
{ … }

static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
					     const struct ni_leakage_coeffients *coeff,
					     u16 v,
					     s32 t,
					     u32 i_leakage,
					     u32 *leakage)
{ … }

static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
					       const u32 fixed_kt, u16 v,
					       u32 ileakage, u32 *leakage)
{ … }

static void si_calculate_leakage_for_v(struct radeon_device *rdev,
				       const struct ni_leakage_coeffients *coeff,
				       const u32 fixed_kt,
				       u16 v,
				       u32 i_leakage,
				       u32 *leakage)
{ … }


static void si_update_dte_from_pl2(struct radeon_device *rdev,
				   struct si_dte_data *dte_data)
{ … }

static void si_initialize_powertune_defaults(struct radeon_device *rdev)
{ … }

static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
{ … }

static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
{ … }

static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
{ … }

static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
					    bool adjust_polarity,
					    u32 tdp_adjustment,
					    u32 *tdp_limit,
					    u32 *near_tdp_limit)
{ … }

static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
				      struct radeon_ps *radeon_state)
{ … }

static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
					struct radeon_ps *radeon_state)
{ … }

static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
					       const u16 prev_std_vddc,
					       const u16 curr_std_vddc)
{ … }

static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
					    struct radeon_ps *radeon_state)
{ … }

static int si_populate_power_containment_values(struct radeon_device *rdev,
						struct radeon_ps *radeon_state,
						SISLANDS_SMC_SWSTATE *smc_state)
{ … }

static int si_populate_sq_ramping_values(struct radeon_device *rdev,
					 struct radeon_ps *radeon_state,
					 SISLANDS_SMC_SWSTATE *smc_state)
{ … }

static int si_enable_power_containment(struct radeon_device *rdev,
				       struct radeon_ps *radeon_new_state,
				       bool enable)
{ … }

static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
{ … }

static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
					  u16 *max, u16 *min)
{ … }

static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
{ … }

static int si_init_dte_leakage_table(struct radeon_device *rdev,
				     PP_SIslands_CacConfig *cac_tables,
				     u16 vddc_max, u16 vddc_min, u16 vddc_step,
				     u16 t0, u16 t_step)
{ … }

static int si_init_simplified_leakage_table(struct radeon_device *rdev,
					    PP_SIslands_CacConfig *cac_tables,
					    u16 vddc_max, u16 vddc_min, u16 vddc_step)
{ … }

static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
{ … }

static int si_program_cac_config_registers(struct radeon_device *rdev,
					   const struct si_cac_config_reg *cac_config_regs)
{ … }

static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
{ … }

static int si_enable_smc_cac(struct radeon_device *rdev,
			     struct radeon_ps *radeon_new_state,
			     bool enable)
{ … }

static int si_init_smc_spll_table(struct radeon_device *rdev)
{ … }

static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
						   u16 vce_voltage)
{ … }

static int si_get_vce_clock_voltage(struct radeon_device *rdev,
				    u32 evclk, u32 ecclk, u16 *voltage)
{ … }

static void si_apply_state_adjust_rules(struct radeon_device *rdev,
					struct radeon_ps *rps)
{ … }

#if 0
static int si_read_smc_soft_register(struct radeon_device *rdev,
				     u16 reg_offset, u32 *value)
{
	struct si_power_info *si_pi = si_get_pi(rdev);

	return si_read_smc_sram_dword(rdev,
				      si_pi->soft_regs_start + reg_offset, value,
				      si_pi->sram_end);
}
#endif

static int si_write_smc_soft_register(struct radeon_device *rdev,
				      u16 reg_offset, u32 value)
{ … }

static bool si_is_special_1gb_platform(struct radeon_device *rdev)
{ … }

static void si_get_leakage_vddc(struct radeon_device *rdev)
{ … }

static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
						     u32 index, u16 *leakage_voltage)
{ … }

static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
{ … }

static void si_enable_auto_throttle_source(struct radeon_device *rdev,
					   enum radeon_dpm_auto_throttle_src source,
					   bool enable)
{ … }

static void si_start_dpm(struct radeon_device *rdev)
{ … }

static void si_stop_dpm(struct radeon_device *rdev)
{ … }

static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
{ … }

#if 0
static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
					       u32 thermal_level)
{
	PPSMC_Result ret;

	if (thermal_level == 0) {
		ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
		if (ret == PPSMC_Result_OK)
			return 0;
		else
			return -EINVAL;
	}
	return 0;
}

static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
{
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
}
#endif

#if 0
static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
{
	if (ac_power)
		return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
			0 : -EINVAL;

	return 0;
}
#endif

static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
						      PPSMC_Msg msg, u32 parameter)
{ … }

static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
{ … }

int si_dpm_force_performance_level(struct radeon_device *rdev,
				   enum radeon_dpm_forced_level level)
{ … }

#if 0
static int si_set_boot_state(struct radeon_device *rdev)
{
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
		0 : -EINVAL;
}
#endif

static int si_set_sw_state(struct radeon_device *rdev)
{ … }

static int si_halt_smc(struct radeon_device *rdev)
{ … }

static int si_resume_smc(struct radeon_device *rdev)
{ … }

static void si_dpm_start_smc(struct radeon_device *rdev)
{ … }

static void si_dpm_stop_smc(struct radeon_device *rdev)
{ … }

static int si_process_firmware_header(struct radeon_device *rdev)
{ … }

static void si_read_clock_registers(struct radeon_device *rdev)
{ … }

static void si_enable_thermal_protection(struct radeon_device *rdev,
					  bool enable)
{ … }

static void si_enable_acpi_power_management(struct radeon_device *rdev)
{ … }

#if 0
static int si_enter_ulp_state(struct radeon_device *rdev)
{
	WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);

	udelay(25000);

	return 0;
}

static int si_exit_ulp_state(struct radeon_device *rdev)
{
	int i;

	WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);

	udelay(7000);

	for (i = 0; i < rdev->usec_timeout; i++) {
		if (RREG32(SMC_RESP_0) == 1)
			break;
		udelay(1000);
	}

	return 0;
}
#endif

static int si_notify_smc_display_change(struct radeon_device *rdev,
				     bool has_display)
{ … }

static void si_program_response_times(struct radeon_device *rdev)
{ … }

static void si_program_ds_registers(struct radeon_device *rdev)
{ … }

static void si_program_display_gap(struct radeon_device *rdev)
{ … }

static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
{ … }

static void si_setup_bsp(struct radeon_device *rdev)
{ … }

static void si_program_git(struct radeon_device *rdev)
{ … }

static void si_program_tp(struct radeon_device *rdev)
{ … }

static void si_program_tpp(struct radeon_device *rdev)
{ … }

static void si_program_sstp(struct radeon_device *rdev)
{ … }

static void si_enable_display_gap(struct radeon_device *rdev)
{ … }

static void si_program_vc(struct radeon_device *rdev)
{ … }

static void si_clear_vc(struct radeon_device *rdev)
{ … }

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
{ … }

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
{ … }

static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
{ … }

static int si_upload_firmware(struct radeon_device *rdev)
{ … }

static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
					      const struct atom_voltage_table *table,
					      const struct radeon_phase_shedding_limits_table *limits)
{ … }

void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
					      u32 max_voltage_steps,
					      struct atom_voltage_table *voltage_table)
{ … }

static int si_get_svi2_voltage_table(struct radeon_device *rdev,
				     struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
				     struct atom_voltage_table *voltage_table)
{ … }

static int si_construct_voltage_tables(struct radeon_device *rdev)
{ … }

static void si_populate_smc_voltage_table(struct radeon_device *rdev,
					  const struct atom_voltage_table *voltage_table,
					  SISLANDS_SMC_STATETABLE *table)
{ … }

static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
					  SISLANDS_SMC_STATETABLE *table)
{ … }

static int si_populate_voltage_value(struct radeon_device *rdev,
				     const struct atom_voltage_table *table,
				     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
{ … }

static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
				  SISLANDS_SMC_VOLTAGE_VALUE *voltage)
{ … }

static int si_get_std_voltage_value(struct radeon_device *rdev,
				    SISLANDS_SMC_VOLTAGE_VALUE *voltage,
				    u16 *std_voltage)
{ … }

static int si_populate_std_voltage_value(struct radeon_device *rdev,
					 u16 value, u8 index,
					 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
{ … }

static int si_populate_phase_shedding_value(struct radeon_device *rdev,
					    const struct radeon_phase_shedding_limits_table *limits,
					    u16 voltage, u32 sclk, u32 mclk,
					    SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
{ … }

static int si_init_arb_table_index(struct radeon_device *rdev)
{ … }

static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
{ … }

static int si_reset_to_default(struct radeon_device *rdev)
{ … }

static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
{ … }

static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
					    u32 engine_clock)
{ … }

static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
						struct rv7xx_pl *pl,
						SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
{ … }

static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
						  struct radeon_ps *radeon_state,
						  unsigned int first_arb_set)
{ … }

static int si_program_memory_timing_parameters(struct radeon_device *rdev,
					       struct radeon_ps *radeon_new_state)
{ … }

static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
					  struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
{ … }

static int si_populate_smc_initial_state(struct radeon_device *rdev,
					 struct radeon_ps *radeon_initial_state,
					 SISLANDS_SMC_STATETABLE *table)
{ … }

static int si_populate_smc_acpi_state(struct radeon_device *rdev,
				      SISLANDS_SMC_STATETABLE *table)
{ … }

static int si_populate_ulv_state(struct radeon_device *rdev,
				 struct SISLANDS_SMC_SWSTATE_SINGLE *state)
{ … }

static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
{ … }

static void si_get_mvdd_configuration(struct radeon_device *rdev)
{ … }

static int si_init_smc_table(struct radeon_device *rdev)
{ … }

static int si_calculate_sclk_params(struct radeon_device *rdev,
				    u32 engine_clock,
				    SISLANDS_SMC_SCLK_VALUE *sclk)
{ … }

static int si_populate_sclk_value(struct radeon_device *rdev,
				  u32 engine_clock,
				  SISLANDS_SMC_SCLK_VALUE *sclk)
{ … }

static int si_populate_mclk_value(struct radeon_device *rdev,
				  u32 engine_clock,
				  u32 memory_clock,
				  SISLANDS_SMC_MCLK_VALUE *mclk,
				  bool strobe_mode,
				  bool dll_state_on)
{ … }

static void si_populate_smc_sp(struct radeon_device *rdev,
			       struct radeon_ps *radeon_state,
			       SISLANDS_SMC_SWSTATE *smc_state)
{ … }

static int si_convert_power_level_to_smc(struct radeon_device *rdev,
					 struct rv7xx_pl *pl,
					 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
{ … }

static int si_populate_smc_t(struct radeon_device *rdev,
			     struct radeon_ps *radeon_state,
			     SISLANDS_SMC_SWSTATE *smc_state)
{ … }

static int si_disable_ulv(struct radeon_device *rdev)
{ … }

static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
				       struct radeon_ps *radeon_state)
{ … }

static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
						       struct radeon_ps *radeon_new_state)
{ … }

static int si_convert_power_state_to_smc(struct radeon_device *rdev,
					 struct radeon_ps *radeon_state,
					 SISLANDS_SMC_SWSTATE *smc_state)
{ … }

static int si_upload_sw_state(struct radeon_device *rdev,
			      struct radeon_ps *radeon_new_state)
{ … }

static int si_upload_ulv_state(struct radeon_device *rdev)
{ … }

static int si_upload_smc_data(struct radeon_device *rdev)
{ … }

static int si_set_mc_special_registers(struct radeon_device *rdev,
				       struct si_mc_reg_table *table)
{ … }

static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
{ … }

static void si_set_valid_flag(struct si_mc_reg_table *table)
{ … }

static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
{ … }

static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
				      struct si_mc_reg_table *si_table)
{ … }

static int si_initialize_mc_reg_table(struct radeon_device *rdev)
{ … }

static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
					 SMC_SIslands_MCRegisters *mc_reg_table)
{ … }

static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
				    SMC_SIslands_MCRegisterSet *data,
				    u32 num_entries, u32 valid_flag)
{ … }

static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
						 struct rv7xx_pl *pl,
						 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
{ … }

static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
					   struct radeon_ps *radeon_state,
					   SMC_SIslands_MCRegisters *mc_reg_table)
{ … }

static int si_populate_mc_reg_table(struct radeon_device *rdev,
				    struct radeon_ps *radeon_boot_state)
{ … }

static int si_upload_mc_reg_table(struct radeon_device *rdev,
				  struct radeon_ps *radeon_new_state)
{ … }

static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
{ … }

static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
						      struct radeon_ps *radeon_state)
{ … }

static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
{ … }

static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
							     struct radeon_ps *radeon_new_state,
							     struct radeon_ps *radeon_current_state)
{ … }

static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
							   struct radeon_ps *radeon_new_state,
							   struct radeon_ps *radeon_current_state)
{ … }

#if 0
static int si_ds_request(struct radeon_device *rdev,
			 bool ds_status_on, u32 count_write)
{
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);

	if (eg_pi->sclk_deep_sleep) {
		if (ds_status_on)
			return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
				PPSMC_Result_OK) ?
				0 : -EINVAL;
		else
			return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
				PPSMC_Result_OK) ? 0 : -EINVAL;
	}
	return 0;
}
#endif

static void si_set_max_cu_value(struct radeon_device *rdev)
{ … }

static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
							     struct radeon_clock_voltage_dependency_table *table)
{ … }

static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
{ … }

static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
					  struct radeon_ps *radeon_new_state,
					  struct radeon_ps *radeon_current_state)
{ … }

static void si_set_vce_clock(struct radeon_device *rdev,
			     struct radeon_ps *new_rps,
			     struct radeon_ps *old_rps)
{ … }

void si_dpm_setup_asic(struct radeon_device *rdev)
{ … }

static int si_thermal_enable_alert(struct radeon_device *rdev,
				   bool enable)
{ … }

static int si_thermal_set_temperature_range(struct radeon_device *rdev,
					    int min_temp, int max_temp)
{ … }

static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
{ … }

static int si_thermal_setup_fan_table(struct radeon_device *rdev)
{ … }

static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
{ … }

static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
{ … }

int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
				      u32 *speed)
{ … }

int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
				      u32 speed)
{ … }

void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
{ … }

u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
{ … }

#if 0
static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
					 u32 *speed)
{
	u32 tach_period;
	u32 xclk = radeon_get_xclk(rdev);

	if (rdev->pm.no_fan)
		return -ENOENT;

	if (rdev->pm.fan_pulses_per_revolution == 0)
		return -ENOENT;

	tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
	if (tach_period == 0)
		return -ENOENT;

	*speed = 60 * xclk * 10000 / tach_period;

	return 0;
}

static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
					 u32 speed)
{
	u32 tach_period, tmp;
	u32 xclk = radeon_get_xclk(rdev);

	if (rdev->pm.no_fan)
		return -ENOENT;

	if (rdev->pm.fan_pulses_per_revolution == 0)
		return -ENOENT;

	if ((speed < rdev->pm.fan_min_rpm) ||
	    (speed > rdev->pm.fan_max_rpm))
		return -EINVAL;

	if (rdev->pm.dpm.fan.ucode_fan_control)
		si_fan_ctrl_stop_smc_fan_control(rdev);

	tach_period = 60 * xclk * 10000 / (8 * speed);
	tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
	tmp |= TARGET_PERIOD(tach_period);
	WREG32(CG_TACH_CTRL, tmp);

	si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);

	return 0;
}
#endif

static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
{ … }

static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
{ … }

static void si_thermal_initialize(struct radeon_device *rdev)
{ … }

static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
{ … }

static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
{ … }

int si_dpm_enable(struct radeon_device *rdev)
{ … }

static int si_set_temperature_range(struct radeon_device *rdev)
{ … }

int si_dpm_late_enable(struct radeon_device *rdev)
{ … }

void si_dpm_disable(struct radeon_device *rdev)
{ … }

int si_dpm_pre_set_power_state(struct radeon_device *rdev)
{ … }

static int si_power_control_set_level(struct radeon_device *rdev)
{ … }

int si_dpm_set_power_state(struct radeon_device *rdev)
{ … }

void si_dpm_post_set_power_state(struct radeon_device *rdev)
{ … }

#if 0
void si_dpm_reset_asic(struct radeon_device *rdev)
{
	si_restrict_performance_levels_before_switch(rdev);
	si_disable_ulv(rdev);
	si_set_boot_state(rdev);
}
#endif

void si_dpm_display_configuration_changed(struct radeon_device *rdev)
{ … }

power_info;

pplib_clock_info;

pplib_power_state;

static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
					  struct radeon_ps *rps,
					  struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
					  u8 table_rev)
{ … }

static void si_parse_pplib_clock_info(struct radeon_device *rdev,
				      struct radeon_ps *rps, int index,
				      union pplib_clock_info *clock_info)
{ … }

static int si_parse_power_table(struct radeon_device *rdev)
{ … }

int si_dpm_init(struct radeon_device *rdev)
{ … }

void si_dpm_fini(struct radeon_device *rdev)
{ … }

void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
						    struct seq_file *m)
{ … }

u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
{ … }

u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
{ … }