/* * Copyright 2013 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __CI_DPM_H__ #define __CI_DPM_H__ #include "ppsmc.h" #include "radeon.h" #define SMU__NUM_SCLK_DPM_STATE … #define SMU__NUM_MCLK_DPM_LEVELS … #define SMU__NUM_LCLK_DPM_LEVELS … #define SMU__NUM_PCIE_DPM_LEVELS … #include "smu7_discrete.h" #define CISLANDS_MAX_HARDWARE_POWERLEVELS … #define CISLANDS_UNUSED_GPIO_PIN … struct ci_pl { … }; struct ci_ps { … }; struct ci_dpm_level { … }; #define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID … #define MAX_REGULAR_DPM_NUMBER … #define CISLAND_MINIMUM_ENGINE_CLOCK … struct ci_single_dpm_table { … }; struct ci_dpm_table { … }; struct ci_mc_reg_entry { … }; struct ci_mc_reg_table { … }; struct ci_ulv_parm { … }; #define CISLANDS_MAX_LEAKAGE_COUNT … struct ci_leakage_voltage { … }; struct ci_dpm_level_enable_mask { … }; struct ci_vbios_boot_state { … }; struct ci_clock_registers { … }; struct ci_thermal_temperature_setting { … }; struct ci_pcie_perf_range { … }; enum ci_pt_config_reg_type { … }; #define POWERCONTAINMENT_FEATURE_BAPM … #define POWERCONTAINMENT_FEATURE_TDCLimit … #define POWERCONTAINMENT_FEATURE_PkgPwrLimit … struct ci_pt_config_reg { … }; struct ci_pt_defaults { … }; #define DPMTABLE_OD_UPDATE_SCLK … #define DPMTABLE_OD_UPDATE_MCLK … #define DPMTABLE_UPDATE_SCLK … #define DPMTABLE_UPDATE_MCLK … struct ci_power_info { … }; #define CISLANDS_VOLTAGE_CONTROL_NONE … #define CISLANDS_VOLTAGE_CONTROL_BY_GPIO … #define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 … #define CISLANDS_Q88_FORMAT_CONVERSION_UNIT … #define CISLANDS_VRC_DFLT0 … #define CISLANDS_VRC_DFLT1 … #define CISLANDS_VRC_DFLT2 … #define CISLANDS_VRC_DFLT3 … #define CISLANDS_VRC_DFLT4 … #define CISLANDS_VRC_DFLT5 … #define CISLANDS_VRC_DFLT6 … #define CISLANDS_VRC_DFLT7 … #define CISLANDS_CGULVPARAMETER_DFLT … #define CISLAND_TARGETACTIVITY_DFLT … #define CISLAND_MCLK_TARGETACTIVITY_DFLT … #define PCIE_PERF_REQ_REMOVE_REGISTRY … #define PCIE_PERF_REQ_FORCE_LOWPOWER … #define PCIE_PERF_REQ_PECI_GEN1 … #define PCIE_PERF_REQ_PECI_GEN2 … #define PCIE_PERF_REQ_PECI_GEN3 … int ci_copy_bytes_to_smc(struct radeon_device *rdev, u32 smc_start_address, const u8 *src, u32 byte_count, u32 limit); void ci_start_smc(struct radeon_device *rdev); void ci_reset_smc(struct radeon_device *rdev); int ci_program_jump_on_start(struct radeon_device *rdev); void ci_stop_smc_clock(struct radeon_device *rdev); void ci_start_smc_clock(struct radeon_device *rdev); bool ci_is_smc_running(struct radeon_device *rdev); PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev); int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit); int ci_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, u32 *value, u32 limit); int ci_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, u32 value, u32 limit); #endif
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