/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/math64.h> #include <linux/pci.h> #include <linux/seq_file.h> #include "atom.h" #include "evergreen.h" #include "ni_dpm.h" #include "nid.h" #include "r600_dpm.h" #include "rv770.h" #include "radeon.h" #include "radeon_asic.h" #define MC_CG_ARB_FREQ_F0 … #define MC_CG_ARB_FREQ_F1 … #define MC_CG_ARB_FREQ_F2 … #define MC_CG_ARB_FREQ_F3 … #define SMC_RAM_END … static const struct ni_cac_weights cac_weights_cayman_xt = …; static const struct ni_cac_weights cac_weights_cayman_pro = …; static const struct ni_cac_weights cac_weights_cayman_le = …; #define NISLANDS_MGCG_SEQUENCE … static const u32 cayman_cgcg_cgls_default[] = …; #define CAYMAN_CGCG_CGLS_DEFAULT_LENGTH … static const u32 cayman_cgcg_cgls_disable[] = …; #define CAYMAN_CGCG_CGLS_DISABLE_LENGTH … static const u32 cayman_cgcg_cgls_enable[] = …; #define CAYMAN_CGCG_CGLS_ENABLE_LENGTH … static const u32 cayman_mgcg_default[] = …; #define CAYMAN_MGCG_DEFAULT_LENGTH … static const u32 cayman_mgcg_disable[] = …; #define CAYMAN_MGCG_DISABLE_LENGTH … static const u32 cayman_mgcg_enable[] = …; #define CAYMAN_MGCG_ENABLE_LENGTH … #define NISLANDS_SYSLS_SEQUENCE … static const u32 cayman_sysls_default[] = …; #define CAYMAN_SYSLS_DEFAULT_LENGTH … static const u32 cayman_sysls_disable[] = …; #define CAYMAN_SYSLS_DISABLE_LENGTH … static const u32 cayman_sysls_enable[] = …; #define CAYMAN_SYSLS_ENABLE_LENGTH … extern int ni_mc_load_microcode(struct radeon_device *rdev); struct ni_power_info *ni_get_pi(struct radeon_device *rdev) { … } struct ni_ps *ni_get_ps(struct radeon_ps *rps) { … } static void ni_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, u16 v, s32 t, u32 ileakage, u32 *leakage) { … } static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev, const struct ni_leakage_coeffients *coeff, u16 v, s32 t, u32 i_leakage, u32 *leakage) { … } bool ni_dpm_vblank_too_short(struct radeon_device *rdev) { … } static void ni_apply_state_adjust_rules(struct radeon_device *rdev, struct radeon_ps *rps) { … } static void ni_cg_clockgating_default(struct radeon_device *rdev) { … } static void ni_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) { … } static void ni_mg_clockgating_default(struct radeon_device *rdev) { … } static void ni_mg_clockgating_enable(struct radeon_device *rdev, bool enable) { … } static void ni_ls_clockgating_default(struct radeon_device *rdev) { … } static void ni_ls_clockgating_enable(struct radeon_device *rdev, bool enable) { … } static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, struct radeon_clock_voltage_dependency_table *table) { … } static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) { … } static void ni_stop_dpm(struct radeon_device *rdev) { … } #if 0 static int ni_notify_hw_of_power_source(struct radeon_device *rdev, bool ac_power) { if (ac_power) return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 0 : -EINVAL; return 0; } #endif static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev, PPSMC_Msg msg, u32 parameter) { … } static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev) { … } int ni_dpm_force_performance_level(struct radeon_device *rdev, enum radeon_dpm_forced_level level) { … } static void ni_stop_smc(struct radeon_device *rdev) { … } static int ni_process_firmware_header(struct radeon_device *rdev) { … } static void ni_read_clock_registers(struct radeon_device *rdev) { … } #if 0 static int ni_enter_ulp_state(struct radeon_device *rdev) { struct rv7xx_power_info *pi = rv770_get_pi(rdev); if (pi->gfx_clock_gating) { WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); RREG32(GB_ADDR_CONFIG); } WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), ~HOST_SMC_MSG_MASK); udelay(25000); return 0; } #endif static void ni_program_response_times(struct radeon_device *rdev) { … } static void ni_populate_smc_voltage_table(struct radeon_device *rdev, struct atom_voltage_table *voltage_table, NISLANDS_SMC_STATETABLE *table) { … } static void ni_populate_smc_voltage_tables(struct radeon_device *rdev, NISLANDS_SMC_STATETABLE *table) { … } static int ni_populate_voltage_value(struct radeon_device *rdev, struct atom_voltage_table *table, u16 value, NISLANDS_SMC_VOLTAGE_VALUE *voltage) { … } static void ni_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, NISLANDS_SMC_VOLTAGE_VALUE *voltage) { … } static int ni_get_std_voltage_value(struct radeon_device *rdev, NISLANDS_SMC_VOLTAGE_VALUE *voltage, u16 *std_voltage) { … } static void ni_populate_std_voltage_value(struct radeon_device *rdev, u16 value, u8 index, NISLANDS_SMC_VOLTAGE_VALUE *voltage) { … } static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev) { … } static u32 ni_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) { … } static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev, struct radeon_ps *radeon_state, u32 near_tdp_limit) { … } static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev, bool adjust_polarity, u32 tdp_adjustment, u32 *tdp_limit, u32 *near_tdp_limit) { … } static int ni_populate_smc_tdp_limits(struct radeon_device *rdev, struct radeon_ps *radeon_state) { … } int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, u32 arb_freq_src, u32 arb_freq_dest) { … } static int ni_init_arb_table_index(struct radeon_device *rdev) { … } static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) { … } static int ni_force_switch_to_arb_f0(struct radeon_device *rdev) { … } static int ni_populate_memory_timing_parameters(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs) { … } static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev, struct radeon_ps *radeon_state, unsigned int first_arb_set) { … } static int ni_program_memory_timing_parameters(struct radeon_device *rdev, struct radeon_ps *radeon_new_state) { … } static void ni_populate_initial_mvdd_value(struct radeon_device *rdev, struct NISLANDS_SMC_VOLTAGE_VALUE *voltage) { … } static int ni_populate_smc_initial_state(struct radeon_device *rdev, struct radeon_ps *radeon_initial_state, NISLANDS_SMC_STATETABLE *table) { … } static int ni_populate_smc_acpi_state(struct radeon_device *rdev, NISLANDS_SMC_STATETABLE *table) { … } static int ni_init_smc_table(struct radeon_device *rdev) { … } static int ni_calculate_sclk_params(struct radeon_device *rdev, u32 engine_clock, NISLANDS_SMC_SCLK_VALUE *sclk) { … } static int ni_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, NISLANDS_SMC_SCLK_VALUE *sclk) { … } static int ni_init_smc_spll_table(struct radeon_device *rdev) { … } static int ni_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, NISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) { … } static void ni_populate_smc_sp(struct radeon_device *rdev, struct radeon_ps *radeon_state, NISLANDS_SMC_SWSTATE *smc_state) { … } static int ni_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) { … } static int ni_populate_smc_t(struct radeon_device *rdev, struct radeon_ps *radeon_state, NISLANDS_SMC_SWSTATE *smc_state) { … } static int ni_populate_power_containment_values(struct radeon_device *rdev, struct radeon_ps *radeon_state, NISLANDS_SMC_SWSTATE *smc_state) { … } static int ni_populate_sq_ramping_values(struct radeon_device *rdev, struct radeon_ps *radeon_state, NISLANDS_SMC_SWSTATE *smc_state) { … } static int ni_enable_power_containment(struct radeon_device *rdev, struct radeon_ps *radeon_new_state, bool enable) { … } static int ni_convert_power_state_to_smc(struct radeon_device *rdev, struct radeon_ps *radeon_state, NISLANDS_SMC_SWSTATE *smc_state) { … } static int ni_upload_sw_state(struct radeon_device *rdev, struct radeon_ps *radeon_new_state) { … } static int ni_set_mc_special_registers(struct radeon_device *rdev, struct ni_mc_reg_table *table) { … } static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) { … } static void ni_set_valid_flag(struct ni_mc_reg_table *table) { … } static void ni_set_s0_mc_reg_index(struct ni_mc_reg_table *table) { … } static int ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, struct ni_mc_reg_table *ni_table) { … } static int ni_initialize_mc_reg_table(struct radeon_device *rdev) { … } static void ni_populate_mc_reg_addresses(struct radeon_device *rdev, SMC_NIslands_MCRegisters *mc_reg_table) { … } static void ni_convert_mc_registers(struct ni_mc_reg_entry *entry, SMC_NIslands_MCRegisterSet *data, u32 num_entries, u32 valid_flag) { … } static void ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_NIslands_MCRegisterSet *mc_reg_table_data) { … } static void ni_convert_mc_reg_table_to_smc(struct radeon_device *rdev, struct radeon_ps *radeon_state, SMC_NIslands_MCRegisters *mc_reg_table) { … } static int ni_populate_mc_reg_table(struct radeon_device *rdev, struct radeon_ps *radeon_boot_state) { … } static int ni_upload_mc_reg_table(struct radeon_device *rdev, struct radeon_ps *radeon_new_state) { … } static int ni_init_driver_calculated_leakage_table(struct radeon_device *rdev, PP_NIslands_CACTABLES *cac_tables) { … } static int ni_init_simplified_leakage_table(struct radeon_device *rdev, PP_NIslands_CACTABLES *cac_tables) { … } static int ni_initialize_smc_cac_tables(struct radeon_device *rdev) { … } static int ni_initialize_hardware_cac_manager(struct radeon_device *rdev) { … } static int ni_enable_smc_cac(struct radeon_device *rdev, struct radeon_ps *radeon_new_state, bool enable) { … } static int ni_pcie_performance_request(struct radeon_device *rdev, u8 perf_req, bool advertise) { … } static int ni_advertise_gen2_capability(struct radeon_device *rdev) { … } static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable) { … } static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable) { … } void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, struct radeon_ps *new_ps, struct radeon_ps *old_ps) { … } void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, struct radeon_ps *new_ps, struct radeon_ps *old_ps) { … } void ni_dpm_setup_asic(struct radeon_device *rdev) { … } void ni_update_current_ps(struct radeon_device *rdev, struct radeon_ps *rps) { … } void ni_update_requested_ps(struct radeon_device *rdev, struct radeon_ps *rps) { … } int ni_dpm_enable(struct radeon_device *rdev) { … } void ni_dpm_disable(struct radeon_device *rdev) { … } static int ni_power_control_set_level(struct radeon_device *rdev) { … } int ni_dpm_pre_set_power_state(struct radeon_device *rdev) { … } int ni_dpm_set_power_state(struct radeon_device *rdev) { … } void ni_dpm_post_set_power_state(struct radeon_device *rdev) { … } #if 0 void ni_dpm_reset_asic(struct radeon_device *rdev) { ni_restrict_performance_levels_before_switch(rdev); rv770_set_boot_state(rdev); } #endif power_info; pplib_clock_info; pplib_power_state; static void ni_parse_pplib_non_clock_info(struct radeon_device *rdev, struct radeon_ps *rps, struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, u8 table_rev) { … } static void ni_parse_pplib_clock_info(struct radeon_device *rdev, struct radeon_ps *rps, int index, union pplib_clock_info *clock_info) { … } static int ni_parse_power_table(struct radeon_device *rdev) { … } int ni_dpm_init(struct radeon_device *rdev) { … } void ni_dpm_fini(struct radeon_device *rdev) { … } void ni_dpm_print_power_state(struct radeon_device *rdev, struct radeon_ps *rps) { … } void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, struct seq_file *m) { … } u32 ni_dpm_get_current_sclk(struct radeon_device *rdev) { … } u32 ni_dpm_get_current_mclk(struct radeon_device *rdev) { … } u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low) { … } u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low) { … }
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