/* * Copyright 2013 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include <linux/pci.h> #include <linux/seq_file.h> #include "atom.h" #include "ci_dpm.h" #include "cik.h" #include "cikd.h" #include "r600_dpm.h" #include "radeon.h" #include "radeon_asic.h" #include "radeon_ucode.h" #include "si_dpm.h" #define MC_CG_ARB_FREQ_F0 … #define MC_CG_ARB_FREQ_F1 … #define MC_CG_ARB_FREQ_F2 … #define MC_CG_ARB_FREQ_F3 … #define SMC_RAM_END … #define VOLTAGE_SCALE … #define VOLTAGE_VID_OFFSET_SCALE1 … #define VOLTAGE_VID_OFFSET_SCALE2 … static const struct ci_pt_defaults defaults_hawaii_xt = …; static const struct ci_pt_defaults defaults_hawaii_pro = …; static const struct ci_pt_defaults defaults_bonaire_xt = …; static const struct ci_pt_defaults defaults_saturn_xt = …; static const struct ci_pt_config_reg didt_config_ci[] = …; extern u8 rv770_get_memory_module_index(struct radeon_device *rdev); extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, u32 arb_freq_src, u32 arb_freq_dest); static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, struct atom_voltage_table_entry *voltage_table, u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); static int ci_set_power_limit(struct radeon_device *rdev, u32 n); static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, u32 target_tdp); static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate); static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, PPSMC_Msg msg, u32 parameter); static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev); static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev); static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) { … } static struct ci_ps *ci_get_ps(struct radeon_ps *rps) { … } static void ci_initialize_powertune_defaults(struct radeon_device *rdev) { … } static u8 ci_convert_to_vid(u16 vddc) { … } static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) { … } static int ci_populate_vddc_vid(struct radeon_device *rdev) { … } static int ci_populate_svi_load_line(struct radeon_device *rdev) { … } static int ci_populate_tdc_limit(struct radeon_device *rdev) { … } static int ci_populate_dw8(struct radeon_device *rdev) { … } static int ci_populate_fuzzy_fan(struct radeon_device *rdev) { … } static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) { … } static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) { … } static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) { … } static int ci_populate_pm_base(struct radeon_device *rdev) { … } static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) { … } static int ci_program_pt_config_registers(struct radeon_device *rdev, const struct ci_pt_config_reg *cac_config_regs) { … } static int ci_enable_didt(struct radeon_device *rdev, bool enable) { … } static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) { … } static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) { … } static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev, bool enable) { … } static int ci_power_control_set_level(struct radeon_device *rdev) { … } void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) { … } bool ci_dpm_vblank_too_short(struct radeon_device *rdev) { … } static void ci_apply_state_adjust_rules(struct radeon_device *rdev, struct radeon_ps *rps) { … } static int ci_thermal_set_temperature_range(struct radeon_device *rdev, int min_temp, int max_temp) { … } static int ci_thermal_enable_alert(struct radeon_device *rdev, bool enable) { … } static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) { … } static int ci_thermal_setup_fan_table(struct radeon_device *rdev) { … } static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) { … } static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) { … } int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, u32 *speed) { … } int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, u32 speed) { … } void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) { … } u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev) { … } #if 0 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, u32 *speed) { u32 tach_period; u32 xclk = radeon_get_xclk(rdev); if (rdev->pm.no_fan) return -ENOENT; if (rdev->pm.fan_pulses_per_revolution == 0) return -ENOENT; tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; if (tach_period == 0) return -ENOENT; *speed = 60 * xclk * 10000 / tach_period; return 0; } static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, u32 speed) { u32 tach_period, tmp; u32 xclk = radeon_get_xclk(rdev); if (rdev->pm.no_fan) return -ENOENT; if (rdev->pm.fan_pulses_per_revolution == 0) return -ENOENT; if ((speed < rdev->pm.fan_min_rpm) || (speed > rdev->pm.fan_max_rpm)) return -EINVAL; if (rdev->pm.dpm.fan.ucode_fan_control) ci_fan_ctrl_stop_smc_fan_control(rdev); tach_period = 60 * xclk * 10000 / (8 * speed); tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; tmp |= TARGET_PERIOD(tach_period); WREG32_SMC(CG_TACH_CTRL, tmp); ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); return 0; } #endif static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev) { … } static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev) { … } static void ci_thermal_initialize(struct radeon_device *rdev) { … } static int ci_thermal_start_thermal_controller(struct radeon_device *rdev) { … } static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev) { … } #if 0 static int ci_read_smc_soft_register(struct radeon_device *rdev, u16 reg_offset, u32 *value) { struct ci_power_info *pi = ci_get_pi(rdev); return ci_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset, value, pi->sram_end); } #endif static int ci_write_smc_soft_register(struct radeon_device *rdev, u16 reg_offset, u32 value) { … } static void ci_init_fps_limits(struct radeon_device *rdev) { … } static int ci_update_sclk_t(struct radeon_device *rdev) { … } static void ci_get_leakage_voltages(struct radeon_device *rdev) { … } static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) { … } static void ci_enable_auto_throttle_source(struct radeon_device *rdev, enum radeon_dpm_auto_throttle_src source, bool enable) { … } static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) { … } static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) { … } static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) { … } static int ci_start_dpm(struct radeon_device *rdev) { … } static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) { … } static int ci_stop_dpm(struct radeon_device *rdev) { … } static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) { … } #if 0 static int ci_notify_hw_of_power_source(struct radeon_device *rdev, bool ac_power) { struct ci_power_info *pi = ci_get_pi(rdev); struct radeon_cac_tdp_table *cac_tdp_table = rdev->pm.dpm.dyn_state.cac_tdp_table; u32 power_limit; if (ac_power) power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); else power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); ci_set_power_limit(rdev, power_limit); if (pi->caps_automatic_dc_transition) { if (ac_power) ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC); else ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp); } return 0; } #endif static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg) { … } static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, PPSMC_Msg msg, u32 parameter) { … } static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, PPSMC_Msg msg, u32 *parameter) { … } static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) { … } static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) { … } static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) { … } static int ci_set_power_limit(struct radeon_device *rdev, u32 n) { … } static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, u32 target_tdp) { … } #if 0 static int ci_set_boot_state(struct radeon_device *rdev) { return ci_enable_sclk_mclk_dpm(rdev, false); } #endif static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) { … } static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) { … } static void ci_dpm_start_smc(struct radeon_device *rdev) { … } static void ci_dpm_stop_smc(struct radeon_device *rdev) { … } static int ci_process_firmware_header(struct radeon_device *rdev) { … } static void ci_read_clock_registers(struct radeon_device *rdev) { … } static void ci_init_sclk_t(struct radeon_device *rdev) { … } static void ci_enable_thermal_protection(struct radeon_device *rdev, bool enable) { … } static void ci_enable_acpi_power_management(struct radeon_device *rdev) { … } #if 0 static int ci_enter_ulp_state(struct radeon_device *rdev) { WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); udelay(25000); return 0; } static int ci_exit_ulp_state(struct radeon_device *rdev) { int i; WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); udelay(7000); for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32(SMC_RESP_0) == 1) break; udelay(1000); } return 0; } #endif static int ci_notify_smc_display_change(struct radeon_device *rdev, bool has_display) { … } static int ci_enable_ds_master_switch(struct radeon_device *rdev, bool enable) { … } static void ci_program_display_gap(struct radeon_device *rdev) { … } static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) { … } static void ci_program_sstp(struct radeon_device *rdev) { … } static void ci_enable_display_gap(struct radeon_device *rdev) { … } static void ci_program_vc(struct radeon_device *rdev) { … } static void ci_clear_vc(struct radeon_device *rdev) { … } static int ci_upload_firmware(struct radeon_device *rdev) { … } static int ci_get_svi2_voltage_table(struct radeon_device *rdev, struct radeon_clock_voltage_dependency_table *voltage_dependency_table, struct atom_voltage_table *voltage_table) { … } static int ci_construct_voltage_tables(struct radeon_device *rdev) { … } static void ci_populate_smc_voltage_table(struct radeon_device *rdev, struct atom_voltage_table_entry *voltage_table, SMU7_Discrete_VoltageLevel *smc_voltage_table) { … } static int ci_populate_smc_vddc_table(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_populate_smc_vddci_table(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, SMU7_Discrete_VoltageLevel *voltage) { … } static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, struct atom_voltage_table_entry *voltage_table, u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) { … } static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, const struct radeon_phase_shedding_limits_table *limits, u32 sclk, u32 *phase_shedding) { … } static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, const struct radeon_phase_shedding_limits_table *limits, u32 mclk, u32 *phase_shedding) { … } static int ci_init_arb_table_index(struct radeon_device *rdev) { … } static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table, u32 clock, u32 *voltage) { … } static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, u32 sclk, u32 min_sclk_in_sr) { … } static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) { … } static int ci_reset_to_default(struct radeon_device *rdev) { … } static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) { … } static void ci_register_patching_mc_arb(struct radeon_device *rdev, const u32 engine_clock, const u32 memory_clock, u32 *dram_timimg2) { … } static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, u32 sclk, u32 mclk, SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) { … } static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) { … } static int ci_program_memory_timing_parameters(struct radeon_device *rdev) { … } static void ci_populate_smc_initial_state(struct radeon_device *rdev, struct radeon_ps *radeon_boot_state) { … } static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) { … } static void ci_populate_smc_link_level(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_populate_smc_uvd_level(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_populate_smc_vce_level(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_populate_smc_acp_level(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_populate_smc_samu_level(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_calculate_mclk_params(struct radeon_device *rdev, u32 memory_clock, SMU7_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dll_state_on) { … } static int ci_populate_single_memory_level(struct radeon_device *rdev, u32 memory_clock, SMU7_Discrete_MemoryLevel *memory_level) { … } static int ci_populate_smc_acpi_level(struct radeon_device *rdev, SMU7_Discrete_DpmTable *table) { … } static int ci_enable_ulv(struct radeon_device *rdev, bool enable) { … } static int ci_populate_ulv_level(struct radeon_device *rdev, SMU7_Discrete_Ulv *state) { … } static int ci_calculate_sclk_params(struct radeon_device *rdev, u32 engine_clock, SMU7_Discrete_GraphicsLevel *sclk) { … } static int ci_populate_single_graphic_level(struct radeon_device *rdev, u32 engine_clock, u16 sclk_activity_level_t, SMU7_Discrete_GraphicsLevel *graphic_level) { … } static int ci_populate_all_graphic_levels(struct radeon_device *rdev) { … } static int ci_populate_ulv_state(struct radeon_device *rdev, SMU7_Discrete_Ulv *ulv_level) { … } static int ci_populate_all_memory_levels(struct radeon_device *rdev) { … } static void ci_reset_single_dpm_table(struct radeon_device *rdev, struct ci_single_dpm_table *dpm_table, u32 count) { … } static void ci_setup_pcie_table_entry(struct ci_single_dpm_table *dpm_table, u32 index, u32 pcie_gen, u32 pcie_lanes) { … } static int ci_setup_default_pcie_tables(struct radeon_device *rdev) { … } static int ci_setup_default_dpm_tables(struct radeon_device *rdev) { … } static int ci_find_boot_level(struct ci_single_dpm_table *table, u32 value, u32 *boot_level) { … } static int ci_init_smc_table(struct radeon_device *rdev) { … } static void ci_trim_single_dpm_states(struct radeon_device *rdev, struct ci_single_dpm_table *dpm_table, u32 low_limit, u32 high_limit) { … } static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, u32 speed_low, u32 lanes_low, u32 speed_high, u32 lanes_high) { … } static int ci_trim_dpm_states(struct radeon_device *rdev, struct radeon_ps *radeon_state) { … } static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) { … } static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) { … } static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, struct radeon_ps *radeon_state) { … } static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, struct radeon_ps *radeon_state) { … } static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) { … } static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) { … } #if 0 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable) { struct ci_power_info *pi = ci_get_pi(rdev); const struct radeon_clock_and_voltage_limits *max_limits; int i; if (rdev->pm.dpm.ac_power) max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; else max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; if (enable) { pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; if (!pi->caps_samu_dpm) break; } } ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SAMUDPM_SetEnabledMask, pi->dpm_level_enable_mask.samu_dpm_enable_mask); } return (ci_send_msg_to_smc(rdev, enable ? PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? 0 : -EINVAL; } static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable) { struct ci_power_info *pi = ci_get_pi(rdev); const struct radeon_clock_and_voltage_limits *max_limits; int i; if (rdev->pm.dpm.ac_power) max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; else max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; if (enable) { pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; if (!pi->caps_acp_dpm) break; } } ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_ACPDPM_SetEnabledMask, pi->dpm_level_enable_mask.acp_dpm_enable_mask); } return (ci_send_msg_to_smc(rdev, enable ? PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? 0 : -EINVAL; } #endif static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) { … } static u8 ci_get_vce_boot_level(struct radeon_device *rdev) { … } static int ci_update_vce_dpm(struct radeon_device *rdev, struct radeon_ps *radeon_new_state, struct radeon_ps *radeon_current_state) { … } #if 0 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate) { return ci_enable_samu_dpm(rdev, gate); } static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate) { struct ci_power_info *pi = ci_get_pi(rdev); u32 tmp; if (!gate) { pi->smc_state_table.AcpBootLevel = 0; tmp = RREG32_SMC(DPM_TABLE_475); tmp &= ~AcpBootLevel_MASK; tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); WREG32_SMC(DPM_TABLE_475, tmp); } return ci_enable_acp_dpm(rdev, !gate); } #endif static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, struct radeon_ps *radeon_state) { … } static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, u32 level_mask) { … } int ci_dpm_force_performance_level(struct radeon_device *rdev, enum radeon_dpm_forced_level level) { … } static int ci_set_mc_special_registers(struct radeon_device *rdev, struct ci_mc_reg_table *table) { … } static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) { … } static void ci_set_valid_flag(struct ci_mc_reg_table *table) { … } static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) { … } static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, struct ci_mc_reg_table *ci_table) { … } static int ci_register_patching_mc_seq(struct radeon_device *rdev, struct ci_mc_reg_table *table) { … } static int ci_initialize_mc_reg_table(struct radeon_device *rdev) { … } static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, SMU7_Discrete_MCRegisters *mc_reg_table) { … } static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, SMU7_Discrete_MCRegisterSet *data, u32 num_entries, u32 valid_flag) { … } static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, const u32 memory_clock, SMU7_Discrete_MCRegisterSet *mc_reg_table_data) { … } static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, SMU7_Discrete_MCRegisters *mc_reg_table) { … } static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) { … } static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) { … } static void ci_enable_voltage_control(struct radeon_device *rdev) { … } static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, struct radeon_ps *radeon_state) { … } static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) { … } static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) { … } static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, struct radeon_ps *radeon_new_state, struct radeon_ps *radeon_current_state) { … } static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, struct radeon_ps *radeon_new_state, struct radeon_ps *radeon_current_state) { … } static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) { … } static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) { … } static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) { … } static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, struct radeon_clock_voltage_dependency_table *table) { … } static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, struct radeon_clock_voltage_dependency_table *table) { … } static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, struct radeon_vce_clock_voltage_dependency_table *table) { … } static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, struct radeon_uvd_clock_voltage_dependency_table *table) { … } static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, struct radeon_phase_shedding_limits_table *table) { … } static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, struct radeon_clock_and_voltage_limits *table) { … } static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, struct radeon_cac_leakage_table *table) { … } static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) { … } static void ci_get_memory_type(struct radeon_device *rdev) { … } static void ci_update_current_ps(struct radeon_device *rdev, struct radeon_ps *rps) { … } static void ci_update_requested_ps(struct radeon_device *rdev, struct radeon_ps *rps) { … } int ci_dpm_pre_set_power_state(struct radeon_device *rdev) { … } void ci_dpm_post_set_power_state(struct radeon_device *rdev) { … } void ci_dpm_setup_asic(struct radeon_device *rdev) { … } int ci_dpm_enable(struct radeon_device *rdev) { … } static int ci_set_temperature_range(struct radeon_device *rdev) { … } int ci_dpm_late_enable(struct radeon_device *rdev) { … } void ci_dpm_disable(struct radeon_device *rdev) { … } int ci_dpm_set_power_state(struct radeon_device *rdev) { … } #if 0 void ci_dpm_reset_asic(struct radeon_device *rdev) { ci_set_boot_state(rdev); } #endif void ci_dpm_display_configuration_changed(struct radeon_device *rdev) { … } power_info; pplib_clock_info; pplib_power_state; static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, struct radeon_ps *rps, struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, u8 table_rev) { … } static void ci_parse_pplib_clock_info(struct radeon_device *rdev, struct radeon_ps *rps, int index, union pplib_clock_info *clock_info) { … } static int ci_parse_power_table(struct radeon_device *rdev) { … } static int ci_get_vbios_boot_values(struct radeon_device *rdev, struct ci_vbios_boot_state *boot_state) { … } void ci_dpm_fini(struct radeon_device *rdev) { … } int ci_dpm_init(struct radeon_device *rdev) { … } void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, struct seq_file *m) { … } void ci_dpm_print_power_state(struct radeon_device *rdev, struct radeon_ps *rps) { … } u32 ci_dpm_get_current_sclk(struct radeon_device *rdev) { … } u32 ci_dpm_get_current_mclk(struct radeon_device *rdev) { … } u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) { … } u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) { … }
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