/* * Copyright 2013 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #include <linux/firmware.h> #include "radeon.h" #include "radeon_ucode.h" #include "radeon_asic.h" #include "radeon_trace.h" #include "cik.h" #include "cikd.h" /* sdma */ #define CIK_SDMA_UCODE_SIZE … #define CIK_SDMA_UCODE_VERSION … /* * sDMA - System DMA * Starting with CIK, the GPU has new asynchronous * DMA engines. These engines are used for compute * and gfx. There are two DMA engines (SDMA0, SDMA1) * and each one supports 1 ring buffer used for gfx * and 2 queues used for compute. * * The programming model is very similar to the CP * (ring buffer, IBs, etc.), but sDMA has it's own * packet format that is different from the PM4 format * used by the CP. sDMA supports copying data, writing * embedded data, solid fills, and a number of other * things. It also has support for tiling/detiling of * buffers. */ /** * cik_sdma_get_rptr - get the current read pointer * * @rdev: radeon_device pointer * @ring: radeon ring pointer * * Get the current rptr from the hardware (CIK+). */ uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, struct radeon_ring *ring) { … } /** * cik_sdma_get_wptr - get the current write pointer * * @rdev: radeon_device pointer * @ring: radeon ring pointer * * Get the current wptr from the hardware (CIK+). */ uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, struct radeon_ring *ring) { … } /** * cik_sdma_set_wptr - commit the write pointer * * @rdev: radeon_device pointer * @ring: radeon ring pointer * * Write the wptr back to the hardware (CIK+). */ void cik_sdma_set_wptr(struct radeon_device *rdev, struct radeon_ring *ring) { … } /** * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine * * @rdev: radeon_device pointer * @ib: IB object to schedule * * Schedule an IB in the DMA ring (CIK). */ void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) { … } /** * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring * * @rdev: radeon_device pointer * @ridx: radeon ring index * * Emit an hdp flush packet on the requested DMA ring. */ static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, int ridx) { … } /** * cik_sdma_fence_ring_emit - emit a fence on the DMA ring * * @rdev: radeon_device pointer * @fence: radeon fence object * * Add a DMA fence packet to the ring to write * the fence seq number and DMA trap packet to generate * an interrupt if needed (CIK). */ void cik_sdma_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence) { … } /** * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring * * @rdev: radeon_device pointer * @ring: radeon_ring structure holding ring information * @semaphore: radeon semaphore object * @emit_wait: wait or signal semaphore * * Add a DMA semaphore packet to the ring wait on or signal * other rings (CIK). */ bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, struct radeon_ring *ring, struct radeon_semaphore *semaphore, bool emit_wait) { … } /** * cik_sdma_gfx_stop - stop the gfx async dma engines * * @rdev: radeon_device pointer * * Stop the gfx async dma ring buffers (CIK). */ static void cik_sdma_gfx_stop(struct radeon_device *rdev) { … } /** * cik_sdma_rlc_stop - stop the compute async dma engines * * @rdev: radeon_device pointer * * Stop the compute async dma queues (CIK). */ static void cik_sdma_rlc_stop(struct radeon_device *rdev) { … } /** * cik_sdma_ctx_switch_enable - enable/disable sdma engine preemption * * @rdev: radeon_device pointer * @enable: enable/disable preemption. * * Halt or unhalt the async dma engines (CIK). */ static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable) { … } /** * cik_sdma_enable - stop the async dma engines * * @rdev: radeon_device pointer * @enable: enable/disable the DMA MEs. * * Halt or unhalt the async dma engines (CIK). */ void cik_sdma_enable(struct radeon_device *rdev, bool enable) { … } /** * cik_sdma_gfx_resume - setup and start the async dma engines * * @rdev: radeon_device pointer * * Set up the gfx DMA ring buffers and enable them (CIK). * Returns 0 for success, error for failure. */ static int cik_sdma_gfx_resume(struct radeon_device *rdev) { … } /** * cik_sdma_rlc_resume - setup and start the async dma engines * * @rdev: radeon_device pointer * * Set up the compute DMA queues and enable them (CIK). * Returns 0 for success, error for failure. */ static int cik_sdma_rlc_resume(struct radeon_device *rdev) { … } /** * cik_sdma_load_microcode - load the sDMA ME ucode * * @rdev: radeon_device pointer * * Loads the sDMA0/1 ucode. * Returns 0 for success, -EINVAL if the ucode is not available. */ static int cik_sdma_load_microcode(struct radeon_device *rdev) { … } /** * cik_sdma_resume - setup and start the async dma engines * * @rdev: radeon_device pointer * * Set up the DMA engines and enable them (CIK). * Returns 0 for success, error for failure. */ int cik_sdma_resume(struct radeon_device *rdev) { … } /** * cik_sdma_fini - tear down the async dma engines * * @rdev: radeon_device pointer * * Stop the async dma engines and free the rings (CIK). */ void cik_sdma_fini(struct radeon_device *rdev) { … } /** * cik_copy_dma - copy pages using the DMA engine * * @rdev: radeon_device pointer * @src_offset: src GPU address * @dst_offset: dst GPU address * @num_gpu_pages: number of GPU pages to xfer * @resv: reservation object to sync to * * Copy GPU paging using the DMA engine (CIK). * Used by the radeon ttm implementation to move pages if * registered as the asic copy callback. */ struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, uint64_t src_offset, uint64_t dst_offset, unsigned num_gpu_pages, struct dma_resv *resv) { … } /** * cik_sdma_ring_test - simple async dma engine test * * @rdev: radeon_device pointer * @ring: radeon_ring structure holding ring information * * Test the DMA engine by writing using it to write an * value to memory. (CIK). * Returns 0 for success, error for failure. */ int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) { … } /** * cik_sdma_ib_test - test an IB on the DMA engine * * @rdev: radeon_device pointer * @ring: radeon_ring structure holding ring information * * Test a simple IB in the DMA ring (CIK). * Returns 0 on success, error on failure. */ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) { … } /** * cik_sdma_is_lockup - Check if the DMA engine is locked up * * @rdev: radeon_device pointer * @ring: radeon_ring structure holding ring information * * Check if the async DMA engine is locked up (CIK). * Returns true if the engine appears to be locked up, false if not. */ bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) { … } /** * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART * * @rdev: radeon_device pointer * @ib: indirect buffer to fill with commands * @pe: addr of the page entry * @src: src addr to copy from * @count: number of page entries to update * * Update PTEs by copying them from the GART using sDMA (CIK). */ void cik_sdma_vm_copy_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t src, unsigned count) { … } /** * cik_sdma_vm_write_pages - update PTEs by writing them manually * * @rdev: radeon_device pointer * @ib: indirect buffer to fill with commands * @pe: addr of the page entry * @addr: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes * @flags: access flags * * Update PTEs by writing them manually using sDMA (CIK). */ void cik_sdma_vm_write_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags) { … } /** * cik_sdma_vm_set_pages - update the page tables using sDMA * * @rdev: radeon_device pointer * @ib: indirect buffer to fill with commands * @pe: addr of the page entry * @addr: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes * @flags: access flags * * Update the page tables using sDMA (CIK). */ void cik_sdma_vm_set_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags) { … } /** * cik_sdma_vm_pad_ib - pad the IB to the required number of dw * * @ib: indirect buffer to fill with padding * */ void cik_sdma_vm_pad_ib(struct radeon_ib *ib) { … } /* * cik_dma_vm_flush - cik vm flush using sDMA * * Update the page table base and flush the VM TLB * using sDMA (CIK). */ void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, unsigned vm_id, uint64_t pd_addr) { … }
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