/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- * * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Fremont, California. * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Kevin E. Martin <[email protected]> * Gareth Hughes <[email protected]> * Keith Whitwell <[email protected]> */ #ifndef __AMDGPU_DRM_H__ #define __AMDGPU_DRM_H__ #include "drm.h" #if defined(__cplusplus) extern "C" { #endif #define DRM_AMDGPU_GEM_CREATE … #define DRM_AMDGPU_GEM_MMAP … #define DRM_AMDGPU_CTX … #define DRM_AMDGPU_BO_LIST … #define DRM_AMDGPU_CS … #define DRM_AMDGPU_INFO … #define DRM_AMDGPU_GEM_METADATA … #define DRM_AMDGPU_GEM_WAIT_IDLE … #define DRM_AMDGPU_GEM_VA … #define DRM_AMDGPU_WAIT_CS … #define DRM_AMDGPU_GEM_OP … #define DRM_AMDGPU_GEM_USERPTR … #define DRM_AMDGPU_WAIT_FENCES … #define DRM_AMDGPU_VM … #define DRM_AMDGPU_FENCE_TO_HANDLE … #define DRM_AMDGPU_SCHED … #define DRM_IOCTL_AMDGPU_GEM_CREATE … #define DRM_IOCTL_AMDGPU_GEM_MMAP … #define DRM_IOCTL_AMDGPU_CTX … #define DRM_IOCTL_AMDGPU_BO_LIST … #define DRM_IOCTL_AMDGPU_CS … #define DRM_IOCTL_AMDGPU_INFO … #define DRM_IOCTL_AMDGPU_GEM_METADATA … #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE … #define DRM_IOCTL_AMDGPU_GEM_VA … #define DRM_IOCTL_AMDGPU_WAIT_CS … #define DRM_IOCTL_AMDGPU_GEM_OP … #define DRM_IOCTL_AMDGPU_GEM_USERPTR … #define DRM_IOCTL_AMDGPU_WAIT_FENCES … #define DRM_IOCTL_AMDGPU_VM … #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE … #define DRM_IOCTL_AMDGPU_SCHED … /** * DOC: memory domains * * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. * Memory in this pool could be swapped out to disk if there is pressure. * * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the * GPU's virtual address space via gart. Gart memory linearizes non-contiguous * pages of system memory, allows GPU access system memory in a linearized * fashion. * * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory * carved out by the BIOS. * * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data * across shader threads. * * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the * execution of all the waves on a device. * * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines * for appending data. * * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for * signalling user mode queues. */ #define AMDGPU_GEM_DOMAIN_CPU … #define AMDGPU_GEM_DOMAIN_GTT … #define AMDGPU_GEM_DOMAIN_VRAM … #define AMDGPU_GEM_DOMAIN_GDS … #define AMDGPU_GEM_DOMAIN_GWS … #define AMDGPU_GEM_DOMAIN_OA … #define AMDGPU_GEM_DOMAIN_DOORBELL … #define AMDGPU_GEM_DOMAIN_MASK … /* Flag that CPU access will be required for the case of VRAM domain */ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED … /* Flag that CPU access will not work, this VRAM domain is invisible */ #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS … /* Flag that USWC attributes should be used for GTT */ #define AMDGPU_GEM_CREATE_CPU_GTT_USWC … /* Flag that the memory should be in VRAM and cleared */ #define AMDGPU_GEM_CREATE_VRAM_CLEARED … /* Flag that allocating the BO should use linear VRAM */ #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS … /* Flag that BO is always valid in this VM */ #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID … /* Flag that BO sharing will be explicitly synchronized */ #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC … /* Flag that indicates allocating MQD gart on GFX9, where the mtype * for the second page onward should be set to NC. It should never * be used by user space applications. */ #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 … /* Flag that BO may contain sensitive data that must be wiped before * releasing the memory */ #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE … /* Flag that BO will be encrypted and that the TMZ bit should be * set in the PTEs when mapping this buffer via GPUVM or * accessing it with various hw blocks */ #define AMDGPU_GEM_CREATE_ENCRYPTED … /* Flag that BO will be used only in preemptible context, which does * not require GTT memory accounting */ #define AMDGPU_GEM_CREATE_PREEMPTIBLE … /* Flag that BO can be discarded under memory pressure without keeping the * content. */ #define AMDGPU_GEM_CREATE_DISCARDABLE … /* Flag that BO is shared coherently between multiple devices or CPU threads. * May depend on GPU instructions to flush caches to system scope explicitly. * * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and * may override the MTYPE selected in AMDGPU_VA_OP_MAP. */ #define AMDGPU_GEM_CREATE_COHERENT … /* Flag that BO should not be cached by GPU. Coherent without having to flush * GPU caches explicitly * * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and * may override the MTYPE selected in AMDGPU_VA_OP_MAP. */ #define AMDGPU_GEM_CREATE_UNCACHED … /* Flag that BO should be coherent across devices when using device-level * atomics. May depend on GPU instructions to flush caches to device scope * explicitly, promoting them to system scope automatically. * * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and * may override the MTYPE selected in AMDGPU_VA_OP_MAP. */ #define AMDGPU_GEM_CREATE_EXT_COHERENT … /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ #define AMDGPU_GEM_CREATE_GFX12_DCC … struct drm_amdgpu_gem_create_in { … }; struct drm_amdgpu_gem_create_out { … }; drm_amdgpu_gem_create; /** Opcode to create new residency list. */ #define AMDGPU_BO_LIST_OP_CREATE … /** Opcode to destroy previously created residency list */ #define AMDGPU_BO_LIST_OP_DESTROY … /** Opcode to update resource information in the list */ #define AMDGPU_BO_LIST_OP_UPDATE … struct drm_amdgpu_bo_list_in { … }; struct drm_amdgpu_bo_list_entry { … }; struct drm_amdgpu_bo_list_out { … }; drm_amdgpu_bo_list; /* context related */ #define AMDGPU_CTX_OP_ALLOC_CTX … #define AMDGPU_CTX_OP_FREE_CTX … #define AMDGPU_CTX_OP_QUERY_STATE … #define AMDGPU_CTX_OP_QUERY_STATE2 … #define AMDGPU_CTX_OP_GET_STABLE_PSTATE … #define AMDGPU_CTX_OP_SET_STABLE_PSTATE … /* GPU reset status */ #define AMDGPU_CTX_NO_RESET … /* this the context caused it */ #define AMDGPU_CTX_GUILTY_RESET … /* some other context caused it */ #define AMDGPU_CTX_INNOCENT_RESET … /* unknown cause */ #define AMDGPU_CTX_UNKNOWN_RESET … /* indicate gpu reset occurred after ctx created */ #define AMDGPU_CTX_QUERY2_FLAGS_RESET … /* indicate vram lost occurred after ctx created */ #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST … /* indicate some job from this context once cause gpu hang */ #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY … /* indicate some errors are detected by RAS */ #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE … #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE … /* indicate that the reset hasn't completed yet */ #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS … /* Context priority level */ #define AMDGPU_CTX_PRIORITY_UNSET … #define AMDGPU_CTX_PRIORITY_VERY_LOW … #define AMDGPU_CTX_PRIORITY_LOW … #define AMDGPU_CTX_PRIORITY_NORMAL … /* * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires * CAP_SYS_NICE or DRM_MASTER */ #define AMDGPU_CTX_PRIORITY_HIGH … #define AMDGPU_CTX_PRIORITY_VERY_HIGH … /* select a stable profiling pstate for perfmon tools */ #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK … #define AMDGPU_CTX_STABLE_PSTATE_NONE … #define AMDGPU_CTX_STABLE_PSTATE_STANDARD … #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK … #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK … #define AMDGPU_CTX_STABLE_PSTATE_PEAK … struct drm_amdgpu_ctx_in { … }; drm_amdgpu_ctx_out; drm_amdgpu_ctx; /* vm ioctl */ #define AMDGPU_VM_OP_RESERVE_VMID … #define AMDGPU_VM_OP_UNRESERVE_VMID … struct drm_amdgpu_vm_in { … }; struct drm_amdgpu_vm_out { … }; drm_amdgpu_vm; /* sched ioctl */ #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE … #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE … struct drm_amdgpu_sched_in { … }; drm_amdgpu_sched; /* * This is not a reliable API and you should expect it to fail for any * number of reasons and have fallback path that do not use userptr to * perform any operation. */ #define AMDGPU_GEM_USERPTR_READONLY … #define AMDGPU_GEM_USERPTR_ANONONLY … #define AMDGPU_GEM_USERPTR_VALIDATE … #define AMDGPU_GEM_USERPTR_REGISTER … struct drm_amdgpu_gem_userptr { … }; /* SI-CI-VI: */ /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT … #define AMDGPU_TILING_ARRAY_MODE_MASK … #define AMDGPU_TILING_PIPE_CONFIG_SHIFT … #define AMDGPU_TILING_PIPE_CONFIG_MASK … #define AMDGPU_TILING_TILE_SPLIT_SHIFT … #define AMDGPU_TILING_TILE_SPLIT_MASK … #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT … #define AMDGPU_TILING_MICRO_TILE_MODE_MASK … #define AMDGPU_TILING_BANK_WIDTH_SHIFT … #define AMDGPU_TILING_BANK_WIDTH_MASK … #define AMDGPU_TILING_BANK_HEIGHT_SHIFT … #define AMDGPU_TILING_BANK_HEIGHT_MASK … #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT … #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK … #define AMDGPU_TILING_NUM_BANKS_SHIFT … #define AMDGPU_TILING_NUM_BANKS_MASK … /* GFX9 - GFX11: */ #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT … #define AMDGPU_TILING_SWIZZLE_MODE_MASK … #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT … #define AMDGPU_TILING_DCC_OFFSET_256B_MASK … #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT … #define AMDGPU_TILING_DCC_PITCH_MAX_MASK … #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT … #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK … #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT … #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK … #define AMDGPU_TILING_SCANOUT_SHIFT … #define AMDGPU_TILING_SCANOUT_MASK … /* GFX12 and later: */ #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT … #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK … /* These are DCC recompression setting for memory management: */ #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT … #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK … #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT … #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK … #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT … #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK … /* Set/Get helpers for tiling flags. */ #define AMDGPU_TILING_SET(field, value) … #define AMDGPU_TILING_GET(value, field) … #define AMDGPU_GEM_METADATA_OP_SET_METADATA … #define AMDGPU_GEM_METADATA_OP_GET_METADATA … /** The same structure is shared for input/output */ struct drm_amdgpu_gem_metadata { … }; struct drm_amdgpu_gem_mmap_in { … }; struct drm_amdgpu_gem_mmap_out { … }; drm_amdgpu_gem_mmap; struct drm_amdgpu_gem_wait_idle_in { … }; struct drm_amdgpu_gem_wait_idle_out { … }; drm_amdgpu_gem_wait_idle; struct drm_amdgpu_wait_cs_in { … }; struct drm_amdgpu_wait_cs_out { … }; drm_amdgpu_wait_cs; struct drm_amdgpu_fence { … }; struct drm_amdgpu_wait_fences_in { … }; struct drm_amdgpu_wait_fences_out { … }; drm_amdgpu_wait_fences; #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO … #define AMDGPU_GEM_OP_SET_PLACEMENT … /* Sets or returns a value associated with a buffer. */ struct drm_amdgpu_gem_op { … }; #define AMDGPU_VA_OP_MAP … #define AMDGPU_VA_OP_UNMAP … #define AMDGPU_VA_OP_CLEAR … #define AMDGPU_VA_OP_REPLACE … /* Delay the page table update till the next CS */ #define AMDGPU_VM_DELAY_UPDATE … /* Mapping flags */ /* readable mapping */ #define AMDGPU_VM_PAGE_READABLE … /* writable mapping */ #define AMDGPU_VM_PAGE_WRITEABLE … /* executable mapping, new for VI */ #define AMDGPU_VM_PAGE_EXECUTABLE … /* partially resident texture */ #define AMDGPU_VM_PAGE_PRT … /* MTYPE flags use bit 5 to 8 */ #define AMDGPU_VM_MTYPE_MASK … /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ #define AMDGPU_VM_MTYPE_DEFAULT … /* Use Non Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_NC … /* Use Write Combine MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_WC … /* Use Cache Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_CC … /* Use UnCached MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_UC … /* Use Read Write MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_RW … /* don't allocate MALL */ #define AMDGPU_VM_PAGE_NOALLOC … struct drm_amdgpu_gem_va { … }; #define AMDGPU_HW_IP_GFX … #define AMDGPU_HW_IP_COMPUTE … #define AMDGPU_HW_IP_DMA … #define AMDGPU_HW_IP_UVD … #define AMDGPU_HW_IP_VCE … #define AMDGPU_HW_IP_UVD_ENC … #define AMDGPU_HW_IP_VCN_DEC … /* * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support * both encoding and decoding jobs. */ #define AMDGPU_HW_IP_VCN_ENC … #define AMDGPU_HW_IP_VCN_JPEG … #define AMDGPU_HW_IP_VPE … #define AMDGPU_HW_IP_NUM … #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT … #define AMDGPU_CHUNK_ID_IB … #define AMDGPU_CHUNK_ID_FENCE … #define AMDGPU_CHUNK_ID_DEPENDENCIES … #define AMDGPU_CHUNK_ID_SYNCOBJ_IN … #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT … #define AMDGPU_CHUNK_ID_BO_HANDLES … #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES … #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT … #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL … #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW … struct drm_amdgpu_cs_chunk { … }; struct drm_amdgpu_cs_in { … }; struct drm_amdgpu_cs_out { … }; drm_amdgpu_cs; /* Specify flags to be used for IB */ /* This IB should be submitted to CE */ #define AMDGPU_IB_FLAG_CE … /* Preamble flag, which means the IB could be dropped if no context switch */ #define AMDGPU_IB_FLAG_PREAMBLE … /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ #define AMDGPU_IB_FLAG_PREEMPT … /* The IB fence should do the L2 writeback but not invalidate any shader * caches (L2/vL1/sL1/I$). */ #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE … /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. * This will reset wave ID counters for the IB. */ #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID … /* Flag the IB as secure (TMZ) */ #define AMDGPU_IB_FLAGS_SECURE … /* Tell KMD to flush and invalidate caches */ #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC … struct drm_amdgpu_cs_chunk_ib { … }; struct drm_amdgpu_cs_chunk_dep { … }; struct drm_amdgpu_cs_chunk_fence { … }; struct drm_amdgpu_cs_chunk_sem { … }; struct drm_amdgpu_cs_chunk_syncobj { … }; #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ … #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD … #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD … drm_amdgpu_fence_to_handle; struct drm_amdgpu_cs_chunk_data { … }; #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW … struct drm_amdgpu_cs_chunk_cp_gfx_shadow { … }; /* * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU * */ #define AMDGPU_IDS_FLAGS_FUSION … #define AMDGPU_IDS_FLAGS_PREEMPTION … #define AMDGPU_IDS_FLAGS_TMZ … #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD … /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING … /* get the crtc_id from the mode object id? */ #define AMDGPU_INFO_CRTC_FROM_ID … /* query hw IP info */ #define AMDGPU_INFO_HW_IP_INFO … /* query hw IP instance count for the specified type */ #define AMDGPU_INFO_HW_IP_COUNT … /* timestamp for GL_ARB_timer_query */ #define AMDGPU_INFO_TIMESTAMP … /* Query the firmware version */ #define AMDGPU_INFO_FW_VERSION … /* Subquery id: Query VCE firmware version */ #define AMDGPU_INFO_FW_VCE … /* Subquery id: Query UVD firmware version */ #define AMDGPU_INFO_FW_UVD … /* Subquery id: Query GMC firmware version */ #define AMDGPU_INFO_FW_GMC … /* Subquery id: Query GFX ME firmware version */ #define AMDGPU_INFO_FW_GFX_ME … /* Subquery id: Query GFX PFP firmware version */ #define AMDGPU_INFO_FW_GFX_PFP … /* Subquery id: Query GFX CE firmware version */ #define AMDGPU_INFO_FW_GFX_CE … /* Subquery id: Query GFX RLC firmware version */ #define AMDGPU_INFO_FW_GFX_RLC … /* Subquery id: Query GFX MEC firmware version */ #define AMDGPU_INFO_FW_GFX_MEC … /* Subquery id: Query SMC firmware version */ #define AMDGPU_INFO_FW_SMC … /* Subquery id: Query SDMA firmware version */ #define AMDGPU_INFO_FW_SDMA … /* Subquery id: Query PSP SOS firmware version */ #define AMDGPU_INFO_FW_SOS … /* Subquery id: Query PSP ASD firmware version */ #define AMDGPU_INFO_FW_ASD … /* Subquery id: Query VCN firmware version */ #define AMDGPU_INFO_FW_VCN … /* Subquery id: Query GFX RLC SRLC firmware version */ #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL … /* Subquery id: Query GFX RLC SRLG firmware version */ #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM … /* Subquery id: Query GFX RLC SRLS firmware version */ #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM … /* Subquery id: Query DMCU firmware version */ #define AMDGPU_INFO_FW_DMCU … #define AMDGPU_INFO_FW_TA … /* Subquery id: Query DMCUB firmware version */ #define AMDGPU_INFO_FW_DMCUB … /* Subquery id: Query TOC firmware version */ #define AMDGPU_INFO_FW_TOC … /* Subquery id: Query CAP firmware version */ #define AMDGPU_INFO_FW_CAP … /* Subquery id: Query GFX RLCP firmware version */ #define AMDGPU_INFO_FW_GFX_RLCP … /* Subquery id: Query GFX RLCV firmware version */ #define AMDGPU_INFO_FW_GFX_RLCV … /* Subquery id: Query MES_KIQ firmware version */ #define AMDGPU_INFO_FW_MES_KIQ … /* Subquery id: Query MES firmware version */ #define AMDGPU_INFO_FW_MES … /* Subquery id: Query IMU firmware version */ #define AMDGPU_INFO_FW_IMU … /* Subquery id: Query VPE firmware version */ #define AMDGPU_INFO_FW_VPE … /* number of bytes moved for TTM migration */ #define AMDGPU_INFO_NUM_BYTES_MOVED … /* the used VRAM size */ #define AMDGPU_INFO_VRAM_USAGE … /* the used GTT size */ #define AMDGPU_INFO_GTT_USAGE … /* Information about GDS, etc. resource configuration */ #define AMDGPU_INFO_GDS_CONFIG … /* Query information about VRAM and GTT domains */ #define AMDGPU_INFO_VRAM_GTT … /* Query information about register in MMR address space*/ #define AMDGPU_INFO_READ_MMR_REG … /* Query information about device: rev id, family, etc. */ #define AMDGPU_INFO_DEV_INFO … /* visible vram usage */ #define AMDGPU_INFO_VIS_VRAM_USAGE … /* number of TTM buffer evictions */ #define AMDGPU_INFO_NUM_EVICTIONS … /* Query memory about VRAM and GTT domains */ #define AMDGPU_INFO_MEMORY … /* Query vce clock table */ #define AMDGPU_INFO_VCE_CLOCK_TABLE … /* Query vbios related information */ #define AMDGPU_INFO_VBIOS … /* Subquery id: Query vbios size */ #define AMDGPU_INFO_VBIOS_SIZE … /* Subquery id: Query vbios image */ #define AMDGPU_INFO_VBIOS_IMAGE … /* Subquery id: Query vbios info */ #define AMDGPU_INFO_VBIOS_INFO … /* Query UVD handles */ #define AMDGPU_INFO_NUM_HANDLES … /* Query sensor related information */ #define AMDGPU_INFO_SENSOR … /* Subquery id: Query GPU shader clock */ #define AMDGPU_INFO_SENSOR_GFX_SCLK … /* Subquery id: Query GPU memory clock */ #define AMDGPU_INFO_SENSOR_GFX_MCLK … /* Subquery id: Query GPU temperature */ #define AMDGPU_INFO_SENSOR_GPU_TEMP … /* Subquery id: Query GPU load */ #define AMDGPU_INFO_SENSOR_GPU_LOAD … /* Subquery id: Query average GPU power */ #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER … /* Subquery id: Query northbridge voltage */ #define AMDGPU_INFO_SENSOR_VDDNB … /* Subquery id: Query graphics voltage */ #define AMDGPU_INFO_SENSOR_VDDGFX … /* Subquery id: Query GPU stable pstate shader clock */ #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK … /* Subquery id: Query GPU stable pstate memory clock */ #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK … /* Subquery id: Query GPU peak pstate shader clock */ #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK … /* Subquery id: Query GPU peak pstate memory clock */ #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK … /* Subquery id: Query input GPU power */ #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER … /* Number of VRAM page faults on CPU access. */ #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS … #define AMDGPU_INFO_VRAM_LOST_COUNTER … /* query ras mask of enabled features*/ #define AMDGPU_INFO_RAS_ENABLED_FEATURES … /* RAS MASK: UMC (VRAM) */ #define AMDGPU_INFO_RAS_ENABLED_UMC … /* RAS MASK: SDMA */ #define AMDGPU_INFO_RAS_ENABLED_SDMA … /* RAS MASK: GFX */ #define AMDGPU_INFO_RAS_ENABLED_GFX … /* RAS MASK: MMHUB */ #define AMDGPU_INFO_RAS_ENABLED_MMHUB … /* RAS MASK: ATHUB */ #define AMDGPU_INFO_RAS_ENABLED_ATHUB … /* RAS MASK: PCIE */ #define AMDGPU_INFO_RAS_ENABLED_PCIE … /* RAS MASK: HDP */ #define AMDGPU_INFO_RAS_ENABLED_HDP … /* RAS MASK: XGMI */ #define AMDGPU_INFO_RAS_ENABLED_XGMI … /* RAS MASK: DF */ #define AMDGPU_INFO_RAS_ENABLED_DF … /* RAS MASK: SMN */ #define AMDGPU_INFO_RAS_ENABLED_SMN … /* RAS MASK: SEM */ #define AMDGPU_INFO_RAS_ENABLED_SEM … /* RAS MASK: MP0 */ #define AMDGPU_INFO_RAS_ENABLED_MP0 … /* RAS MASK: MP1 */ #define AMDGPU_INFO_RAS_ENABLED_MP1 … /* RAS MASK: FUSE */ #define AMDGPU_INFO_RAS_ENABLED_FUSE … /* query video encode/decode caps */ #define AMDGPU_INFO_VIDEO_CAPS … /* Subquery id: Decode */ #define AMDGPU_INFO_VIDEO_CAPS_DECODE … /* Subquery id: Encode */ #define AMDGPU_INFO_VIDEO_CAPS_ENCODE … /* Query the max number of IBs per gang per submission */ #define AMDGPU_INFO_MAX_IBS … /* query last page fault info */ #define AMDGPU_INFO_GPUVM_FAULT … #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT … #define AMDGPU_INFO_MMR_SE_INDEX_MASK … #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT … #define AMDGPU_INFO_MMR_SH_INDEX_MASK … struct drm_amdgpu_query_fw { … }; /* Input structure for the INFO ioctl */ struct drm_amdgpu_info { … }; struct drm_amdgpu_info_gds { … }; struct drm_amdgpu_info_vram_gtt { … }; struct drm_amdgpu_heap_info { … }; struct drm_amdgpu_memory_info { … }; struct drm_amdgpu_info_firmware { … }; struct drm_amdgpu_info_vbios { … }; #define AMDGPU_VRAM_TYPE_UNKNOWN … #define AMDGPU_VRAM_TYPE_GDDR1 … #define AMDGPU_VRAM_TYPE_DDR2 … #define AMDGPU_VRAM_TYPE_GDDR3 … #define AMDGPU_VRAM_TYPE_GDDR4 … #define AMDGPU_VRAM_TYPE_GDDR5 … #define AMDGPU_VRAM_TYPE_HBM … #define AMDGPU_VRAM_TYPE_DDR3 … #define AMDGPU_VRAM_TYPE_DDR4 … #define AMDGPU_VRAM_TYPE_GDDR6 … #define AMDGPU_VRAM_TYPE_DDR5 … #define AMDGPU_VRAM_TYPE_LPDDR4 … #define AMDGPU_VRAM_TYPE_LPDDR5 … struct drm_amdgpu_info_device { … }; struct drm_amdgpu_info_hw_ip { … }; struct drm_amdgpu_info_num_handles { … }; #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES … struct drm_amdgpu_info_vce_clock_table_entry { … }; struct drm_amdgpu_info_vce_clock_table { … }; /* query video encode/decode caps */ #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 … #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 … #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 … #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC … #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC … #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG … #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 … #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 … #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT … struct drm_amdgpu_info_video_codec_info { … }; struct drm_amdgpu_info_video_caps { … }; #define AMDGPU_VMHUB_TYPE_MASK … #define AMDGPU_VMHUB_TYPE_SHIFT … #define AMDGPU_VMHUB_TYPE_GFX … #define AMDGPU_VMHUB_TYPE_MM0 … #define AMDGPU_VMHUB_TYPE_MM1 … #define AMDGPU_VMHUB_IDX_MASK … #define AMDGPU_VMHUB_IDX_SHIFT … struct drm_amdgpu_info_gpuvm_fault { … }; /* * Supported GPU families */ #define AMDGPU_FAMILY_UNKNOWN … #define AMDGPU_FAMILY_SI … #define AMDGPU_FAMILY_CI … #define AMDGPU_FAMILY_KV … #define AMDGPU_FAMILY_VI … #define AMDGPU_FAMILY_CZ … #define AMDGPU_FAMILY_AI … #define AMDGPU_FAMILY_RV … #define AMDGPU_FAMILY_NV … #define AMDGPU_FAMILY_VGH … #define AMDGPU_FAMILY_GC_11_0_0 … #define AMDGPU_FAMILY_YC … #define AMDGPU_FAMILY_GC_11_0_1 … #define AMDGPU_FAMILY_GC_10_3_6 … #define AMDGPU_FAMILY_GC_10_3_7 … #define AMDGPU_FAMILY_GC_11_5_0 … #define AMDGPU_FAMILY_GC_12_0_0 … /* FIXME wrong namespace! */ struct drm_color_ctm_3x4 { … }; #if defined(__cplusplus) } #endif #endif
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