/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * */ #ifndef _AMDGPU_RAS_H #define _AMDGPU_RAS_H #include <linux/debugfs.h> #include <linux/list.h> #include <linux/kfifo.h> #include <linux/radix-tree.h> #include <linux/siphash.h> #include "ta_ras_if.h" #include "amdgpu_ras_eeprom.h" #include "amdgpu_smuio.h" #include "amdgpu_aca.h" struct amdgpu_iv_entry; #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) … #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) … #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) … #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) … #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) … #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) … #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) … #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) … #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) … #define AMDGPU_RAS_GPU_ERR_AID_ID(x) … #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) … #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT … #define AMDGPU_RAS_BOOT_STEADY_STATUS … #define AMDGPU_RAS_BOOT_STATUS_MASK … #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS … /* position of instance value in sub_block_index of * ta_ras_trigger_error_input, the sub block uses lower 12 bits */ #define AMDGPU_RAS_INST_MASK … #define AMDGPU_RAS_INST_SHIFT … #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT … #define AMDGPU_RAS_FEATURES_SOCKETID_MASK … /* Reserve 8 physical dram row for possible retirement. * In worst cases, it will lose 8 * 2MB memory in vram domain */ #define AMDGPU_RAS_RESERVED_VRAM_SIZE … /* The high three bits indicates socketid */ #define AMDGPU_RAS_GET_FEATURES(val) … #define RAS_EVENT_INVALID_ID … #define RAS_EVENT_ID_IS_VALID(x) … #define RAS_EVENT_LOG(adev, id, fmt, ...) … #define amdgpu_ras_mark_ras_event(adev, type) … enum amdgpu_ras_block { … }; enum amdgpu_ras_mca_block { … }; #define AMDGPU_RAS_BLOCK_COUNT … #define AMDGPU_RAS_MCA_BLOCK_COUNT … #define AMDGPU_RAS_BLOCK_MASK … enum amdgpu_ras_gfx_subblock { … }; enum amdgpu_ras_error_type { … }; enum amdgpu_ras_ret { … }; enum amdgpu_ras_error_query_mode { … }; /* ras error status reisger fields */ #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT … #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK … #define ERR_STATUS_LO__MEMORY_ID__SHIFT … #define ERR_STATUS_LO__MEMORY_ID_MASK … #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT … #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK … #define ERR_STATUS__ERR_CNT__SHIFT … #define ERR_STATUS__ERR_CNT_MASK … #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) … #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) … #define AMDGPU_RAS_ERR_INFO_VALID … #define AMDGPU_RAS_ERR_STATUS_VALID … #define AMDGPU_RAS_ERR_ADDRESS_VALID … #define AMDGPU_RAS_GPU_RESET_MODE2_RESET … #define AMDGPU_RAS_GPU_RESET_MODE1_RESET … struct amdgpu_ras_err_status_reg_entry { … }; struct amdgpu_ras_memory_id_entry { … }; struct ras_common_if { … }; #define MAX_UMC_CHANNEL_NUM … struct ecc_info_per_ch { … }; struct umc_ecc_info { … }; enum ras_event_type { … }; struct ras_event_state { … }; struct ras_event_manager { … }; struct ras_event_id { … }; struct ras_query_context { … }; pasid_notify; struct ras_poison_msg { … }; struct ras_err_pages { … }; struct ras_ecc_err { … }; struct ras_ecc_log_info { … }; struct amdgpu_ras { … }; struct ras_fs_data { … }; struct ras_err_addr { … }; struct ras_err_info { … }; struct ras_err_node { … }; struct ras_err_data { … }; #define for_each_ras_error(err_node, err_data) … struct ras_err_handler_data { … }; ras_ih_cb; struct ras_ih_data { … }; struct ras_manager { … }; struct ras_badpage { … }; /* interfaces for IP */ struct ras_fs_if { … }; struct ras_query_if { … }; struct ras_inject_if { … }; struct ras_cure_if { … }; struct ras_ih_if { … }; struct ras_dispatch_if { … }; struct ras_debug_if { … }; struct amdgpu_ras_block_object { … }; struct amdgpu_ras_block_hw_ops { … }; /* work flow * vbios * 1: ras feature enable (enabled by default) * psp * 2: ras framework init (in ip_init) * IP * 3: IH add * 4: debugfs/sysfs create * 5: query/inject * 6: debugfs/sysfs remove * 7: IH remove * 8: feature disable */ int amdgpu_ras_recovery_init(struct amdgpu_device *adev); void amdgpu_ras_resume(struct amdgpu_device *adev); void amdgpu_ras_suspend(struct amdgpu_device *adev); int amdgpu_ras_query_error_count(struct amdgpu_device *adev, unsigned long *ce_count, unsigned long *ue_count, struct ras_query_if *query_info); /* error handling functions */ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, struct eeprom_table_record *bps, int pages); int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, unsigned long *new_cnt); static inline enum ta_ras_block amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { … } static inline enum ta_ras_error_type amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { … } /* called in ip_init and ip_fini */ int amdgpu_ras_init(struct amdgpu_device *adev); int amdgpu_ras_late_init(struct amdgpu_device *adev); int amdgpu_ras_fini(struct amdgpu_device *adev); int amdgpu_ras_pre_fini(struct amdgpu_device *adev); int amdgpu_ras_block_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block); int amdgpu_ras_feature_enable(struct amdgpu_device *adev, struct ras_common_if *head, bool enable); int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, struct ras_common_if *head, bool enable); int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, struct ras_common_if *head); int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, struct ras_common_if *head); void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info); int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block block); int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, enum amdgpu_ras_block block); int amdgpu_ras_error_inject(struct amdgpu_device *adev, struct ras_inject_if *info); int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, struct ras_common_if *head); int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, struct ras_common_if *head); int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, struct ras_dispatch_if *info); struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, struct ras_common_if *head); extern atomic_t amdgpu_ras_in_intr; static inline bool amdgpu_ras_intr_triggered(void) { … } static inline void amdgpu_ras_intr_cleared(void) { … } void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); void amdgpu_release_ras_context(struct amdgpu_device *adev); int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); const char *get_ras_block_str(struct ras_common_if *ras_block); bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable); bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev); bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, unsigned int *mode); int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, struct amdgpu_ras_block_object *ras_block_obj); void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name); bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, const struct amdgpu_ras_err_status_reg_entry *reg_entry, uint32_t instance, uint32_t *memory_id); bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, const struct amdgpu_ras_err_status_reg_entry *reg_entry, uint32_t instance, unsigned long *err_cnt); void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, const struct amdgpu_ras_err_status_reg_entry *reg_list, uint32_t reg_list_size, const struct amdgpu_ras_memory_id_entry *mem_list, uint32_t mem_list_size, uint32_t instance, uint32_t err_type, unsigned long *err_count); void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, const struct amdgpu_ras_err_status_reg_entry *reg_list, uint32_t reg_list_size, uint32_t instance); int amdgpu_ras_error_data_init(struct ras_err_data *err_data); void amdgpu_ras_error_data_fini(struct ras_err_data *err_data); int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, struct amdgpu_smuio_mcm_config_info *mcm_info, struct ras_err_addr *err_addr, u64 count); int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, struct amdgpu_smuio_mcm_config_info *mcm_info, struct ras_err_addr *err_addr, u64 count); int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, struct amdgpu_smuio_mcm_config_info *mcm_info, struct ras_err_addr *err_addr, u64 count); void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, const struct aca_info *aca_info, void *data); int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk); ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, struct aca_handle *handle, char *buf, void *data); void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *err_addr); void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *mca_err_addr); void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status); bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev); u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type); int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type, const void *caller); int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn); int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, enum amdgpu_ras_block block, uint16_t pasid, pasid_notify pasid_fn, void *data, uint32_t reset); bool amdgpu_ras_in_recovery(struct amdgpu_device *adev); __printf(3, 4) void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id, const char *fmt, ...); #endif
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