/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __AMDGPU_GFX_H__ #define __AMDGPU_GFX_H__ /* * GFX stuff */ #include "clearstate_defs.h" #include "amdgpu_ring.h" #include "amdgpu_rlc.h" #include "amdgpu_imu.h" #include "soc15.h" #include "amdgpu_ras.h" #include "amdgpu_ring_mux.h" /* GFX current status */ #define AMDGPU_GFX_NORMAL_MODE … #define AMDGPU_GFX_SAFE_MODE … #define AMDGPU_GFX_PG_DISABLED_MODE … #define AMDGPU_GFX_CG_DISABLED_MODE … #define AMDGPU_GFX_LBPW_DISABLED_MODE … #define AMDGPU_MAX_GC_INSTANCES … #define AMDGPU_MAX_QUEUES … #define AMDGPU_MAX_GFX_QUEUES … #define AMDGPU_MAX_COMPUTE_QUEUES … enum amdgpu_gfx_pipe_priority { … }; #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM … #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM … enum amdgpu_gfx_partition { … }; #define NUM_XCC(x) … enum amdgpu_gfx_ras_mem_id_type { … }; struct amdgpu_mec { … }; struct amdgpu_mec_bitmap { … }; enum amdgpu_unmap_queues_action { … }; struct kiq_pm4_funcs { … }; struct amdgpu_kiq { … }; /* * GFX configurations */ #define AMDGPU_GFX_MAX_SE … #define AMDGPU_GFX_MAX_SH_PER_SE … struct amdgpu_rb_config { … }; struct gb_addr_config { … }; struct amdgpu_gfx_config { … }; struct amdgpu_cu_info { … }; struct amdgpu_gfx_ras { … }; struct amdgpu_gfx_shadow_info { … }; struct amdgpu_gfx_funcs { … }; struct sq_work { … }; struct amdgpu_pfp { … }; struct amdgpu_ce { … }; struct amdgpu_me { … }; struct amdgpu_gfx { … }; struct amdgpu_gfx_ras_reg_entry { … }; struct amdgpu_gfx_ras_mem_id_entry { … }; #define AMDGPU_GFX_MEMID_ENT(x) … #define amdgpu_gfx_get_gpu_clock_counter(adev) … #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) … #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) … #define amdgpu_gfx_init_spm_golden(adev) … #define amdgpu_gfx_get_gfx_shadow_info(adev, si) … /** * amdgpu_gfx_create_bitmask - create a bitmask * * @bit_width: length of the mask * * create a variable length bit mask. * Returns the bitmask. */ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) { … } void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh); int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id); void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, unsigned hpd_size, int xcc_id); int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, unsigned mqd_size, int xcc_id); void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id); void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, int pipe, int queue); void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, int *mec, int *pipe, int *queue); bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id, int mec, int pipe, int queue); bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring); bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring); int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, int pipe, int queue); void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, int *me, int *pipe, int *queue); bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, int pipe, int queue); void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, void *err_data, struct amdgpu_iv_entry *entry); int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry); uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev); int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev); void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev); void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev, void *ras_error_status, void (*func)(struct amdgpu_device *adev, void *ras_error_status, int xcc_id)); static inline const char *amdgpu_gfx_compute_mode_desc(int mode) { … } #endif
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