/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __AMD_SHARED_H__ #define __AMD_SHARED_H__ #include <drm/amd_asic_type.h> #include <drm/drm_print.h> #define AMD_MAX_USEC_TIMEOUT … /* * Chip flags */ enum amd_chip_flags { … }; enum amd_apu_flags { … }; /** * DOC: IP Blocks * * GPUs are composed of IP (intellectual property) blocks. These * IP blocks provide various functionalities: display, graphics, * video decode, etc. The IP blocks that comprise a particular GPU * are listed in the GPU's respective SoC file. amdgpu_device.c * acquires the list of IP blocks for the GPU in use on initialization. * It can then operate on this list to perform standard driver operations * such as: init, fini, suspend, resume, etc. * * * IP block implementations are named using the following convention: * <functionality>_v<version> (E.g.: gfx_v6_0). */ /** * enum amd_ip_block_type - Used to classify IP blocks by functionality. * * @AMD_IP_BLOCK_TYPE_COMMON: GPU Family * @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller * @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler * @AMD_IP_BLOCK_TYPE_SMC: System Management Controller * @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor * @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine * @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine * @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine * @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder * @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor * @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine * @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine * @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Schduler for Multimedia * @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types */ enum amd_ip_block_type { … }; enum amd_clockgating_state { … }; enum amd_powergating_state { … }; /* CG flags */ #define AMD_CG_SUPPORT_GFX_MGCG … #define AMD_CG_SUPPORT_GFX_MGLS … #define AMD_CG_SUPPORT_GFX_CGCG … #define AMD_CG_SUPPORT_GFX_CGLS … #define AMD_CG_SUPPORT_GFX_CGTS … #define AMD_CG_SUPPORT_GFX_CGTS_LS … #define AMD_CG_SUPPORT_GFX_CP_LS … #define AMD_CG_SUPPORT_GFX_RLC_LS … #define AMD_CG_SUPPORT_MC_LS … #define AMD_CG_SUPPORT_MC_MGCG … #define AMD_CG_SUPPORT_SDMA_LS … #define AMD_CG_SUPPORT_SDMA_MGCG … #define AMD_CG_SUPPORT_BIF_LS … #define AMD_CG_SUPPORT_UVD_MGCG … #define AMD_CG_SUPPORT_VCE_MGCG … #define AMD_CG_SUPPORT_HDP_LS … #define AMD_CG_SUPPORT_HDP_MGCG … #define AMD_CG_SUPPORT_ROM_MGCG … #define AMD_CG_SUPPORT_DRM_LS … #define AMD_CG_SUPPORT_BIF_MGCG … #define AMD_CG_SUPPORT_GFX_3D_CGCG … #define AMD_CG_SUPPORT_GFX_3D_CGLS … #define AMD_CG_SUPPORT_DRM_MGCG … #define AMD_CG_SUPPORT_DF_MGCG … #define AMD_CG_SUPPORT_VCN_MGCG … #define AMD_CG_SUPPORT_HDP_DS … #define AMD_CG_SUPPORT_HDP_SD … #define AMD_CG_SUPPORT_IH_CG … #define AMD_CG_SUPPORT_ATHUB_LS … #define AMD_CG_SUPPORT_ATHUB_MGCG … #define AMD_CG_SUPPORT_JPEG_MGCG … #define AMD_CG_SUPPORT_GFX_FGCG … #define AMD_CG_SUPPORT_REPEATER_FGCG … #define AMD_CG_SUPPORT_GFX_PERF_CLK … /* PG flags */ #define AMD_PG_SUPPORT_GFX_PG … #define AMD_PG_SUPPORT_GFX_SMG … #define AMD_PG_SUPPORT_GFX_DMG … #define AMD_PG_SUPPORT_UVD … #define AMD_PG_SUPPORT_VCE … #define AMD_PG_SUPPORT_CP … #define AMD_PG_SUPPORT_GDS … #define AMD_PG_SUPPORT_RLC_SMU_HS … #define AMD_PG_SUPPORT_SDMA … #define AMD_PG_SUPPORT_ACP … #define AMD_PG_SUPPORT_SAMU … #define AMD_PG_SUPPORT_GFX_QUICK_MG … #define AMD_PG_SUPPORT_GFX_PIPELINE … #define AMD_PG_SUPPORT_MMHUB … #define AMD_PG_SUPPORT_VCN … #define AMD_PG_SUPPORT_VCN_DPG … #define AMD_PG_SUPPORT_ATHUB … #define AMD_PG_SUPPORT_JPEG … #define AMD_PG_SUPPORT_IH_SRAM_PG … #define AMD_PG_SUPPORT_JPEG_DPG … /** * enum PP_FEATURE_MASK - Used to mask power play features. * * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock. * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock. * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes. * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep. * @PP_POWER_CONTAINMENT_MASK: Power containment. * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake. * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control. * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support. * @PP_ULV_MASK: Ultra low voltage. * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating. * @PP_CLOCK_STRETCH_MASK: Clock stretching. * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control. * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock. * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock. * @PP_OVERDRIVE_MASK: Over- and under-clocking support. * @PP_GFXOFF_MASK: Dynamic graphics engine power control. * @PP_ACG_MASK: Adaptive clock generator. * @PP_STUTTER_MODE: Stutter mode. * @PP_AVFS_MASK: Adaptive voltage and frequency scaling. * @PP_GFX_DCS_MASK: GFX Async DCS. * * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to * the kernel's command line parameters. This is usually done through a system's * boot loader (E.g. GRUB). If manually loading the driver, pass * ppfeaturemask=<mask> as a modprobe parameter. */ enum PP_FEATURE_MASK { … }; enum amd_harvest_ip_mask { … }; enum DC_FEATURE_MASK { … }; enum DC_DEBUG_MASK { … }; enum amd_dpm_forced_level; /** * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks * @name: Name of IP block * @early_init: sets up early driver state (pre sw_init), * does not configure hw - Optional * @late_init: sets up late driver/hw state (post hw_init) - Optional * @sw_init: sets up driver state, does not configure hw * @sw_fini: tears down driver state, does not configure hw * @early_fini: tears down stuff before dev detached from driver * @hw_init: sets up the hw state * @hw_fini: tears down the hw state * @late_fini: final cleanup * @prepare_suspend: handle IP specific changes to prepare for suspend * (such as allocating any required memory) * @suspend: handles IP specific hw/sw changes for suspend * @resume: handles IP specific hw/sw changes for resume * @is_idle: returns current IP block idle status * @wait_for_idle: poll for idle * @check_soft_reset: check soft reset the IP block * @pre_soft_reset: pre soft reset the IP block * @soft_reset: soft reset the IP block * @post_soft_reset: post soft reset the IP block * @set_clockgating_state: enable/disable cg for the IP block * @set_powergating_state: enable/disable pg for the IP block * @get_clockgating_state: get current clockgating status * @dump_ip_state: dump the IP state of the ASIC during a gpu hang * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC * * These hooks provide an interface for controlling the operational state * of IP blocks. After acquiring a list of IP blocks for the GPU in use, * the driver can make chip-wide state changes by walking this list and * making calls to hooks from each IP block. This list is ordered to ensure * that the driver initializes the IP blocks in a safe sequence. */ struct amd_ip_funcs { … }; #endif /* __AMD_SHARED_H__ */
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