/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef DC_DP_TYPES_H #define DC_DP_TYPES_H #include "os_types.h" #include "dc_ddc_types.h" enum dc_lane_count { … }; /* This is actually a reference clock (27MHz) multiplier * 162MBps bandwidth for 1.62GHz like rate, * 270MBps for 2.70GHz, * 324MBps for 3.24Ghz, * 540MBps for 5.40GHz * 810MBps for 8.10GHz */ enum dc_link_rate { … }; enum dc_link_spread { … }; enum dc_voltage_swing { … }; enum dc_pre_emphasis { … }; /* Post Cursor 2 is optional for transmitter * and it applies only to the main link operating at HBR2 */ enum dc_post_cursor2 { … }; enum dc_dp_ffe_preset_level { … }; enum dc_dp_training_pattern { … }; enum dp_link_encoding { … }; enum dp_test_link_rate { … }; struct dc_link_settings { … }; dc_dp_ffe_preset; struct dc_lane_settings { … }; struct dc_link_training_overrides { … }; payload_table_update_status; dpcd_rev; max_lane_count; max_down_spread; mstm_cap; lane_count_set; lane_status; device_service_irq; sink_count; lane_align_status_updated; lane_adjust; dpcd_training_pattern; /* Training Lane is used to configure downstream DP device's voltage swing and pre-emphasis levels*/ /* The DPCD addresses are from 0x103 to 0x106*/ dpcd_training_lane; /* TMDS-converter related */ dwnstream_port_caps_byte0; /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ enum dpcd_downstream_port_detailed_type { … }; dwnstream_port_caps_byte2; dp_downstream_port_present; dwnstream_port_caps_byte3_dvi; dwnstream_port_caps_byte3_hdmi; hdmi_sink_encoded_link_bw_support; hdmi_encoded_link_bw; /*4-byte structure for detailed capabilities of a down-stream port (DP-to-TMDS converter).*/ dwnstream_portxcaps; downstream_port; sink_status; /*6-byte structure corresponding to 6 registers (200h-205h) read during handling of HPD-IRQ*/ hpd_irq_data; down_stream_port_count; down_spread_ctrl; dpcd_edp_config; struct dp_device_vendor_id { … }; struct dp_sink_hw_fw_revision { … }; struct dpcd_vendor_signature { … }; struct dpcd_amd_signature { … }; struct dpcd_amd_device_id { … }; struct target_luminance_value { … }; struct dpcd_source_backlight_set { … }; dpcd_source_backlight_get; /*DPCD register of DP receiver capability field bits-*/ edp_configuration_cap; dprx_feature; training_aux_rd_interval; /* Automated test structures */ test_request; test_response; phy_test_pattern; /* States of Compliance Test Specification (CTS DP1.2). */ compliance_test_state; link_test_pattern; test_misc; audio_test_mode; audio_test_pattern_period; struct audio_test_pattern_type { … }; struct dp_audio_test_data_flags { … }; struct dp_audio_test_data { … }; /* FEC capability DPCD register field bits-*/ dpcd_fec_capability; /* DSC capability DPCD register field bits-*/ struct dpcd_dsc_support { … }; struct dpcd_dsc_algorithm_revision { … }; struct dpcd_dsc_rc_buffer_block_size { … }; struct dpcd_dsc_slice_capability1 { … }; struct dpcd_dsc_line_buffer_bit_depth { … }; struct dpcd_dsc_block_prediction_support { … }; struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { … }; struct dpcd_dsc_decoder_color_format_capabilities { … }; struct dpcd_dsc_decoder_color_depth_capabilities { … }; struct dpcd_peak_dsc_throughput_dsc_sink { … }; struct dpcd_dsc_slice_capabilities_2 { … }; struct dpcd_bits_per_pixel_increment{ … }; dpcd_dsc_basic_capabilities; dpcd_dsc_branch_decoder_capabilities; struct dpcd_dsc_capabilities { … }; /* These parameters are from PSR capabilities reported by Sink DPCD */ struct psr_caps { … }; dpcd_dprx_feature_enumeration_list_cont_1; struct adaptive_sync_caps { … }; /* Length of router topology ID read from DPCD in bytes. */ #define DPCD_USB4_TOPOLOGY_ID_LEN … /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ dp_tun_cap_support; /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ dpia_info; /* DP Tunneling over USB4 */ struct dpcd_usb4_dp_tunneling_info { … }; dp_main_line_channel_coding_cap; dp_main_link_channel_coding_lttpr_cap; dp_128b_132b_supported_link_rates; dp_128b_132b_supported_lttpr_link_rates; dp_sink_video_fallback_formats; dp_fec_capability1; dp_cable_id; struct dp_color_depth_caps { … }; struct dp_encoding_format_caps { … }; dp_dfp_cap_ext; dp_128b_132b_training_aux_rd_interval; edp_alpm_caps; edp_psr_dpcd_caps; struct edp_psr_info { … }; struct replay_info { … }; struct dprx_states { … }; enum dpcd_downstream_port_max_bpc { … }; enum link_training_offset { … }; #define MAX_REPEATER_CNT … struct dc_lttpr_caps { … }; struct dc_dongle_dfp_cap_ext { … }; struct dc_dongle_caps { … }; struct dpcd_caps { … }; dpcd_sink_ext_caps; enum dc_link_fec_state { … }; dpcd_psr_configuration; replay_enable_and_configuration; dpcd_replay_configuration; dpcd_alpm_configuration; dpcd_sink_active_vtotal_control_mode; psr_error_status; psr_sink_psr_status; struct edp_trace_power_timestamps { … }; struct dp_trace_lt_counts { … }; enum link_training_result { … }; struct dp_trace_lt { … }; struct dp_trace { … }; /* TODO - This is a temporary location for any new DPCD definitions. * We should move these to drm_dp header. */ #ifndef DP_LINK_SQUARE_PATTERN #define DP_LINK_SQUARE_PATTERN … #endif #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX … #endif #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX … #endif #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE … #endif #ifndef DP_TUNNELING_IRQ #define DP_TUNNELING_IRQ … #endif /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/ #ifndef DP_TUNNELING_CAPABILITIES #define DP_TUNNELING_CAPABILITIES … #endif #ifndef USB4_DRIVER_ID #define USB4_DRIVER_ID … #endif #ifndef USB4_DRIVER_BW_CAPABILITY #define USB4_DRIVER_BW_CAPABILITY … #endif #ifndef DP_IN_ADAPTER_TUNNEL_INFO #define DP_IN_ADAPTER_TUNNEL_INFO … #endif #ifndef DP_BW_GRANULALITY #define DP_BW_GRANULALITY … #endif #ifndef ESTIMATED_BW #define ESTIMATED_BW … #endif #ifndef ALLOCATED_BW #define ALLOCATED_BW … #endif #ifndef DP_TUNNELING_STATUS #define DP_TUNNELING_STATUS … #endif #ifndef DP_TUNNELING_MAX_LINK_RATE #define DP_TUNNELING_MAX_LINK_RATE … #endif #ifndef DP_TUNNELING_MAX_LANE_COUNT #define DP_TUNNELING_MAX_LANE_COUNT … #endif #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL #define DPTX_BW_ALLOCATION_MODE_CONTROL … #endif #ifndef REQUESTED_BW #define REQUESTED_BW … #endif #endif /* DC_DP_TYPES_H */
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