dc_hw_types.h | Explore in Territory

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef DC_HW_TYPES_H
#define DC_HW_TYPES_H

#include "os_types.h"
#include "fixed31_32.h"
#include "signal_types.h"

/******************************************************************************
 * Data types for Virtual HW Layer of DAL3.
 * (see DAL3 design documents for HW Layer definition)
 *
 * The intended uses are:
 * 1. Generation pseudocode sequences for HW programming.
 * 2. Implementation of real HW programming by HW Sequencer of DAL3.
 *
 * Note: do *not* add any types which are *not* used for HW programming - this
 * will ensure separation of Logic layer from HW layer.
 ******************************************************************************/

large_integer;

#define PHYSICAL_ADDRESS_LOC …

enum dc_plane_addr_type { … };

struct dc_plane_address { … };

struct dc_size { … };

struct rect { … };

struct plane_size { … };

struct dc_plane_dcc_param { … };

/*Displayable pixel format in fb*/
enum surface_pixel_format { … };



/* Pixel format */
enum pixel_format { … };

/*
 * This structure holds a surface address.  There could be multiple addresses
 * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
 * as frame durations and DCC format can also be set.
 */
#define DC_MAX_DIRTY_RECTS …
struct dc_flip_addrs { … };

enum tile_split_values { … };

enum tripleBuffer_enable { … };
enum tile_split_values_new { … };

/* TODO: These values come from hardware spec. We need to readdress this
 * if they ever change.
 */
enum array_mode_values { … };

enum tile_mode_values { … };

enum swizzle_mode_values { … };

// Definition of swizzle modes with addr3 ASICs
enum swizzle_mode_addr3_values { … };

dc_tiling_info;

/* Rotation angle */
enum dc_rotation_angle { … };

enum dc_scan_direction { … };

/**
 * struct dc_cursor_position: Hardware cursor data.
 *
 * This struct keeps the action information related to the cursor that will be
 * sent and received from our DC core.
 */
struct dc_cursor_position { … };

struct dc_cursor_mi_param { … };

/* IPP related types */

enum { … };

enum dc_gamma_type { … };

struct dc_csc_transform { … };

struct dc_rgb_fixed { … };

struct dc_gamma { … };

/* Used by both ipp amd opp functions*/
/* TODO: to be consolidated with enum color_space */

/**
 * enum dc_cursor_color_format - DC cursor programming mode
 *
 * This enum is for programming CURSOR_MODE register field. What this register
 * should be programmed to depends on OS requested cursor shape flags and what
 * we stored in the cursor surface.
 */
enum dc_cursor_color_format { … };

/*
 * This is all the parameters required by DAL in order to update the cursor
 * attributes, including the new cursor image surface address, size, hotspot
 * location, color format, etc.
 */

dc_cursor_attribute_flags;

struct dc_cursor_attributes { … };

struct dpp_cursor_attributes { … };

/* OPP */

enum dc_color_space { … };

enum dc_dither_option { … };

enum dc_quantization_range { … };

enum dc_dynamic_expansion { … };

/* XFM */

/* used in  struct dc_plane_state */
struct scaling_taps { … };

enum dc_timing_standard { … };

enum dc_color_depth { … };

enum dc_pixel_encoding { … };

enum dc_aspect_ratio { … };

enum scanning_type { … };

enum chroma_cositing { … };

struct dc_crtc_timing_flags { … };

enum dc_timing_3d_format { … };

#define DC_DSC_QP_SET_SIZE …
#define DC_DSC_RC_BUF_THRESH_SIZE …
struct dc_dsc_rc_params_override { … };

struct dc_dsc_config { … };

/**
 * struct dc_crtc_timing - Timing parameters used to configure DCN blocks
 *
 * DCN provides multiple signals and parameters that can be used to adjust
 * timing parameters, this struct aggregate multiple of these values for easy
 * access. In this struct, fields prefixed with h_* are related to horizontal
 * timing, and v_* to vertical timing. Keep in mind that when we talk about
 * vertical timings, the values, in general, are described in the number of
 * lines; on the other hand, the horizontal values are in pixels.
 */
struct dc_crtc_timing { … };

enum trigger_delay { … };

enum crtc_event { … };

struct crtc_trigger_info { … };

struct dc_crtc_timing_adjust { … };


/* Passed on init */
enum vram_type { … };

enum dwb_cnv_out_bpc { … };

enum dwb_output_depth { … };

enum dwb_capture_rate { … };

enum dwb_scaler_mode { … };

enum dwb_subsample_position { … };

enum dwb_stereo_eye_select { … };

enum dwb_stereo_type { … };

enum dwb_out_format { … };

enum dwb_out_denorm { … };

enum cm_gamut_remap_select { … };

enum cm_gamut_coef_format { … };

enum mpcc_gamut_remap_mode_select { … };

enum mpcc_gamut_remap_id { … };

enum cursor_matrix_mode { … };

struct mcif_warmup_params { … };

#define MCIF_BUF_COUNT …

struct mcif_buf_params { … };


#define MAX_TG_COLOR_VALUE …
struct tg_color { … };

enum symclk_state { … };

struct phy_state { … };

#endif /* DC_HW_TYPES_H */
linux/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
