dm_services_types.h | Explore in Territory

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DM_SERVICES_TYPES_H__
#define __DM_SERVICES_TYPES_H__

#include "os_types.h"
#include "dc_types.h"

struct pp_smu_funcs;

struct dm_pp_clock_range { … };

enum dm_pp_clocks_state { … };

struct dm_pp_gpu_clock_range { … };

enum dm_pp_clock_type { … };

#define DC_DECODE_PP_CLOCK_TYPE(clk_type) …

#define DM_PP_MAX_CLOCK_LEVELS …

struct dm_pp_clock_levels { … };

struct dm_pp_clock_with_latency { … };

struct dm_pp_clock_levels_with_latency { … };

struct dm_pp_clock_with_voltage { … };

struct dm_pp_clock_levels_with_voltage { … };

struct dm_pp_single_disp_config { … };

#define MAX_WM_SETS …

enum dm_pp_wm_set_id { … };

struct dm_pp_clock_range_for_wm_set { … };

struct dm_pp_wm_sets_with_clock_ranges { … };

struct dm_pp_clock_range_for_dmif_wm_set_soc15 { … };

struct dm_pp_clock_range_for_mcif_wm_set_soc15 { … };

struct dm_pp_wm_sets_with_clock_ranges_soc15 { … };

#define MAX_DISPLAY_CONFIGS …

struct dm_pp_display_configuration { … };

struct dm_bl_data_point { … };

/* Total size of the structure should not exceed 256 bytes */
#define BL_DATA_POINTS …
struct dm_acpi_atif_backlight_caps { … };

enum dm_acpi_display_type { … };

struct dm_pp_power_level_change_request { … };

struct dm_pp_clock_for_voltage_req { … };

struct dm_pp_static_clock_info { … };

struct dtn_min_clk_info { … };

enum dm_dmub_wait_type { … };

#endif
linux/drivers/gpu/drm/amd/display/dc/dm_services_types.h
