/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KGD_PP_INTERFACE_H__ #define __KGD_PP_INTERFACE_H__ extern const struct amdgpu_ip_block_version pp_smu_ip_block; extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; enum smu_event_type { … }; struct amd_vce_state { … }; enum amd_dpm_forced_level { … }; enum amd_pm_state_type { … }; #define AMD_MAX_VCE_LEVELS … enum amd_vce_level { … }; enum amd_fan_ctrl_mode { … }; enum pp_clock_type { … }; enum amd_pp_sensors { … }; enum amd_pp_task { … }; enum PP_SMC_POWER_PROFILE { … }; extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; enum { … }; enum PP_OD_DPM_TABLE_COMMAND { … }; struct pp_states_info { … }; enum PP_HWMON_TEMP { … }; enum pp_mp1_state { … }; enum pp_df_cstate { … }; /** * DOC: amdgpu_pp_power * * APU power is managed to system-level requirements through the PPT * (package power tracking) feature. PPT is intended to limit power to the * requirements of the power source and could be dynamically updated to * maximize APU performance within the system power budget. * * Two types of power measurement can be requested, where supported, with * :c:type:`enum pp_power_type <pp_power_type>`. */ /** * enum pp_power_limit_level - Used to query the power limits * * @PP_PWR_LIMIT_MIN: Minimum Power Limit * @PP_PWR_LIMIT_CURRENT: Current Power Limit * @PP_PWR_LIMIT_DEFAULT: Default Power Limit * @PP_PWR_LIMIT_MAX: Maximum Power Limit */ enum pp_power_limit_level { … }; /** * enum pp_power_type - Used to specify the type of the requested power * * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant * moving average of APU power (default ~5000 ms). * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, * where supported. */ enum pp_power_type { … }; enum pp_xgmi_plpd_mode { … }; enum pp_pm_policy { … }; enum pp_policy_soc_pstate { … }; #define PP_POLICY_MAX_LEVELS … #define PP_GROUP_MASK … #define PP_GROUP_SHIFT … #define PP_BLOCK_MASK … #define PP_BLOCK_SHIFT … #define PP_BLOCK_GFX_CG … #define PP_BLOCK_GFX_MG … #define PP_BLOCK_GFX_3D … #define PP_BLOCK_GFX_RLC … #define PP_BLOCK_GFX_CP … #define PP_BLOCK_SYS_BIF … #define PP_BLOCK_SYS_MC … #define PP_BLOCK_SYS_ROM … #define PP_BLOCK_SYS_DRM … #define PP_BLOCK_SYS_HDP … #define PP_BLOCK_SYS_SDMA … #define PP_STATE_MASK … #define PP_STATE_SHIFT … #define PP_STATE_SUPPORT_MASK … #define PP_STATE_SUPPORT_SHIFT … #define PP_STATE_CG … #define PP_STATE_LS … #define PP_STATE_DS … #define PP_STATE_SD … #define PP_STATE_SUPPORT_CG … #define PP_STATE_SUPPORT_LS … #define PP_STATE_SUPPORT_DS … #define PP_STATE_SUPPORT_SD … #define PP_CG_MSG_ID(group, block, support, state) … #define XGMI_MODE_PSTATE_D3 … #define XGMI_MODE_PSTATE_D0 … #define NUM_HBM_INSTANCES … #define NUM_XGMI_LINKS … #define MAX_GFX_CLKS … #define MAX_CLKS … #define NUM_VCN … #define NUM_JPEG_ENG … struct seq_file; enum amd_pp_clock_type; struct amd_pp_simple_clock_info; struct amd_pp_display_configuration; struct amd_pp_clock_info; struct pp_display_clock_request; struct pp_clock_levels_with_voltage; struct pp_clock_levels_with_latency; struct amd_pp_clocks; struct pp_smu_wm_range_sets; struct pp_smu_nv_clock_table; struct dpm_clocks; struct amd_pm_funcs { … }; struct metrics_table_header { … }; /* * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v1_1 or later instead. */ struct gpu_metrics_v1_0 { … }; struct gpu_metrics_v1_1 { … }; struct gpu_metrics_v1_2 { … }; struct gpu_metrics_v1_3 { … }; struct gpu_metrics_v1_4 { … }; struct gpu_metrics_v1_5 { … }; /* * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v2_1 or later instead. */ struct gpu_metrics_v2_0 { … }; struct gpu_metrics_v2_1 { … }; struct gpu_metrics_v2_2 { … }; struct gpu_metrics_v2_3 { … }; struct gpu_metrics_v2_4 { … }; struct gpu_metrics_v3_0 { … }; struct amdgpu_pmmetrics_header { … }; struct amdgpu_pm_metrics { … }; #endif
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