/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __AMDGPU_UCODE_H__ #define __AMDGPU_UCODE_H__ #include "amdgpu_socbb.h" struct common_firmware_header { … }; /* version_major=1, version_minor=0 */ struct mc_firmware_header_v1_0 { … }; /* version_major=1, version_minor=0 */ struct smc_firmware_header_v1_0 { … }; /* version_major=2, version_minor=0 */ struct smc_firmware_header_v2_0 { … }; struct smc_soft_pptable_entry { … }; /* version_major=2, version_minor=1 */ struct smc_firmware_header_v2_1 { … }; struct psp_fw_legacy_bin_desc { … }; /* version_major=1, version_minor=0 */ struct psp_firmware_header_v1_0 { … }; /* version_major=1, version_minor=1 */ struct psp_firmware_header_v1_1 { … }; /* version_major=1, version_minor=2 */ struct psp_firmware_header_v1_2 { … }; /* version_major=1, version_minor=3 */ struct psp_firmware_header_v1_3 { … }; struct psp_fw_bin_desc { … }; enum psp_fw_type { … }; /* version_major=2, version_minor=0 */ struct psp_firmware_header_v2_0 { … }; /* version_major=1, version_minor=0 */ struct ta_firmware_header_v1_0 { … }; enum ta_fw_type { … }; /* version_major=2, version_minor=0 */ struct ta_firmware_header_v2_0 { … }; /* version_major=1, version_minor=0 */ struct gfx_firmware_header_v1_0 { … }; /* version_major=2, version_minor=0 */ struct gfx_firmware_header_v2_0 { … }; /* version_major=1, version_minor=0 */ struct mes_firmware_header_v1_0 { … }; /* version_major=1, version_minor=0 */ struct rlc_firmware_header_v1_0 { … }; /* version_major=2, version_minor=0 */ struct rlc_firmware_header_v2_0 { … }; /* version_major=2, version_minor=1 */ struct rlc_firmware_header_v2_1 { … }; /* version_major=2, version_minor=2 */ struct rlc_firmware_header_v2_2 { … }; /* version_major=2, version_minor=3 */ struct rlc_firmware_header_v2_3 { … }; /* version_major=2, version_minor=4 */ struct rlc_firmware_header_v2_4 { … }; /* version_major=1, version_minor=0 */ struct sdma_firmware_header_v1_0 { … }; /* version_major=1, version_minor=1 */ struct sdma_firmware_header_v1_1 { … }; /* version_major=2, version_minor=0 */ struct sdma_firmware_header_v2_0 { … }; /* version_major=1, version_minor=0 */ struct vpe_firmware_header_v1_0 { … }; /* version_major=1, version_minor=0 */ struct umsch_mm_firmware_header_v1_0 { … }; /* version_major=3, version_minor=0 */ struct sdma_firmware_header_v3_0 { … }; /* gpu info payload */ struct gpu_info_firmware_v1_0 { … }; struct gpu_info_firmware_v1_1 { … }; /* gpu info payload * version_major=1, version_minor=1 */ struct gpu_info_firmware_v1_2 { … }; /* version_major=1, version_minor=0 */ struct gpu_info_firmware_header_v1_0 { … }; /* version_major=1, version_minor=0 */ struct dmcu_firmware_header_v1_0 { … }; /* version_major=1, version_minor=0 */ struct dmcub_firmware_header_v1_0 { … }; /* version_major=1, version_minor=0 */ struct imu_firmware_header_v1_0 { … }; /* header is fixed size */ amdgpu_firmware_header; #define UCODE_MAX_PSP_PACKAGING … /* * fw loading support */ enum AMDGPU_UCODE_ID { … }; /* engine firmware status */ enum AMDGPU_UCODE_STATUS { … }; enum amdgpu_firmware_load_type { … }; /* conform to smu_ucode_xfer_cz.h */ #define AMDGPU_SDMA0_UCODE_LOADED … #define AMDGPU_SDMA1_UCODE_LOADED … #define AMDGPU_CPCE_UCODE_LOADED … #define AMDGPU_CPPFP_UCODE_LOADED … #define AMDGPU_CPME_UCODE_LOADED … #define AMDGPU_CPMEC1_UCODE_LOADED … #define AMDGPU_CPMEC2_UCODE_LOADED … #define AMDGPU_CPRLC_UCODE_LOADED … /* amdgpu firmware info */ struct amdgpu_firmware_info { … }; struct amdgpu_firmware { … }; void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); __printf(3, 4) int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, const char *fmt, ...); void amdgpu_ucode_release(const struct firmware **fw); bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, uint16_t hdr_major, uint16_t hdr_minor); int amdgpu_ucode_init_bo(struct amdgpu_device *adev); int amdgpu_ucode_create_bo(struct amdgpu_device *adev); int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); void amdgpu_ucode_free_bo(struct amdgpu_device *adev); void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); enum amdgpu_firmware_load_type amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); #endif
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