/* * Copyright 2006-2007 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ /****************************************************************************/ /*Portion I: Definitions shared between VBIOS and Driver */ /****************************************************************************/ #ifndef _ATOMBIOS_H #define _ATOMBIOS_H #define ATOM_VERSION_MAJOR … #define ATOM_VERSION_MINOR … #define ATOM_HEADER_VERSION … /* Endianness should be specified before inclusion, * default to little endian */ #ifndef ATOM_BIG_ENDIAN #error Endian not specified #endif #ifdef _H2INC #ifndef ULONG typedef unsigned long ULONG; #endif #ifndef UCHAR typedef unsigned char UCHAR; #endif #ifndef USHORT typedef unsigned short USHORT; #endif #endif #define ATOM_DAC_A … #define ATOM_DAC_B … #define ATOM_EXT_DAC … #define ATOM_CRTC1 … #define ATOM_CRTC2 … #define ATOM_CRTC3 … #define ATOM_CRTC4 … #define ATOM_CRTC5 … #define ATOM_CRTC6 … #define ATOM_UNDERLAY_PIPE0 … #define ATOM_UNDERLAY_PIPE1 … #define ATOM_CRTC_INVALID … #define ATOM_DIGA … #define ATOM_DIGB … #define ATOM_PPLL1 … #define ATOM_PPLL2 … #define ATOM_DCPLL … #define ATOM_PPLL0 … #define ATOM_PPLL3 … #define ATOM_PHY_PLL0 … #define ATOM_PHY_PLL1 … #define ATOM_EXT_PLL1 … #define ATOM_GCK_DFS … #define ATOM_EXT_PLL2 … #define ATOM_FCH_CLK … #define ATOM_EXT_CLOCK … #define ATOM_DP_DTO … #define ATOM_COMBOPHY_PLL0 … #define ATOM_COMBOPHY_PLL1 … #define ATOM_COMBOPHY_PLL2 … #define ATOM_COMBOPHY_PLL3 … #define ATOM_COMBOPHY_PLL4 … #define ATOM_COMBOPHY_PLL5 … #define ATOM_PPLL_INVALID … #define ENCODER_REFCLK_SRC_P1PLL … #define ENCODER_REFCLK_SRC_P2PLL … #define ENCODER_REFCLK_SRC_DCPLL … #define ENCODER_REFCLK_SRC_EXTCLK … #define ENCODER_REFCLK_SRC_INVALID … #define ATOM_SCALER_DISABLE … #define ATOM_SCALER_CENTER … #define ATOM_SCALER_EXPANSION … #define ATOM_SCALER_MULTI_EX … #define ATOM_DISABLE … #define ATOM_ENABLE … #define ATOM_LCD_BLOFF … #define ATOM_LCD_BLON … #define ATOM_LCD_BL_BRIGHTNESS_CONTROL … #define ATOM_LCD_SELFTEST_START … #define ATOM_LCD_SELFTEST_STOP … #define ATOM_ENCODER_INIT … #define ATOM_INIT … #define ATOM_GET_STATUS … #define ATOM_BLANKING … #define ATOM_BLANKING_OFF … #define ATOM_CRT1 … #define ATOM_CRT2 … #define ATOM_TV_NTSC … #define ATOM_TV_NTSCJ … #define ATOM_TV_PAL … #define ATOM_TV_PALM … #define ATOM_TV_PALCN … #define ATOM_TV_PALN … #define ATOM_TV_PAL60 … #define ATOM_TV_SECAM … #define ATOM_TV_CV … #define ATOM_DAC1_PS2 … #define ATOM_DAC1_CV … #define ATOM_DAC1_NTSC … #define ATOM_DAC1_PAL … #define ATOM_DAC2_PS2 … #define ATOM_DAC2_CV … #define ATOM_DAC2_NTSC … #define ATOM_DAC2_PAL … #define ATOM_PM_ON … #define ATOM_PM_STANDBY … #define ATOM_PM_SUSPEND … #define ATOM_PM_OFF … // For ATOM_LVDS_INFO_V12 // Bit0:{=0:single, =1:dual}, // Bit1 {=0:666RGB, =1:888RGB}, // Bit2:3:{Grey level} // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} #define ATOM_PANEL_MISC_DUAL … #define ATOM_PANEL_MISC_888RGB … #define ATOM_PANEL_MISC_GREY_LEVEL … #define ATOM_PANEL_MISC_FPDI … #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT … #define ATOM_PANEL_MISC_SPATIAL … #define ATOM_PANEL_MISC_TEMPORAL … #define ATOM_PANEL_MISC_API_ENABLED … #define MEMTYPE_DDR1 … #define MEMTYPE_DDR2 … #define MEMTYPE_DDR3 … #define MEMTYPE_DDR4 … #define ASIC_BUS_TYPE_PCI … #define ASIC_BUS_TYPE_AGP … #define ASIC_BUS_TYPE_PCIE … //Maximum size of that FireGL flag string #define ATOM_FIREGL_FLAG_STRING … #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING … #define ATOM_FAKE_DESKTOP_STRING … #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING … #define ATOM_M54T_FLAG_STRING … #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING … #define HW_ASSISTED_I2C_STATUS_FAILURE … #define HW_ASSISTED_I2C_STATUS_SUCCESS … #pragma pack(1) // BIOS data must use byte alignment // Define offset to location of ROM header. #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER … #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE … #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE … #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE … #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER … #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START … /****************************************************************************/ // Common header for all tables (Data table, Command table). // Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. // And the pointer actually points to this header. /****************************************************************************/ ATOM_COMMON_TABLE_HEADER; /****************************************************************************/ // Structure stores the ROM header. /****************************************************************************/ ATOM_ROM_HEADER; ATOM_ROM_HEADER_V2_1; //==============================Command Table Portion==================================== /****************************************************************************/ // Structures used in Command.mtb /****************************************************************************/ ATOM_MASTER_LIST_OF_COMMAND_TABLES; // For backward compatible #define ReadEDIDFromHWAssistedI2C … #define DPTranslatorControl … #define UNIPHYTransmitterControl … #define LVTMATransmitterControl … #define SetCRTC_DPM_State … #define ASIC_StaticPwrMgtStatusChange … #define HPDInterruptService … #define EnableVGA_Access … #define EnableYUV … #define DynamicClockGating … #define SetupHWAssistedI2CStatus … #define DAC2OutputControl … #define TMDSAEncoderControl … #define LVDSEncoderControl … #define LCD1OutputControl … #define TV1OutputControl … #define TVEncoderControl … #define EnableHW_IconCursor … #define SetCRTC_Replication … #define MemoryRefreshConversion … ATOM_MASTER_COMMAND_TABLE; /****************************************************************************/ // Structures used in every command table /****************************************************************************/ ATOM_TABLE_ATTRIBUTE; /****************************************************************************/ // Common header for all command tables. // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. // And the pointer actually points to this header. /****************************************************************************/ ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; /****************************************************************************/ // Structures used by ComputeMemoryEnginePLLTable /****************************************************************************/ #define COMPUTE_MEMORY_PLL_PARAM … #define COMPUTE_ENGINE_PLL_PARAM … #define ADJUST_MC_SETTING_PARAM … /****************************************************************************/ // Structures used by AdjustMemoryControllerTable /****************************************************************************/ ATOM_ADJUST_MEMORY_CLOCK_FREQ; #define POINTER_RETURN_FLAG … COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION … #define SET_CLOCK_FREQ_MASK … #define USE_NON_BUS_CLOCK_MASK … #define USE_MEMORY_SELF_REFRESH_MASK … #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE … #define FIRST_TIME_CHANGE_CLOCK … #define SKIP_SW_PROGRAM_PLL … #define USE_SS_ENABLED_PIXEL_CLOCK … #define b3USE_NON_BUS_CLOCK_MASK … #define b3USE_MEMORY_SELF_REFRESH … #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE … #define b3FIRST_TIME_CHANGE_CLOCK … #define b3SKIP_SW_PROGRAM_PLL … #define b3DRAM_SELF_REFRESH_EXIT … #define b3SRIOV_INIT_BOOT … #define b3SRIOV_LOAD_UCODE … #define b3SRIOV_SKIP_ASIC_INIT … ATOM_COMPUTE_CLOCK_FREQ; ATOM_S_MPLL_FB_DIVIDER; COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; // ucCntlFlag #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN … #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE … #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE … #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 … // V4 are only used for APU which PLL outside GPU COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK … #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK … #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK … COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; //ucPllCntlFlag #define SPLL_CNTL_FLAG_VCO_MODE_MASK … COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7; //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK … #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK … #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK … COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7; // ucInputFlag #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN … // use for ComputeMemoryClockParamTable COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; // definition of ucInputFlag #define MPLL_INPUT_FLAG_STROBE_MODE_EN … // definition of ucPllCntlFlag #define MPLL_CNTL_FLAG_VCO_MODE_MASK … #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL … #define MPLL_CNTL_FLAG_QDR_ENABLE … #define MPLL_CNTL_FLAG_AD_HALF_RATE … //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL #define MPLL_CNTL_FLAG_BYPASS_AD_PLL … // use for ComputeMemoryClockParamTable COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2; COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3; //Input parameter of DynamicMemorySettingsTable //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM DYNAMICE_MEMORY_SETTINGS_PARAMETER; //Input parameter of DynamicMemorySettingsTable //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM DYNAMICE_ENGINE_SETTINGS_PARAMETER; //Input parameter of DynamicMemorySettingsTable ver2.1 and above //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM DYNAMICE_MC_DPM_SETTINGS_PARAMETER; //ucMclkDPMState #define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE … #define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE … #define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE … DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1; /****************************************************************************/ // Structures used by SetEngineClockTable /****************************************************************************/ SET_ENGINE_CLOCK_PARAMETERS; SET_ENGINE_CLOCK_PS_ALLOCATION; SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2; /****************************************************************************/ // Structures used by SetMemoryClockTable /****************************************************************************/ SET_MEMORY_CLOCK_PARAMETERS; SET_MEMORY_CLOCK_PS_ALLOCATION; /****************************************************************************/ // Structures used by ASIC_Init.ctb /****************************************************************************/ ASIC_INIT_PARAMETERS; ASIC_INIT_PS_ALLOCATION; ASIC_INIT_CLOCK_PARAMETERS; ASIC_INIT_PARAMETERS_V1_2; ASIC_INIT_PS_ALLOCATION_V1_2; /****************************************************************************/ // Structure used by DynamicClockGatingTable.ctb /****************************************************************************/ DYNAMIC_CLOCK_GATING_PARAMETERS; #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION … /****************************************************************************/ // Structure used by EnableDispPowerGatingTable.ctb /****************************************************************************/ ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; ENABLE_DISP_POWER_GATING_PS_ALLOCATION; /****************************************************************************/ // Structure used by EnableASIC_StaticPwrMgtTable.ctb /****************************************************************************/ ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION … /****************************************************************************/ // Structures used by DAC_LoadDetectionTable.ctb /****************************************************************************/ DAC_LOAD_DETECTION_PARAMETERS; // DAC_LOAD_DETECTION_PARAMETERS.ucMisc #define DAC_LOAD_MISC_YPrPb … DAC_LOAD_DETECTION_PS_ALLOCATION; /****************************************************************************/ // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb /****************************************************************************/ DAC_ENCODER_CONTROL_PARAMETERS; #define DAC_ENCODER_CONTROL_PS_ALLOCATION … /****************************************************************************/ // Structures used by DIG1EncoderControlTable // DIG2EncoderControlTable // ExternalEncoderControlTable /****************************************************************************/ DIG_ENCODER_CONTROL_PARAMETERS; #define DIG_ENCODER_CONTROL_PS_ALLOCATION … #define EXTERNAL_ENCODER_CONTROL_PARAMETER … //ucConfig #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK … #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ … #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ … #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ … #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK … #define ATOM_ENCODER_CONFIG_LINKA … #define ATOM_ENCODER_CONFIG_LINKB … #define ATOM_ENCODER_CONFIG_LINKA_B … #define ATOM_ENCODER_CONFIG_LINKB_A … #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK … #define ATOM_ENCODER_CONFIG_UNIPHY … #define ATOM_ENCODER_CONFIG_LVTMA … #define ATOM_ENCODER_CONFIG_TRANSMITTER1 … #define ATOM_ENCODER_CONFIG_TRANSMITTER2 … #define ATOM_ENCODER_CONFIG_DIGB … // ucAction // ATOM_ENABLE: Enable Encoder // ATOM_DISABLE: Disable Encoder //ucEncoderMode #define ATOM_ENCODER_MODE_DP … #define ATOM_ENCODER_MODE_LVDS … #define ATOM_ENCODER_MODE_DVI … #define ATOM_ENCODER_MODE_HDMI … #define ATOM_ENCODER_MODE_SDVO … #define ATOM_ENCODER_MODE_DP_AUDIO … #define ATOM_ENCODER_MODE_TV … #define ATOM_ENCODER_MODE_CV … #define ATOM_ENCODER_MODE_CRT … #define ATOM_ENCODER_MODE_DVO … #define ATOM_ENCODER_MODE_DP_SST … #define ATOM_ENCODER_MODE_DP_MST … ATOM_DIG_ENCODER_CONFIG_V2; DIG_ENCODER_CONTROL_PARAMETERS_V2; //ucConfig #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK … #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ … #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ … #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK … #define ATOM_ENCODER_CONFIG_V2_LINKA … #define ATOM_ENCODER_CONFIG_V2_LINKB … #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK … #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 … #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 … #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 … // ucAction: // ATOM_DISABLE // ATOM_ENABLE #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START … #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 … #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 … #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 … #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE … #define ATOM_ENCODER_CMD_DP_VIDEO_OFF … #define ATOM_ENCODER_CMD_DP_VIDEO_ON … #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS … #define ATOM_ENCODER_CMD_SETUP … #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE … // New Command for DIGxEncoderControlTable v1.5 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 … #define ATOM_ENCODER_CMD_STREAM_SETUP … #define ATOM_ENCODER_CMD_LINK_SETUP … #define ATOM_ENCODER_CMD_ENCODER_BLANK … // ucStatus #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE … #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE … //ucTableFormatRevision=1 //ucTableContentRevision=3 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver ATOM_DIG_ENCODER_CONFIG_V3; #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK … #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ … #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ … #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL … #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER … #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER … #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER … #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER … #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER … #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER … DIG_ENCODER_CONTROL_PARAMETERS_V3; //ucTableFormatRevision=1 //ucTableContentRevision=4 // start from NI // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver ATOM_DIG_ENCODER_CONFIG_V4; #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK … #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ … #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ … #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ … #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ … #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL … #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER … #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER … #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER … #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER … #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER … #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER … #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER … DIG_ENCODER_CONTROL_PARAMETERS_V4; // define ucBitPerColor: #define PANEL_BPC_UNDEFINE … #define PANEL_6BIT_PER_COLOR … #define PANEL_8BIT_PER_COLOR … #define PANEL_10BIT_PER_COLOR … #define PANEL_12BIT_PER_COLOR … #define PANEL_16BIT_PER_COLOR … //define ucPanelMode #define DP_PANEL_MODE_EXTERNAL_DP_MODE … #define DP_PANEL_MODE_INTERNAL_DP2_MODE … #define DP_PANEL_MODE_INTERNAL_DP1_MODE … ENCODER_STREAM_SETUP_PARAMETERS_V5; ENCODER_LINK_SETUP_PARAMETERS_V5; DP_PANEL_MODE_SETUP_PARAMETERS_V5; ENCODER_GENERIC_CMD_PARAMETERS_V5; //ucDigId #define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER … #define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER … #define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER … #define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER … #define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER … #define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER … #define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER … DIG_ENCODER_CONTROL_PARAMETERS_V5; /****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable // LVTMATransmitterControlTable // DVOOutputControlTable /****************************************************************************/ ATOM_DP_VS_MODE; DIG_TRANSMITTER_CONTROL_PARAMETERS; #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION … //ucInitInfo #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK … //ucConfig #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK … #define ATOM_TRANSMITTER_CONFIG_COHERENT … #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_LINKA … #define ATOM_TRANSMITTER_CONFIG_LINKB … #define ATOM_TRANSMITTER_CONFIG_LINKA_B … #define ATOM_TRANSMITTER_CONFIG_LINKB_A … #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER … #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER … #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK … #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL … #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE … #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN … #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 … #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 … #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 … #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 … #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 … #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 … //ucAction #define ATOM_TRANSMITTER_ACTION_DISABLE … #define ATOM_TRANSMITTER_ACTION_ENABLE … #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF … #define ATOM_TRANSMITTER_ACTION_LCD_BLON … #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL … #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START … #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP … #define ATOM_TRANSMITTER_ACTION_INIT … #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT … #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT … #define ATOM_TRANSMITTER_ACTION_SETUP … #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH … #define ATOM_TRANSMITTER_ACTION_POWER_ON … #define ATOM_TRANSMITTER_ACTION_POWER_OFF … // Following are used for DigTransmitterControlTable ver1.2 ATOM_DIG_TRANSMITTER_CONFIG_V2; //ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR … //Bit1 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT … //Bit2 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V2_LINKA … #define ATOM_TRANSMITTER_CONFIG_V2_LINKB … // Bit3 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER … #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER … // Bit4 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR … // Bit7:6 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 … #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 … #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 … DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; ATOM_DIG_TRANSMITTER_CONFIG_V3; DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; //ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR … //Bit1 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT … //Bit2 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V3_LINKA … #define ATOM_TRANSMITTER_CONFIG_V3_LINKB … // Bit3 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER … #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER … // Bit5:4 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK … #define ATOM_TRASMITTER_CONFIG_V3_P1PLL … #define ATOM_TRASMITTER_CONFIG_V3_P2PLL … #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT … // Bit7:6 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 … #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 … #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 … /****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable V1.4 // ASIC Families: NI // ucTableFormatRevision=1 // ucTableContentRevision=4 /****************************************************************************/ ATOM_DP_VS_MODE_V4; ATOM_DIG_TRANSMITTER_CONFIG_V4; DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; //ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR … //Bit1 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT … //Bit2 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V4_LINKA … #define ATOM_TRANSMITTER_CONFIG_V4_LINKB … // Bit3 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER … #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER … // Bit5:4 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL … #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL … #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL … #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT … // Bit7:6 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 … #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 … #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 … ATOM_DIG_TRANSMITTER_CONFIG_V5; DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; //ucPhyId #define ATOM_PHY_ID_UNIPHYA … #define ATOM_PHY_ID_UNIPHYB … #define ATOM_PHY_ID_UNIPHYC … #define ATOM_PHY_ID_UNIPHYD … #define ATOM_PHY_ID_UNIPHYE … #define ATOM_PHY_ID_UNIPHYF … #define ATOM_PHY_ID_UNIPHYG … // ucDigEncoderSel #define ATOM_TRANMSITTER_V5__DIGA_SEL … #define ATOM_TRANMSITTER_V5__DIGB_SEL … #define ATOM_TRANMSITTER_V5__DIGC_SEL … #define ATOM_TRANMSITTER_V5__DIGD_SEL … #define ATOM_TRANMSITTER_V5__DIGE_SEL … #define ATOM_TRANMSITTER_V5__DIGF_SEL … #define ATOM_TRANMSITTER_V5__DIGG_SEL … // ucDigMode #define ATOM_TRANSMITTER_DIGMODE_V5_DP … #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS … #define ATOM_TRANSMITTER_DIGMODE_V5_DVI … #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI … #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO … #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST … // ucDPLaneSet #define DP_LANE_SET__0DB_0_4V … #define DP_LANE_SET__0DB_0_6V … #define DP_LANE_SET__0DB_0_8V … #define DP_LANE_SET__0DB_1_2V … #define DP_LANE_SET__3_5DB_0_4V … #define DP_LANE_SET__3_5DB_0_6V … #define DP_LANE_SET__3_5DB_0_8V … #define DP_LANE_SET__6DB_0_4V … #define DP_LANE_SET__6DB_0_6V … #define DP_LANE_SET__9_5DB_0_4V … // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; // Bit1 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT … // Bit3:2 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT … #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL … #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL … #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL … #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT … // Bit6:4 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK … #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT … #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL … #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL … #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL … #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL … #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL … #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL … #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL … #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 … DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6; // ucDigEncoderSel #define ATOM_TRANMSITTER_V6__DIGA_SEL … #define ATOM_TRANMSITTER_V6__DIGB_SEL … #define ATOM_TRANMSITTER_V6__DIGC_SEL … #define ATOM_TRANMSITTER_V6__DIGD_SEL … #define ATOM_TRANMSITTER_V6__DIGE_SEL … #define ATOM_TRANMSITTER_V6__DIGF_SEL … #define ATOM_TRANMSITTER_V6__DIGG_SEL … // ucDigMode #define ATOM_TRANSMITTER_DIGMODE_V6_DP … #define ATOM_TRANSMITTER_DIGMODE_V6_DVI … #define ATOM_TRANSMITTER_DIGMODE_V6_HDMI … #define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST … //ucHPDSel #define ATOM_TRANSMITTER_V6_NO_HPD_SEL … #define ATOM_TRANSMITTER_V6_HPD1_SEL … #define ATOM_TRANSMITTER_V6_HPD2_SEL … #define ATOM_TRANSMITTER_V6_HPD3_SEL … #define ATOM_TRANSMITTER_V6_HPD4_SEL … #define ATOM_TRANSMITTER_V6_HPD5_SEL … #define ATOM_TRANSMITTER_V6_HPD6_SEL … /****************************************************************************/ // Structures used by ExternalEncoderControlTable V1.3 // ASIC Families: Evergreen, Llano, NI // ucTableFormatRevision=1 // ucTableContentRevision=3 /****************************************************************************/ EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; // ucAction #define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT … #define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT … #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT … #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP … #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF … #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING … #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION … #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP … // ucConfig #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK … #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ … #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ … #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ … #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS … #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 … #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 … #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 … EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; /****************************************************************************/ // Structures used by DAC1OuputControlTable // DAC2OuputControlTable // LVTMAOutputControlTable (Before DEC30) // TMDSAOutputControlTable (Before DEC30) /****************************************************************************/ DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION … #define CRT1_OUTPUT_CONTROL_PARAMETERS … #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION … #define CRT2_OUTPUT_CONTROL_PARAMETERS … #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION … #define CV1_OUTPUT_CONTROL_PARAMETERS … #define CV1_OUTPUT_CONTROL_PS_ALLOCATION … #define TV1_OUTPUT_CONTROL_PARAMETERS … #define TV1_OUTPUT_CONTROL_PS_ALLOCATION … #define DFP1_OUTPUT_CONTROL_PARAMETERS … #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION … #define DFP2_OUTPUT_CONTROL_PARAMETERS … #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION … #define LCD1_OUTPUT_CONTROL_PARAMETERS … #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION … #define DVO_OUTPUT_CONTROL_PARAMETERS … #define DVO_OUTPUT_CONTROL_PS_ALLOCATION … #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 … LVTMA_OUTPUT_CONTROL_PARAMETERS_V2; /****************************************************************************/ // Structures used by BlankCRTCTable /****************************************************************************/ BLANK_CRTC_PARAMETERS; #define BLANK_CRTC_PS_ALLOCATION … /****************************************************************************/ // Structures used by EnableCRTCTable // EnableCRTCMemReqTable // UpdateCRTC_DoubleBufferRegistersTable /****************************************************************************/ ENABLE_CRTC_PARAMETERS; #define ENABLE_CRTC_PS_ALLOCATION … /****************************************************************************/ // Structures used by SetCRTC_OverScanTable /****************************************************************************/ SET_CRTC_OVERSCAN_PARAMETERS; #define SET_CRTC_OVERSCAN_PS_ALLOCATION … /****************************************************************************/ // Structures used by SetCRTC_ReplicationTable /****************************************************************************/ SET_CRTC_REPLICATION_PARAMETERS; #define SET_CRTC_REPLICATION_PS_ALLOCATION … /****************************************************************************/ // Structures used by SelectCRTC_SourceTable /****************************************************************************/ SELECT_CRTC_SOURCE_PARAMETERS; #define SELECT_CRTC_SOURCE_PS_ALLOCATION … SELECT_CRTC_SOURCE_PARAMETERS_V2; //ucEncoderID //#define ASIC_INT_DAC1_ENCODER_ID 0x00 //#define ASIC_INT_TV_ENCODER_ID 0x02 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 //#define ASIC_EXT_TV_ENCODER_ID 0x06 //#define ASIC_INT_DVO_ENCODER_ID 0x07 //#define ASIC_INT_DIG2_ENCODER_ID 0x09 //#define ASIC_EXT_DIG_ENCODER_ID 0x05 //ucEncodeMode //#define ATOM_ENCODER_MODE_DP 0 //#define ATOM_ENCODER_MODE_LVDS 1 //#define ATOM_ENCODER_MODE_DVI 2 //#define ATOM_ENCODER_MODE_HDMI 3 //#define ATOM_ENCODER_MODE_SDVO 4 //#define ATOM_ENCODER_MODE_TV 13 //#define ATOM_ENCODER_MODE_CV 14 //#define ATOM_ENCODER_MODE_CRT 15 SELECT_CRTC_SOURCE_PARAMETERS_V3; /****************************************************************************/ // Structures used by SetPixelClockTable // GetPixelClockTable /****************************************************************************/ //Major revision=1., Minor revision=1 PIXEL_CLOCK_PARAMETERS; //Major revision=1., Minor revision=2, add ucMiscIfno //ucMiscInfo: #define MISC_FORCE_REPROG_PIXEL_CLOCK … #define MISC_DEVICE_INDEX_MASK … #define MISC_DEVICE_INDEX_SHIFT … PIXEL_CLOCK_PARAMETERS_V2; //Major revision=1., Minor revision=3, structure/definition change //ucEncoderMode: //ATOM_ENCODER_MODE_DP //ATOM_ENOCDER_MODE_LVDS //ATOM_ENOCDER_MODE_DVI //ATOM_ENOCDER_MODE_HDMI //ATOM_ENOCDER_MODE_SDVO //ATOM_ENCODER_MODE_TV 13 //ATOM_ENCODER_MODE_CV 14 //ATOM_ENCODER_MODE_CRT 15 //ucDVOConfig //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 //#define DVO_ENCODER_CONFIG_24BIT 0x08 //ucMiscInfo: also changed, see below #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL … #define PIXEL_CLOCK_MISC_VGA_MODE … #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK … #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 … #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 … #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK … #define PIXEL_CLOCK_MISC_REF_DIV_SRC … // V1.4 for RoadRunner #define PIXEL_CLOCK_V4_MISC_SS_ENABLE … #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE … PIXEL_CLOCK_PARAMETERS_V3; #define PIXEL_CLOCK_PARAMETERS_LAST … #define GET_PIXEL_CLOCK_PS_ALLOCATION … PIXEL_CLOCK_PARAMETERS_V5; #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL … #define PIXEL_CLOCK_V5_MISC_VGA_MODE … #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK … #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP … #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP … #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP … #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC … CRTC_PIXEL_CLOCK_FREQ; PIXEL_CLOCK_PARAMETERS_V6; #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL … #define PIXEL_CLOCK_V6_MISC_VGA_MODE … #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK … #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP … #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP … #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 … #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP … #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 … #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP … #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC … #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK … #define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS … GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; PIXEL_CLOCK_PARAMETERS_V7; //ucMiscInfo #define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL … #define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL … #define PIXEL_CLOCK_V7_MISC_YUV420_MODE … #define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN … #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC … #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN … #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE … #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK … //ucDeepColorRatio #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS … #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 … #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 … #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 … // SetDCEClockTable input parameter for DCE11.1 SET_DCE_CLOCK_PARAMETERS_V1_1; SET_DCE_CLOCK_PS_ALLOCATION_V1_1; //SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag #define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK … #define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS … #define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK … // SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above SET_DCE_CLOCK_PARAMETERS_V2_1; //ucDCEClkType #define DCE_CLOCK_TYPE_DISPCLK … #define DCE_CLOCK_TYPE_DPREFCLK … #define DCE_CLOCK_TYPE_PIXELCLK … //ucDCEClkFlag when ucDCEClkType == DPREFCLK #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK … #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA … #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK … #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE … #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN … //ucDCEClkFlag when ucDCEClkType == PIXCLK #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK … #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS … #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 … #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 … #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 … #define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE … SET_DCE_CLOCK_PS_ALLOCATION_V2_1; /****************************************************************************/ // Structures used by AdjustDisplayPllTable /****************************************************************************/ ADJUST_DISPLAY_PLL_PARAMETERS; #define ADJUST_DISPLAY_CONFIG_SS_ENABLE … #define ADJUST_DISPLAY_PLL_PS_ALLOCATION … ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; // usDispPllConfig v1.2 for RoadRunner #define DISPPLL_CONFIG_DVO_RATE_SEL … #define DISPPLL_CONFIG_DVO_DDR_SPEED … #define DISPPLL_CONFIG_DVO_SDR_SPEED … #define DISPPLL_CONFIG_DVO_OUTPUT_SEL … #define DISPPLL_CONFIG_DVO_LOW12BIT … #define DISPPLL_CONFIG_DVO_UPPER12BIT … #define DISPPLL_CONFIG_DVO_24BIT … #define DISPPLL_CONFIG_SS_ENABLE … #define DISPPLL_CONFIG_COHERENT_MODE … #define DISPPLL_CONFIG_DUAL_LINK … ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; /****************************************************************************/ // Structures used by EnableYUVTable /****************************************************************************/ ENABLE_YUV_PARAMETERS; #define ENABLE_YUV_PS_ALLOCATION … /****************************************************************************/ // Structures used by GetMemoryClockTable /****************************************************************************/ GET_MEMORY_CLOCK_PARAMETERS; #define GET_MEMORY_CLOCK_PS_ALLOCATION … /****************************************************************************/ // Structures used by GetEngineClockTable /****************************************************************************/ GET_ENGINE_CLOCK_PARAMETERS; #define GET_ENGINE_CLOCK_PS_ALLOCATION … /****************************************************************************/ // Following Structures and constant may be obsolete /****************************************************************************/ //Maxium 8 bytes,the data read in will be placed in the parameter space. //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION … #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE … #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES … #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK … #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK … #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK … WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION … SET_UP_HW_I2C_DATA_PARAMETERS; /**************************************************************************/ #define SPEED_FAN_CONTROL_PS_ALLOCATION … /****************************************************************************/ // Structures used by PowerConnectorDetectionTable /****************************************************************************/ POWER_CONNECTOR_DETECTION_PARAMETERS; POWER_CONNECTOR_DETECTION_PS_ALLOCATION; /****************************LVDS SS Command Table Definitions**********************/ /****************************************************************************/ // Structures used by EnableSpreadSpectrumOnPPLLTable /****************************************************************************/ ENABLE_LVDS_SS_PARAMETERS; //ucTableFormatRevision=1,ucTableContentRevision=2 ENABLE_LVDS_SS_PARAMETERS_V2; //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. ENABLE_SPREAD_SPECTRUM_ON_PPLL; ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD … #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD … #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD … #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK … #define ATOM_PPLL_SS_TYPE_V2_P1PLL … #define ATOM_PPLL_SS_TYPE_V2_P2PLL … #define ATOM_PPLL_SS_TYPE_V2_DCPLL … #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK … #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT … #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK … #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT … // Used by DCE5.0 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD … #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD … #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD … #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK … #define ATOM_PPLL_SS_TYPE_V3_P1PLL … #define ATOM_PPLL_SS_TYPE_V3_P2PLL … #define ATOM_PPLL_SS_TYPE_V3_DCPLL … #define ATOM_PPLL_SS_TYPE_V3_P0PLL … #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK … #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT … #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK … #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT … #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION … SET_PIXEL_CLOCK_PS_ALLOCATION; #define ENABLE_VGA_RENDER_PS_ALLOCATION … /****************************************************************************/ // Structures used by ### /****************************************************************************/ MEMORY_TRAINING_PARAMETERS; #define MEMORY_TRAINING_PS_ALLOCATION … MEMORY_TRAINING_PARAMETERS_V1_2; //usMemTrainingMode #define NORMAL_MEMORY_TRAINING_MODE … #define ENTER_DRAM_SELFREFRESH_MODE … #define EXIT_DRAM_SELFRESH_MODE … /****************************LVDS and other encoder command table definitions **********************/ /****************************************************************************/ // Structures used by LVDSEncoderControlTable (Before DEC30) // LVTMAEncoderControlTable (Before DEC30) // TMDSAEncoderControlTable (Before DEC30) /****************************************************************************/ LVDS_ENCODER_CONTROL_PARAMETERS; #define LVDS_ENCODER_CONTROL_PS_ALLOCATION … #define TMDS1_ENCODER_CONTROL_PARAMETERS … #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION … #define TMDS2_ENCODER_CONTROL_PARAMETERS … #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION … //ucTableFormatRevision=1,ucTableContentRevision=2 LVDS_ENCODER_CONTROL_PARAMETERS_V2; #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 … #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 … #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 … #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 … #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 … #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 … #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 … #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 … #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 … #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 … #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 … /****************************************************************************/ // Structures used by ### /****************************************************************************/ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 … ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; /****************************************************************************/ // Structures used by DVOEncoderControlTable /****************************************************************************/ //ucTableFormatRevision=1,ucTableContentRevision=3 //ucDVOConfig: #define DVO_ENCODER_CONFIG_RATE_SEL … #define DVO_ENCODER_CONFIG_DDR_SPEED … #define DVO_ENCODER_CONFIG_SDR_SPEED … #define DVO_ENCODER_CONFIG_OUTPUT_SEL … #define DVO_ENCODER_CONFIG_LOW12BIT … #define DVO_ENCODER_CONFIG_UPPER12BIT … #define DVO_ENCODER_CONFIG_24BIT … DVO_ENCODER_CONTROL_PARAMETERS_V3; #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 … DVO_ENCODER_CONTROL_PARAMETERS_V1_4; #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 … //ucTableFormatRevision=1 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for // bit1=0: non-coherent mode // =1: coherent mode //========================================================================================== //Only change is here next time when changing encoder parameter definitions again! #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST … #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST … #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST … #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST … #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST … #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST … #define DVO_ENCODER_CONTROL_PARAMETERS_LAST … #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST … //========================================================================================== #define PANEL_ENCODER_MISC_DUAL … #define PANEL_ENCODER_MISC_COHERENT … #define PANEL_ENCODER_MISC_TMDS_LINKB … #define PANEL_ENCODER_MISC_HDMI_TYPE … #define PANEL_ENCODER_ACTION_DISABLE … #define PANEL_ENCODER_ACTION_ENABLE … #define PANEL_ENCODER_ACTION_COHERENTSEQ … #define PANEL_ENCODER_TRUNCATE_EN … #define PANEL_ENCODER_TRUNCATE_DEPTH … #define PANEL_ENCODER_SPATIAL_DITHER_EN … #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH … #define PANEL_ENCODER_TEMPORAL_DITHER_EN … #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH … #define PANEL_ENCODER_TEMPORAL_LEVEL_4 … #define PANEL_ENCODER_25FRC_MASK … #define PANEL_ENCODER_25FRC_E … #define PANEL_ENCODER_25FRC_F … #define PANEL_ENCODER_50FRC_MASK … #define PANEL_ENCODER_50FRC_A … #define PANEL_ENCODER_50FRC_B … #define PANEL_ENCODER_50FRC_C … #define PANEL_ENCODER_50FRC_D … #define PANEL_ENCODER_75FRC_MASK … #define PANEL_ENCODER_75FRC_E … #define PANEL_ENCODER_75FRC_F … /****************************************************************************/ // Structures used by SetVoltageTable /****************************************************************************/ #define SET_VOLTAGE_TYPE_ASIC_VDDC … #define SET_VOLTAGE_TYPE_ASIC_MVDDC … #define SET_VOLTAGE_TYPE_ASIC_MVDDQ … #define SET_VOLTAGE_TYPE_ASIC_VDDCI … #define SET_VOLTAGE_INIT_MODE … #define SET_VOLTAGE_GET_MAX_VOLTAGE … #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE … #define SET_ASIC_VOLTAGE_MODE_SOURCE_A … #define SET_ASIC_VOLTAGE_MODE_SOURCE_B … #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE … #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL … #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK … SET_VOLTAGE_PARAMETERS; SET_VOLTAGE_PARAMETERS_V2; // used by both SetVoltageTable v1.3 and v1.4 SET_VOLTAGE_PARAMETERS_V1_3; //ucVoltageType #define VOLTAGE_TYPE_VDDC … #define VOLTAGE_TYPE_MVDDC … #define VOLTAGE_TYPE_MVDDQ … #define VOLTAGE_TYPE_VDDCI … #define VOLTAGE_TYPE_VDDGFX … #define VOLTAGE_TYPE_PCC … #define VOLTAGE_TYPE_MVPP … #define VOLTAGE_TYPE_LEDDPM … #define VOLTAGE_TYPE_PCC_MVDD … #define VOLTAGE_TYPE_PCIE_VDDC … #define VOLTAGE_TYPE_PCIE_VDDR … #define VOLTAGE_TYPE_GENERIC_I2C_1 … #define VOLTAGE_TYPE_GENERIC_I2C_2 … #define VOLTAGE_TYPE_GENERIC_I2C_3 … #define VOLTAGE_TYPE_GENERIC_I2C_4 … #define VOLTAGE_TYPE_GENERIC_I2C_5 … #define VOLTAGE_TYPE_GENERIC_I2C_6 … #define VOLTAGE_TYPE_GENERIC_I2C_7 … #define VOLTAGE_TYPE_GENERIC_I2C_8 … #define VOLTAGE_TYPE_GENERIC_I2C_9 … #define VOLTAGE_TYPE_GENERIC_I2C_10 … //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode #define ATOM_SET_VOLTAGE … #define ATOM_INIT_VOLTAGE_REGULATOR … #define ATOM_SET_VOLTAGE_PHASE … #define ATOM_GET_MAX_VOLTAGE … #define ATOM_GET_VOLTAGE_LEVEL … #define ATOM_GET_LEAKAGE_ID … // define vitual voltage id in usVoltageLevel #define ATOM_VIRTUAL_VOLTAGE_ID0 … #define ATOM_VIRTUAL_VOLTAGE_ID1 … #define ATOM_VIRTUAL_VOLTAGE_ID2 … #define ATOM_VIRTUAL_VOLTAGE_ID3 … #define ATOM_VIRTUAL_VOLTAGE_ID4 … #define ATOM_VIRTUAL_VOLTAGE_ID5 … #define ATOM_VIRTUAL_VOLTAGE_ID6 … #define ATOM_VIRTUAL_VOLTAGE_ID7 … SET_VOLTAGE_PS_ALLOCATION; // New Added from SI for GetVoltageInfoTable, input parameter structure GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; // GetVoltageInfo v1.1 ucVoltageMode #define ATOM_GET_VOLTAGE_VID … #define ATOM_GET_VOTLAGE_INIT_SEQ … #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID … #define ATOM_GET_VOLTAGE_SVID2 … // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID … // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID … #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID … #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID … // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; // New in GetVoltageInfo v1.2 ucVoltageMode #define ATOM_GET_VOLTAGE_EVV_VOLTAGE … // New Added from CI Hawaii for EVV feature GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3; // New Added from CI Hawaii for EVV feature GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3; /****************************************************************************/ // Structures used by GetSMUClockInfo /****************************************************************************/ GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1; GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1; /****************************************************************************/ // Structures used by TVEncoderControlTable /****************************************************************************/ TV_ENCODER_CONTROL_PARAMETERS; TV_ENCODER_CONTROL_PS_ALLOCATION; //==============================Data Table Portion==================================== /****************************************************************************/ // Structure used in Data.mtb /****************************************************************************/ ATOM_MASTER_LIST_OF_DATA_TABLES; ATOM_MASTER_DATA_TABLE; // For backward compatible #define LVDS_Info … #define DAC_Info … #define TMDS_Info … #define CompassionateData … #define AnalogTV_Info … #define ComponentVideoInfo … /****************************************************************************/ // Structure used in MultimediaCapabilityInfoTable /****************************************************************************/ ATOM_MULTIMEDIA_CAPABILITY_INFO; /****************************************************************************/ // Structure used in MultimediaConfigInfoTable /****************************************************************************/ ATOM_MULTIMEDIA_CONFIG_INFO; /****************************************************************************/ // Structures used in FirmwareInfoTable /****************************************************************************/ // usBIOSCapability Defintion: // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; // Others: Reserved #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED … #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT … #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT … #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT … #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT … #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU … #define ATOM_BIOS_INFO_WMI_SUPPORT … #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM … #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT … #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK … #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET … #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE … #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT … #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT … #ifndef _H2INC //Please don't add or expand this bitfield structure below, this one will retire soon.! ATOM_FIRMWARE_CAPABILITY; ATOM_FIRMWARE_CAPABILITY_ACCESS; #else typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS { USHORT susAccess; }ATOM_FIRMWARE_CAPABILITY_ACCESS; #endif ATOM_FIRMWARE_INFO; ATOM_FIRMWARE_INFO_V1_2; ATOM_FIRMWARE_INFO_V1_3; ATOM_FIRMWARE_INFO_V1_4; //the structure below to be used from Cypress ATOM_FIRMWARE_INFO_V2_1; //the structure below to be used from NI //ucTableFormatRevision=2 //ucTableContentRevision=2 PRODUCT_BRANDING; ATOM_FIRMWARE_INFO_V2_2; #define ATOM_FIRMWARE_INFO_LAST … // definition of ucRemoteDisplayConfig #define REMOTE_DISPLAY_DISABLE … #define REMOTE_DISPLAY_ENABLE … /****************************************************************************/ // Structures used in IntegratedSystemInfoTable /****************************************************************************/ #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN … #define IGP_CAP_FLAG_AC_CARD … #define IGP_CAP_FLAG_SDVO_CARD … #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE … ATOM_INTEGRATED_SYSTEM_INFO; /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 usFSBClock: For Intel IGP,it's FSB Freq For AMD IGP,it's HT Link Speed usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation VC:Voltage Control ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. */ /* The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. SW components can access the IGP system infor structure in the same way as before */ ATOM_INTEGRATED_SYSTEM_INFO_V2; /* ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock ulSystemConfig: Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state =0: system boots up at driver control state. Power state depends on PowerPlay table. Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. Bit[3]=1: Only one power state(Performance) will be supported. =0: Multiple power states supported from PowerPlay table. Bit[4]=1: CLMC is supported and enabled on current system. =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. =0: Voltage settings is determined by powerplay table. Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. Bit[8]=1: CDLF is supported and enabled on current system. =0: CDLF is not supported or enabled on current system. Bit[9]=1: DLL Shut Down feature is enabled on current system. =0: DLL Shut Down feature is not enabled or supported on current system. ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. [15:8] - Lane configuration attribute; [23:16]- Connector type, possible value: CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D CONNECTOR_OBJECT_ID_HDMI_TYPE_A CONNECTOR_OBJECT_ID_DISPLAYPORT CONNECTOR_OBJECT_ID_eDP [31:24]- Reserved ulDDISlot2Config: Same as Slot1. ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. For IGP, Hypermemory is the only memory type showed in CCC. ucUMAChannelNumber: how many channels for the UMA; ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin ucDockingPinBit: which bit in this register to read the pin status; ucDockingPinPolarity:Polarity of the pin when docked; ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. ulHTLinkFreq: Bootup HT link Frequency in 10Khz. usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. If CDLW enabled, both upstream and downstream width should be the same during bootup. usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. If CDLW enabled, both upstream and downstream width should be the same during bootup. usUMASyncStartDelay: Memory access latency, required for watermark calculation usUMADataReturnTime: Memory access latency, required for watermark calculation usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. This must be less than or equal to ulHTLinkFreq(bootup frequency). ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. This must be less than or equal to ulHighVoltageHTLinkFreq. usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. usMaxDownStreamHTLinkWidth: same as above. usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. usMinDownStreamHTLinkWidth: same as above. */ // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU … #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN … #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND … #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 … #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH … #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI … #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE … #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE … #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE … #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE … #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY … #define SYSTEM_CONFIG_CLMC_ENABLED … #define SYSTEM_CONFIG_CDLW_ENABLED … #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED … #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED … #define SYSTEM_CONFIG_CDLF_ENABLED … #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED … #define IGP_DDI_SLOT_LANE_CONFIG_MASK … #define b0IGP_DDI_SLOT_LANE_MAP_MASK … #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK … #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 … #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 … #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 … #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 … #define IGP_DDI_SLOT_ATTRIBUTE_MASK … #define IGP_DDI_SLOT_CONFIG_REVERSED … #define b1IGP_DDI_SLOT_CONFIG_REVERSED … #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK … // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR ATOM_INTEGRATED_SYSTEM_INFO_V5; /****************************************************************************/ // Structure used in GPUVirtualizationInfoTable /****************************************************************************/ ATOM_GPU_VIRTUALIZATION_INFO_V2_1; #define ATOM_CRT_INT_ENCODER1_INDEX … #define ATOM_LCD_INT_ENCODER1_INDEX … #define ATOM_TV_INT_ENCODER1_INDEX … #define ATOM_DFP_INT_ENCODER1_INDEX … #define ATOM_CRT_INT_ENCODER2_INDEX … #define ATOM_LCD_EXT_ENCODER1_INDEX … #define ATOM_TV_EXT_ENCODER1_INDEX … #define ATOM_DFP_EXT_ENCODER1_INDEX … #define ATOM_CV_INT_ENCODER1_INDEX … #define ATOM_DFP_INT_ENCODER2_INDEX … #define ATOM_CRT_EXT_ENCODER1_INDEX … #define ATOM_CV_EXT_ENCODER1_INDEX … #define ATOM_DFP_INT_ENCODER3_INDEX … #define ATOM_DFP_INT_ENCODER4_INDEX … // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable #define ASIC_INT_DAC1_ENCODER_ID … #define ASIC_INT_TV_ENCODER_ID … #define ASIC_INT_DIG1_ENCODER_ID … #define ASIC_INT_DAC2_ENCODER_ID … #define ASIC_EXT_TV_ENCODER_ID … #define ASIC_INT_DVO_ENCODER_ID … #define ASIC_INT_DIG2_ENCODER_ID … #define ASIC_EXT_DIG_ENCODER_ID … #define ASIC_EXT_DIG2_ENCODER_ID … #define ASIC_INT_DIG3_ENCODER_ID … #define ASIC_INT_DIG4_ENCODER_ID … #define ASIC_INT_DIG5_ENCODER_ID … #define ASIC_INT_DIG6_ENCODER_ID … #define ASIC_INT_DIG7_ENCODER_ID … //define Encoder attribute #define ATOM_ANALOG_ENCODER … #define ATOM_DIGITAL_ENCODER … #define ATOM_DP_ENCODER … #define ATOM_ENCODER_ENUM_MASK … #define ATOM_ENCODER_ENUM_ID1 … #define ATOM_ENCODER_ENUM_ID2 … #define ATOM_ENCODER_ENUM_ID3 … #define ATOM_ENCODER_ENUM_ID4 … #define ATOM_ENCODER_ENUM_ID5 … #define ATOM_ENCODER_ENUM_ID6 … #define ATOM_DEVICE_CRT1_INDEX … #define ATOM_DEVICE_LCD1_INDEX … #define ATOM_DEVICE_TV1_INDEX … #define ATOM_DEVICE_DFP1_INDEX … #define ATOM_DEVICE_CRT2_INDEX … #define ATOM_DEVICE_LCD2_INDEX … #define ATOM_DEVICE_DFP6_INDEX … #define ATOM_DEVICE_DFP2_INDEX … #define ATOM_DEVICE_CV_INDEX … #define ATOM_DEVICE_DFP3_INDEX … #define ATOM_DEVICE_DFP4_INDEX … #define ATOM_DEVICE_DFP5_INDEX … #define ATOM_DEVICE_RESERVEDC_INDEX … #define ATOM_DEVICE_RESERVEDD_INDEX … #define ATOM_DEVICE_RESERVEDE_INDEX … #define ATOM_DEVICE_RESERVEDF_INDEX … #define ATOM_MAX_SUPPORTED_DEVICE_INFO … #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 … #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 … #define ATOM_MAX_SUPPORTED_DEVICE … #define ATOM_DEVICE_CRT1_SUPPORT … #define ATOM_DEVICE_LCD1_SUPPORT … #define ATOM_DEVICE_TV1_SUPPORT … #define ATOM_DEVICE_DFP1_SUPPORT … #define ATOM_DEVICE_CRT2_SUPPORT … #define ATOM_DEVICE_LCD2_SUPPORT … #define ATOM_DEVICE_DFP6_SUPPORT … #define ATOM_DEVICE_DFP2_SUPPORT … #define ATOM_DEVICE_CV_SUPPORT … #define ATOM_DEVICE_DFP3_SUPPORT … #define ATOM_DEVICE_DFP4_SUPPORT … #define ATOM_DEVICE_DFP5_SUPPORT … #define ATOM_DEVICE_CRT_SUPPORT … #define ATOM_DEVICE_DFP_SUPPORT … #define ATOM_DEVICE_TV_SUPPORT … #define ATOM_DEVICE_LCD_SUPPORT … #define ATOM_DEVICE_CONNECTOR_TYPE_MASK … #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT … #define ATOM_DEVICE_CONNECTOR_VGA … #define ATOM_DEVICE_CONNECTOR_DVI_I … #define ATOM_DEVICE_CONNECTOR_DVI_D … #define ATOM_DEVICE_CONNECTOR_DVI_A … #define ATOM_DEVICE_CONNECTOR_SVIDEO … #define ATOM_DEVICE_CONNECTOR_COMPOSITE … #define ATOM_DEVICE_CONNECTOR_LVDS … #define ATOM_DEVICE_CONNECTOR_DIGI_LINK … #define ATOM_DEVICE_CONNECTOR_SCART … #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A … #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B … #define ATOM_DEVICE_CONNECTOR_CASE_1 … #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT … #define ATOM_DEVICE_DAC_INFO_MASK … #define ATOM_DEVICE_DAC_INFO_SHIFT … #define ATOM_DEVICE_DAC_INFO_NODAC … #define ATOM_DEVICE_DAC_INFO_DACA … #define ATOM_DEVICE_DAC_INFO_DACB … #define ATOM_DEVICE_DAC_INFO_EXDAC … #define ATOM_DEVICE_I2C_ID_NOI2C … #define ATOM_DEVICE_I2C_LINEMUX_MASK … #define ATOM_DEVICE_I2C_LINEMUX_SHIFT … #define ATOM_DEVICE_I2C_ID_MASK … #define ATOM_DEVICE_I2C_ID_SHIFT … #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE … #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE … #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE … #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL … #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK … #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT … #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C … #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C … // usDeviceSupport: // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported // Bit 2 = 0 - no TV1 support= 1- TV1 is supported // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported // Bit 8 = 0 - no CV support= 1- CV is supported // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported // // /****************************************************************************/ // Structure used in MclkSS_InfoTable /****************************************************************************/ // ucI2C_ConfigID // [7:0] - I2C LINE Associate ID // = 0 - no I2C // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) // = 0, [6:0]=SW assisted I2C ID // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use // = 2, HW engine for Multimedia use // = 3-7 Reserved for future I2C engines // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C ATOM_I2C_ID_CONFIG; ATOM_I2C_ID_CONFIG_ACCESS; /****************************************************************************/ // Structure used in GPIO_I2C_InfoTable /****************************************************************************/ ATOM_GPIO_I2C_ASSIGMENT; ATOM_GPIO_I2C_INFO; /****************************************************************************/ // Common Structure used in other structures /****************************************************************************/ #ifndef _H2INC //Please don't add or expand this bitfield structure below, this one will retire soon.! ATOM_MODE_MISC_INFO; ATOM_MODE_MISC_INFO_ACCESS; #else typedef union _ATOM_MODE_MISC_INFO_ACCESS { USHORT usAccess; }ATOM_MODE_MISC_INFO_ACCESS; #endif // usModeMiscInfo- #define ATOM_H_CUTOFF … #define ATOM_HSYNC_POLARITY … #define ATOM_VSYNC_POLARITY … #define ATOM_V_CUTOFF … #define ATOM_H_REPLICATIONBY2 … #define ATOM_V_REPLICATIONBY2 … #define ATOM_COMPOSITESYNC … #define ATOM_INTERLACE … #define ATOM_DOUBLE_CLOCK_MODE … #define ATOM_RGB888_MODE … //usRefreshRate- #define ATOM_REFRESH_43 … #define ATOM_REFRESH_47 … #define ATOM_REFRESH_56 … #define ATOM_REFRESH_60 … #define ATOM_REFRESH_65 … #define ATOM_REFRESH_70 … #define ATOM_REFRESH_72 … #define ATOM_REFRESH_75 … #define ATOM_REFRESH_85 … // ATOM_MODE_TIMING data are exactly the same as VESA timing data. // Translation from EDID to ATOM_MODE_TIMING, use the following formula. // // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK // = EDID_HA + EDID_HBL // VESA_HDISP = VESA_ACTIVE = EDID_HA // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH // = EDID_HA + EDID_HSO // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW // VESA_BORDER = EDID_BORDER /****************************************************************************/ // Structure used in SetCRTC_UsingDTDTimingTable /****************************************************************************/ SET_CRTC_USING_DTD_TIMING_PARAMETERS; /****************************************************************************/ // Structure used in SetCRTC_TimingTable /****************************************************************************/ SET_CRTC_TIMING_PARAMETERS; #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION … /****************************************************************************/ // Structure used in StandardVESA_TimingTable // AnalogTV_InfoTable // ComponentVideoInfoTable /****************************************************************************/ ATOM_MODE_TIMING; ATOM_DTD_FORMAT; /****************************************************************************/ // Structure used in LVDS_InfoTable // * Need a document to describe this table /****************************************************************************/ #define SUPPORTED_LCD_REFRESHRATE_30Hz … #define SUPPORTED_LCD_REFRESHRATE_40Hz … #define SUPPORTED_LCD_REFRESHRATE_50Hz … #define SUPPORTED_LCD_REFRESHRATE_60Hz … #define SUPPORTED_LCD_REFRESHRATE_48Hz … //ucTableFormatRevision=1 //ucTableContentRevision=1 ATOM_LVDS_INFO; //ucTableFormatRevision=1 //ucTableContentRevision=2 ATOM_LVDS_INFO_V12; //Definitions for ucLCDPanel_SpecialHandlingCap: //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL #define LCDPANEL_CAP_READ_EDID … //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 #define LCDPANEL_CAP_DRR_SUPPORTED … //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. #define LCDPANEL_CAP_eDP … //Color Bit Depth definition in EDID V1.4 @BYTE 14h //Bit 6 5 4 // 0 0 0 - Color bit depth is undefined // 0 0 1 - 6 Bits per Primary Color // 0 1 0 - 8 Bits per Primary Color // 0 1 1 - 10 Bits per Primary Color // 1 0 0 - 12 Bits per Primary Color // 1 0 1 - 14 Bits per Primary Color // 1 1 0 - 16 Bits per Primary Color // 1 1 1 - Reserved #define PANEL_COLOR_BIT_DEPTH_MASK … // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} #define PANEL_RANDOM_DITHER … #define PANEL_RANDOM_DITHER_MASK … #define ATOM_LVDS_INFO_LAST … ATOM_LCD_REFRESH_RATE_SUPPORT; /****************************************************************************/ // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 // ASIC Families: NI // ucTableFormatRevision=1 // ucTableContentRevision=3 /****************************************************************************/ ATOM_LCD_INFO_V13; #define ATOM_LCD_INFO_LAST … //Definitions for ucLCD_Misc #define ATOM_PANEL_MISC_V13_DUAL … #define ATOM_PANEL_MISC_V13_FPDI … #define ATOM_PANEL_MISC_V13_GREY_LEVEL … #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT … #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK … #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR … #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR … //Color Bit Depth definition in EDID V1.4 @BYTE 14h //Bit 6 5 4 // 0 0 0 - Color bit depth is undefined // 0 0 1 - 6 Bits per Primary Color // 0 1 0 - 8 Bits per Primary Color // 0 1 1 - 10 Bits per Primary Color // 1 0 0 - 12 Bits per Primary Color // 1 0 1 - 14 Bits per Primary Color // 1 1 0 - 16 Bits per Primary Color // 1 1 1 - Reserved //Definitions for ucLCDPanel_SpecialHandlingCap: //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL #define LCDPANEL_CAP_V13_READ_EDID … //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 #define LCDPANEL_CAP_V13_DRR_SUPPORTED … //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. #define LCDPANEL_CAP_V13_eDP … //uceDPToLVDSRxId #define eDP_TO_LVDS_RX_DISABLE … #define eDP_TO_LVDS_COMMON_ID … #define eDP_TO_LVDS_RT_ID … ATOM_PATCH_RECORD_MODE; ATOM_LCD_RTS_RECORD; //!! If the record below exits, it shoud always be the first record for easy use in command table!!! // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. ATOM_LCD_MODE_CONTROL_CAP; #define LCD_MODE_CAP_BL_OFF … #define LCD_MODE_CAP_CRTC_OFF … #define LCD_MODE_CAP_PANEL_OFF … ATOM_FAKE_EDID_PATCH_RECORD; ATOM_PANEL_RESOLUTION_PATCH_RECORD; #define LCD_MODE_PATCH_RECORD_MODE_TYPE … #define LCD_RTS_RECORD_TYPE … #define LCD_CAP_RECORD_TYPE … #define LCD_FAKE_EDID_PATCH_RECORD_TYPE … #define LCD_PANEL_RESOLUTION_RECORD_TYPE … #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE … #define ATOM_RECORD_END_TYPE … /****************************Spread Spectrum Info Table Definitions **********************/ //ucTableFormatRevision=1 //ucTableContentRevision=2 ATOM_SPREAD_SPECTRUM_ASSIGNMENT; #define ATOM_MAX_SS_ENTRY … #define ATOM_DP_SS_ID1 … #define ATOM_DP_SS_ID2 … #define ATOM_LVLINK_2700MHz_SS_ID … #define ATOM_LVLINK_1620MHz_SS_ID … #define ATOM_SS_DOWN_SPREAD_MODE_MASK … #define ATOM_SS_DOWN_SPREAD_MODE … #define ATOM_SS_CENTRE_SPREAD_MODE_MASK … #define ATOM_SS_CENTRE_SPREAD_MODE … #define ATOM_INTERNAL_SS_MASK … #define ATOM_EXTERNAL_SS_MASK … #define EXEC_SS_STEP_SIZE_SHIFT … #define EXEC_SS_DELAY_SHIFT … #define ACTIVEDATA_TO_BLON_DELAY_SHIFT … ATOM_SPREAD_SPECTRUM_INFO; /****************************************************************************/ // Structure used in AnalogTV_InfoTable (Top level) /****************************************************************************/ //ucTVBootUpDefaultStd definiton: //ATOM_TV_NTSC 1 //ATOM_TV_NTSCJ 2 //ATOM_TV_PAL 3 //ATOM_TV_PALM 4 //ATOM_TV_PALCN 5 //ATOM_TV_PALN 6 //ATOM_TV_PAL60 7 //ATOM_TV_SECAM 8 //ucTVSuppportedStd definition: #define NTSC_SUPPORT … #define NTSCJ_SUPPORT … #define PAL_SUPPORT … #define PALM_SUPPORT … #define PALCN_SUPPORT … #define PALN_SUPPORT … #define PAL60_SUPPORT … #define SECAM_SUPPORT … #define MAX_SUPPORTED_TV_TIMING … ATOM_ANALOG_TV_INFO; ATOM_DPCD_INFO; #define ATOM_DPCD_MAX_LANE_MASK … /**************************************************************************/ // VRAM usage and their defintions // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX // Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). //#ifndef VESA_MEMORY_IN_64K_BLOCK //#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) //#endif #define ATOM_EDID_RAW_DATASIZE … #define ATOM_HWICON_SURFACE_SIZE … #define ATOM_HWICON_INFOTABLE_SIZE … #define MAX_DTD_MODE_IN_VRAM … #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE … #define ATOM_STD_MODE_SUPPORT_TBL_SIZE … //20 bytes for Encoder Type and DPCD in STD EDID area #define DFP_ENCODER_TYPE_OFFSET … #define ATOM_DP_DPCD_OFFSET … #define ATOM_HWICON1_SURFACE_ADDR … #define ATOM_HWICON2_SURFACE_ADDR … #define ATOM_HWICON_INFOTABLE_ADDR … #define ATOM_CRT1_EDID_ADDR … #define ATOM_CRT1_DTD_MODE_TBL_ADDR … #define ATOM_CRT1_STD_MODE_TBL_ADDR … #define ATOM_LCD1_EDID_ADDR … #define ATOM_LCD1_DTD_MODE_TBL_ADDR … #define ATOM_LCD1_STD_MODE_TBL_ADDR … #define ATOM_TV1_DTD_MODE_TBL_ADDR … #define ATOM_DFP1_EDID_ADDR … #define ATOM_DFP1_DTD_MODE_TBL_ADDR … #define ATOM_DFP1_STD_MODE_TBL_ADDR … #define ATOM_CRT2_EDID_ADDR … #define ATOM_CRT2_DTD_MODE_TBL_ADDR … #define ATOM_CRT2_STD_MODE_TBL_ADDR … #define ATOM_LCD2_EDID_ADDR … #define ATOM_LCD2_DTD_MODE_TBL_ADDR … #define ATOM_LCD2_STD_MODE_TBL_ADDR … #define ATOM_DFP6_EDID_ADDR … #define ATOM_DFP6_DTD_MODE_TBL_ADDR … #define ATOM_DFP6_STD_MODE_TBL_ADDR … #define ATOM_DFP2_EDID_ADDR … #define ATOM_DFP2_DTD_MODE_TBL_ADDR … #define ATOM_DFP2_STD_MODE_TBL_ADDR … #define ATOM_CV_EDID_ADDR … #define ATOM_CV_DTD_MODE_TBL_ADDR … #define ATOM_CV_STD_MODE_TBL_ADDR … #define ATOM_DFP3_EDID_ADDR … #define ATOM_DFP3_DTD_MODE_TBL_ADDR … #define ATOM_DFP3_STD_MODE_TBL_ADDR … #define ATOM_DFP4_EDID_ADDR … #define ATOM_DFP4_DTD_MODE_TBL_ADDR … #define ATOM_DFP4_STD_MODE_TBL_ADDR … #define ATOM_DFP5_EDID_ADDR … #define ATOM_DFP5_DTD_MODE_TBL_ADDR … #define ATOM_DFP5_STD_MODE_TBL_ADDR … #define ATOM_DP_TRAINING_TBL_ADDR … #define ATOM_STACK_STORAGE_START … #define ATOM_STACK_STORAGE_END … //The size below is in Kb! #define ATOM_VRAM_RESERVE_SIZE … #define ATOM_VRAM_RESERVE_V2_SIZE … #define ATOM_VRAM_OPERATION_FLAGS_MASK … #define ATOM_VRAM_OPERATION_FLAGS_SHIFT … #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION … #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION … #define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION … /***********************************************************************************/ // Structure used in VRAM_UsageByFirmwareTable // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm // at running time. // note2: From RV770, the memory is more than 32bit addressable, so we will change // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware // (in offset to start of memory address) is KB aligned instead of byte aligend. // Note3: /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: If (ulStartAddrUsedByFirmware!=0) FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose else //Non VGA case if (FB_Size<=2Gb) FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; else FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ /***********************************************************************************/ #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO … ATOM_FIRMWARE_VRAM_RESERVE_INFO; ATOM_VRAM_USAGE_BY_FIRMWARE; // change verion to 1.5, when allow driver to allocate the vram area for command table access. ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; /****************************************************************************/ // Structure used in GPIO_Pin_LUTTable /****************************************************************************/ ATOM_GPIO_PIN_ASSIGNMENT; //ucGPIO_ID pre-define id for multiple usage // GPIO use to control PCIE_VDDC in certain SLT board #define PCIE_VDDC_CONTROL_GPIO_PINID … //from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable #define PP_AC_DC_SWITCH_GPIO_PINID … //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable #define VDDC_VRHOT_GPIO_PINID … //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled #define VDDC_PCC_GPIO_PINID … // Only used on certain SLT/PA board to allow utility to cut Efuse. #define EFUSE_CUT_ENABLE_GPIO_PINID … // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= #define DRAM_SELF_REFRESH_GPIO_PINID … // Thermal interrupt output->system thermal chip GPIO pin #define THERMAL_INT_OUTPUT_GPIO_PINID … ATOM_GPIO_PIN_LUT; /****************************************************************************/ // Structure used in ComponentVideoInfoTable /****************************************************************************/ #define GPIO_PIN_ACTIVE_HIGH … #define MAX_SUPPORTED_CV_STANDARDS … // definitions for ATOM_D_INFO.ucSettings #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK … #define ATOM_GPIO_SETTINGS_RESERVED_MASK … #define ATOM_GPIO_SETTINGS_ACTIVE_MASK … ATOM_GPIO_INFO; // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) #define ATOM_CV_RESTRICT_FORMAT_SELECTION … // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i #define ATOM_GPIO_DEFAULT_MODE_EN … #define ATOM_GPIO_SETTING_PERMODE_MASK … // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode //Line 3 out put 5V. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A … #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B … #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT … //Line 3 out put 2.2V #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A … #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B … #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT … //Line 3 out put 0V #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A … #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B … #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT … #define ATOM_CV_LINE3_ASPECTRATIO_MASK … #define ATOM_CV_LINE3_ASPECTRATIO_EXIST … //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A … #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B … ATOM_COMPONENT_VIDEO_INFO; //ucTableFormatRevision=2 //ucTableContentRevision=1 ATOM_COMPONENT_VIDEO_INFO_V21; #define ATOM_COMPONENT_VIDEO_INFO_LAST … /****************************************************************************/ // Structure used in object_InfoTable /****************************************************************************/ ATOM_OBJECT_HEADER; ATOM_OBJECT_HEADER_V3; ATOM_DISPLAY_OBJECT_PATH; ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; ATOM_DISPLAY_OBJECT_PATH_TABLE; ATOM_OBJECT; ATOM_OBJECT_TABLE; ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; //Two definitions below are for OPM on MXM module designs #define EXT_HPDPIN_LUTINDEX_0 … #define EXT_HPDPIN_LUTINDEX_1 … #define EXT_HPDPIN_LUTINDEX_2 … #define EXT_HPDPIN_LUTINDEX_3 … #define EXT_HPDPIN_LUTINDEX_4 … #define EXT_HPDPIN_LUTINDEX_5 … #define EXT_HPDPIN_LUTINDEX_6 … #define EXT_HPDPIN_LUTINDEX_7 … #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES … #define EXT_AUXDDC_LUTINDEX_0 … #define EXT_AUXDDC_LUTINDEX_1 … #define EXT_AUXDDC_LUTINDEX_2 … #define EXT_AUXDDC_LUTINDEX_3 … #define EXT_AUXDDC_LUTINDEX_4 … #define EXT_AUXDDC_LUTINDEX_5 … #define EXT_AUXDDC_LUTINDEX_6 … #define EXT_AUXDDC_LUTINDEX_7 … #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES … //ucChannelMapping are defined as following //for DP connector, eDP, DP to VGA/LVDS //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 ATOM_DP_CONN_CHANNEL_MAPPING; //for DVI/HDMI, in dual link case, both links have to have same mapping. //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 ATOM_DVI_CONN_CHANNEL_MAPPING; EXT_DISPLAY_PATH; #define NUMBER_OF_UCHAR_FOR_GUID … #define MAX_NUMBER_OF_EXT_DISPLAY_PATH … //usCaps #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE … #define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN … #define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK … #define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 … #define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT … #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 … ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; //Related definitions, all records are different but they have a common header ATOM_COMMON_RECORD_HEADER; #define ATOM_I2C_RECORD_TYPE … #define ATOM_HPD_INT_RECORD_TYPE … #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE … #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE … #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE … #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE … #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE … #define ATOM_JTAG_RECORD_TYPE … #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE … #define ATOM_ENCODER_DVO_CF_RECORD_TYPE … #define ATOM_CONNECTOR_CF_RECORD_TYPE … #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE … #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE … #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE … #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE … #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE … #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE … #define ATOM_OBJECT_LINK_RECORD_TYPE … #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE … #define ATOM_ENCODER_CAP_RECORD_TYPE … #define ATOM_BRACKET_LAYOUT_RECORD_TYPE … #define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE … //Must be updated when new record type is added,equal to that record definition! #define ATOM_MAX_OBJECT_RECORD_NUMBER … ATOM_I2C_RECORD; ATOM_HPD_INT_RECORD; ATOM_OUTPUT_PROTECTION_RECORD; ATOM_CONNECTOR_DEVICE_TAG; ATOM_CONNECTOR_DEVICE_TAG_RECORD; ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; ATOM_ENCODER_FPGA_CONTROL_RECORD; ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; ATOM_JTAG_RECORD; //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually ATOM_GPIO_PIN_CONTROL_PAIR; ATOM_OBJECT_GPIO_CNTL_RECORD; //Definitions for GPIO pin state #define GPIO_PIN_TYPE_INPUT … #define GPIO_PIN_TYPE_OUTPUT … #define GPIO_PIN_TYPE_HW_CONTROL … //For GPIO_PIN_TYPE_OUTPUT the following is defined #define GPIO_PIN_OUTPUT_STATE_MASK … #define GPIO_PIN_OUTPUT_STATE_SHIFT … #define GPIO_PIN_STATE_ACTIVE_LOW … #define GPIO_PIN_STATE_ACTIVE_HIGH … // Indexes to GPIO array in GLSync record // GLSync record is for Frame Lock/Gen Lock feature. #define ATOM_GPIO_INDEX_GLSYNC_REFCLK … #define ATOM_GPIO_INDEX_GLSYNC_HSYNC … #define ATOM_GPIO_INDEX_GLSYNC_VSYNC … #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ … #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT … #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT … #define ATOM_GPIO_INDEX_GLSYNC_V_RESET … #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL … #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL … #define ATOM_GPIO_INDEX_GLSYNC_MAX … ATOM_ENCODER_DVO_CF_RECORD; // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap #define ATOM_ENCODER_CAP_RECORD_HBR2 … #define ATOM_ENCODER_CAP_RECORD_MST_EN … #define ATOM_ENCODER_CAP_RECORD_HBR2_EN … #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN … #define ATOM_ENCODER_CAP_RECORD_HBR3_EN … ATOM_ENCODER_CAP_RECORD; // Used after SI ATOM_ENCODER_CAP_RECORD_V2; // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA … #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB … ATOM_CONNECTOR_CF_RECORD; ATOM_CONNECTOR_HARDCODE_DTD_RECORD; ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; ATOM_ROUTER_DDC_PATH_SELECT_RECORD; ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; // define ucMuxType #define ATOM_ROUTER_MUX_PIN_STATE_MASK … #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT … ATOM_CONNECTOR_HPDPIN_LUT_RECORD; ATOM_CONNECTOR_AUXDDC_LUT_RECORD; ATOM_OBJECT_LINK_RECORD; ATOM_CONNECTOR_REMOTE_CAP_RECORD; ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD; ATOM_CONNECTOR_LAYOUT_INFO; // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size #define CONNECTOR_TYPE_DVI_D … #define CONNECTOR_TYPE_DVI_I … #define CONNECTOR_TYPE_VGA … #define CONNECTOR_TYPE_HDMI … #define CONNECTOR_TYPE_DISPLAY_PORT … #define CONNECTOR_TYPE_MINI_DISPLAY_PORT … ATOM_BRACKET_LAYOUT_RECORD; /****************************************************************************/ // Structure used in XXXX /****************************************************************************/ ATOM_VOLTAGE_INFO_HEADER; ATOM_VOLTAGE_INFO; ATOM_VOLTAGE_FORMULA; VOLTAGE_LUT_ENTRY; ATOM_VOLTAGE_FORMULA_V2; ATOM_VOLTAGE_CONTROL; // Define ucVoltageControlId #define VOLTAGE_CONTROLLED_BY_HW … #define VOLTAGE_CONTROLLED_BY_I2C_MASK … #define VOLTAGE_CONTROLLED_BY_GPIO … #define VOLTAGE_CONTROL_ID_LM64 … #define VOLTAGE_CONTROL_ID_DAC … #define VOLTAGE_CONTROL_ID_VT116xM … #define VOLTAGE_CONTROL_ID_DS4402 … #define VOLTAGE_CONTROL_ID_UP6266 … #define VOLTAGE_CONTROL_ID_SCORPIO … #define VOLTAGE_CONTROL_ID_VT1556M … #define VOLTAGE_CONTROL_ID_CHL822x … #define VOLTAGE_CONTROL_ID_VT1586M … #define VOLTAGE_CONTROL_ID_UP1637 … #define VOLTAGE_CONTROL_ID_CHL8214 … #define VOLTAGE_CONTROL_ID_UP1801 … #define VOLTAGE_CONTROL_ID_ST6788A … #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 … #define VOLTAGE_CONTROL_ID_AD527x … #define VOLTAGE_CONTROL_ID_NCP81022 … #define VOLTAGE_CONTROL_ID_LTC2635 … #define VOLTAGE_CONTROL_ID_NCP4208 … #define VOLTAGE_CONTROL_ID_IR35xx … #define VOLTAGE_CONTROL_ID_RT9403 … #define VOLTAGE_CONTROL_ID_GENERIC_I2C … ATOM_VOLTAGE_OBJECT; ATOM_VOLTAGE_OBJECT_V2; ATOM_VOLTAGE_OBJECT_INFO; ATOM_VOLTAGE_OBJECT_INFO_V2; ATOM_LEAKID_VOLTAGE; ATOM_VOLTAGE_OBJECT_HEADER_V3; // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode #define VOLTAGE_OBJ_GPIO_LUT … #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ … #define VOLTAGE_OBJ_PHASE_LUT … #define VOLTAGE_OBJ_SVID2 … #define VOLTAGE_OBJ_EVV … #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT … #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT … #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT … VOLTAGE_LUT_ENTRY_V2; LEAKAGE_VOLTAGE_LUT_ENTRY_V2; ATOM_I2C_VOLTAGE_OBJECT_V3; // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag #define VOLTAGE_DATA_ONE_BYTE … #define VOLTAGE_DATA_TWO_BYTE … ATOM_GPIO_VOLTAGE_OBJECT_V3; ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; ATOM_SVID2_VOLTAGE_OBJECT_V3; ATOM_MERGED_VOLTAGE_OBJECT_V3; ATOM_EVV_DPM_INFO; // ucVoltageMode = VOLTAGE_OBJ_EVV ATOM_EVV_VOLTAGE_OBJECT_V3; ATOM_VOLTAGE_OBJECT_V3; ATOM_VOLTAGE_OBJECT_INFO_V3_1; ATOM_ASIC_PROFILE_VOLTAGE; //ucProfileId #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE … #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE … #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE … ATOM_ASIC_PROFILING_INFO; ATOM_ASIC_PROFILING_INFO_V2_1; //Here is parameter to convert Efuse value to Measure value //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 EFUSE_LOGISTIC_FUNC_PARAM; //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) EFUSE_LINEAR_FUNC_PARAM; ATOM_ASIC_PROFILING_INFO_V3_1; ATOM_ASIC_PROFILING_INFO_V3_2; // for Tonga/Fiji speed EVV algorithm ATOM_ASIC_PROFILING_INFO_V3_3; // for Fiji speed EVV algorithm ATOM_ASIC_PROFILING_INFO_V3_4; // for Polaris10/Polaris11 speed EVV algorithm ATOM_ASIC_PROFILING_INFO_V3_5; /* for Polars10/11 AVFS parameters */ ATOM_ASIC_PROFILING_INFO_V3_6; ATOM_SCLK_FCW_RANGE_ENTRY_V1; // SMU_InfoTable for Polaris10/Polaris11 ATOM_SMU_INFO_V2_1; // GFX_InfoTable for Polaris10/Polaris11 ATOM_GFX_INFO_V2_1; ATOM_GFX_INFO_V2_3; ATOM_POWER_SOURCE_OBJECT; ATOM_POWER_SOURCE_INFO; //Define ucPwrSrcId #define POWERSOURCE_PCIE_ID1 … #define POWERSOURCE_6PIN_CONNECTOR_ID1 … #define POWERSOURCE_8PIN_CONNECTOR_ID1 … #define POWERSOURCE_6PIN_CONNECTOR_ID2 … #define POWERSOURCE_8PIN_CONNECTOR_ID2 … //define ucPwrSensorId #define POWER_SENSOR_ALWAYS … #define POWER_SENSOR_GPIO … #define POWER_SENSOR_I2C … ATOM_CLK_VOLT_CAPABILITY; ATOM_CLK_VOLT_CAPABILITY_V2; ATOM_AVAILABLE_SCLK_LIST; // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE … // this IntegrateSystemInfoTable is used for Liano/Ontario APU ATOM_INTEGRATED_SYSTEM_INFO_V6; // ulGPUCapInfo #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE … #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION … //ucLVDSMisc: #define SYS_INFO_LVDSMISC__888_FPDI_MODE … #define SYS_INFO_LVDSMISC__DL_CH_SWAP … #define SYS_INFO_LVDSMISC__888_BPC … #define SYS_INFO_LVDSMISC__OVERRIDE_EN … #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW … // new since Trinity #define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN … // not used any more #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW … #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW … /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V6 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement. ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_CRT2_SUPPORT 0x0010 ATOM_DEVICE_DFP1_SUPPORT 0x0008 ATOM_DEVICE_DFP6_SUPPORT 0x0040 ATOM_DEVICE_DFP2_SUPPORT 0x0080 ATOM_DEVICE_DFP3_SUPPORT 0x0200 ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 ulOtherDisplayMisc: Other display related flags, not defined yet. ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. =1: TMDS/HDMI Coherent Mode use signel PLL mode. bit[3]=0: Enable HW AUX mode detection logic =1: Disable HW AUX mode dettion logic ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but it's per platform and enabling VariBri under the driver environment from PP table is optional. ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State usNBP1Voltage: VID for voltage on NB P1 State usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set to indicate a range. SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) **********************************************************************************************************************/ // this Table is used for Liano/Ontario APU ATOM_FUSION_SYSTEM_INFO_V1; ATOM_TDP_CONFIG_BITS; ATOM_TDP_CONFIG; /********************************************************************************************************************** ATOM_FUSION_SYSTEM_INFO_V1 Description sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] **********************************************************************************************************************/ // this IntegrateSystemInfoTable is used for Trinity APU ATOM_INTEGRATED_SYSTEM_INFO_V1_7; // ulOtherDisplayMisc #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT … #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT … #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT … #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT … // ulGPUCapInfo #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE … #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE … #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT … #define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS … //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE … //ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML #define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE … /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement. ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_DFP1_SUPPORT 0x0008 ATOM_DEVICE_DFP6_SUPPORT 0x0040 ATOM_DEVICE_DFP2_SUPPORT 0x0080 ATOM_DEVICE_DFP3_SUPPORT 0x0200 ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS bit[3]=0: VBIOS fast boot is disable =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. =1: TMDS/HDMI Coherent Mode use signel PLL mode. bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) =1: DP mode use single PLL mode bit[3]=0: Enable AUX HW mode detection logic =1: Disable AUX HW mode detection logic ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but it's per platform and enabling VariBri under the driver environment from PP table is optional. ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State usNBP1Voltage: VID for voltage on NB P1 State usNBP2Voltage: VID for voltage on NB P2 State usNBP3Voltage: VID for voltage on NB P3 State usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set to indicate a range. SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. =0 means to use VBIOS default delay which is 125 ( 500ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. **********************************************************************************************************************/ // this IntegrateSystemInfoTable is used for Kaveri & Kabini APU ATOM_INTEGRATED_SYSTEM_INFO_V1_8; /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_DFP1_SUPPORT 0x0008 ATOM_DEVICE_DFP6_SUPPORT 0x0040 ATOM_DEVICE_DFP2_SUPPORT 0x0080 ATOM_DEVICE_DFP3_SUPPORT 0x0200 ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS bit[3]=0: VBIOS fast boot is disable =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) ulGPUCapInfo: bit[0~2]= Reserved bit[3]=0: Enable AUX HW mode detection logic =1: Disable AUX HW mode detection logic bit[4]=0: Disable DFS bypass feature =1: Enable DFS bypass feature usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but it's per platform and enabling VariBri under the driver environment from PP table is optional. ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. 1: DDR-PLL Power down feature enabled. Bit[3]=0: GNB DPM is disabled =1: GNB DPM is enabled ulCPUCapInfo: TBD usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set to indicate a range. SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. ucUMAChannelNumber: System memory channel numbers. strVBIOSMsg[40]: VBIOS boot up customized message string sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. =0 means to use VBIOS default delay which is 125 ( 500ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded sExtDispConnInfo: Display connector information table provided to VBIOS **********************************************************************************************************************/ ATOM_I2C_REG_INFO; // this IntegrateSystemInfoTable is used for Carrizo ATOM_INTEGRATED_SYSTEM_INFO_V1_9; // definition for ucEDPv1_4VSMode #define EDP_VS_LEGACY_MODE … #define EDP_VS_LOW_VDIFF_MODE … #define EDP_VS_HIGH_VDIFF_MODE … #define EDP_VS_STRETCH_MODE … #define EDP_VS_SINGLE_VDIFF_MODE … #define EDP_VS_VARIABLE_PREM_MODE … // ulGPUCapInfo #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT … #define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS … //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE … //ulGPUCapInfo[18]=1 indicate the IOMMU is not available #define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE … //ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened. #define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE … DPHY_TIMING_PARA; DPHY_ELEC_PARA; CAMERA_MODULE_INFO; FLASHLIGHT_INFO; CAMERA_DATA; ATOM_INTEGRATED_SYSTEM_INFO_V1_10; // this Table is used for Kaveri/Kabini APU ATOM_FUSION_SYSTEM_INFO_V2; ATOM_FUSION_SYSTEM_INFO_V3; #define FUSION_V3_OFFSET_FROM_TOP_OF_FB … /**************************************************************************/ // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design //Memory SS Info Table //Define Memory Clock SS chip ID #define ICS91719 … #define ICS91720 … //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol ATOM_I2C_DATA_RECORD; //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information ATOM_I2C_DEVICE_SETUP_INFO; //========================================================================================== ATOM_ASIC_MVDD_INFO; //========================================================================================== #define ATOM_MCLK_SS_INFO … //========================================================================================== /**************************************************************************/ ATOM_ASIC_SS_ASSIGNMENT; //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. //SS is not required or enabled if a match is not found. #define ASIC_INTERNAL_MEMORY_SS … #define ASIC_INTERNAL_ENGINE_SS … #define ASIC_INTERNAL_UVD_SS … #define ASIC_INTERNAL_SS_ON_TMDS … #define ASIC_INTERNAL_SS_ON_HDMI … #define ASIC_INTERNAL_SS_ON_LVDS … #define ASIC_INTERNAL_SS_ON_DP … #define ASIC_INTERNAL_SS_ON_DCPLL … #define ASIC_EXTERNAL_SS_ON_DP_CLOCK … #define ASIC_INTERNAL_VCE_SS … #define ASIC_INTERNAL_GPUPLL_SS … ATOM_ASIC_SS_ASSIGNMENT_V2; //ucSpreadSpectrumMode //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 //#define ATOM_INTERNAL_SS_MASK 0x00000000 //#define ATOM_EXTERNAL_SS_MASK 0x00000002 ATOM_ASIC_INTERNAL_SS_INFO; ATOM_ASIC_INTERNAL_SS_INFO_V2; ATOM_ASIC_SS_ASSIGNMENT_V3; //ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode #define SS_MODE_V3_CENTRE_SPREAD_MASK … #define SS_MODE_V3_EXTERNAL_SS_MASK … #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK … ATOM_ASIC_INTERNAL_SS_INFO_V3; //==============================Scratch Pad Definition Portion=============================== #define ATOM_DEVICE_CONNECT_INFO_DEF … #define ATOM_ROM_LOCATION_DEF … #define ATOM_TV_STANDARD_DEF … #define ATOM_ACTIVE_INFO_DEF … #define ATOM_LCD_INFO_DEF … #define ATOM_DOS_REQ_INFO_DEF … #define ATOM_ACC_CHANGE_INFO_DEF … #define ATOM_DOS_MODE_INFO_DEF … #define ATOM_I2C_CHANNEL_STATUS_DEF … #define ATOM_I2C_CHANNEL_STATUS1_DEF … #define ATOM_INTERNAL_TIMER_DEF … // BIOS_0_SCRATCH Definition #define ATOM_S0_CRT1_MONO … #define ATOM_S0_CRT1_COLOR … #define ATOM_S0_CRT1_MASK … #define ATOM_S0_TV1_COMPOSITE_A … #define ATOM_S0_TV1_SVIDEO_A … #define ATOM_S0_TV1_MASK_A … #define ATOM_S0_CV_A … #define ATOM_S0_CV_DIN_A … #define ATOM_S0_CV_MASK_A … #define ATOM_S0_CRT2_MONO … #define ATOM_S0_CRT2_COLOR … #define ATOM_S0_CRT2_MASK … #define ATOM_S0_TV1_COMPOSITE … #define ATOM_S0_TV1_SVIDEO … #define ATOM_S0_TV1_SCART … #define ATOM_S0_TV1_MASK … #define ATOM_S0_CV … #define ATOM_S0_CV_DIN … #define ATOM_S0_CV_MASK … #define ATOM_S0_DFP1 … #define ATOM_S0_DFP2 … #define ATOM_S0_LCD1 … #define ATOM_S0_LCD2 … #define ATOM_S0_DFP6 … #define ATOM_S0_DFP3 … #define ATOM_S0_DFP4 … #define ATOM_S0_DFP5 … #define ATOM_S0_DFP_MASK … #define ATOM_S0_FAD_REGISTER_BUG … // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx #define ATOM_S0_THERMAL_STATE_MASK … #define ATOM_S0_THERMAL_STATE_SHIFT … #define ATOM_S0_SYSTEM_POWER_STATE_MASK … #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT … #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC … #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC … #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC … #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC … //Byte aligned defintion for BIOS usage #define ATOM_S0_CRT1_MONOb0 … #define ATOM_S0_CRT1_COLORb0 … #define ATOM_S0_CRT1_MASKb0 … #define ATOM_S0_TV1_COMPOSITEb0 … #define ATOM_S0_TV1_SVIDEOb0 … #define ATOM_S0_TV1_MASKb0 … #define ATOM_S0_CVb0 … #define ATOM_S0_CV_DINb0 … #define ATOM_S0_CV_MASKb0 … #define ATOM_S0_CRT2_MONOb1 … #define ATOM_S0_CRT2_COLORb1 … #define ATOM_S0_CRT2_MASKb1 … #define ATOM_S0_TV1_COMPOSITEb1 … #define ATOM_S0_TV1_SVIDEOb1 … #define ATOM_S0_TV1_SCARTb1 … #define ATOM_S0_TV1_MASKb1 … #define ATOM_S0_CVb1 … #define ATOM_S0_CV_DINb1 … #define ATOM_S0_CV_MASKb1 … #define ATOM_S0_DFP1b2 … #define ATOM_S0_DFP2b2 … #define ATOM_S0_LCD1b2 … #define ATOM_S0_LCD2b2 … #define ATOM_S0_DFP6b2 … #define ATOM_S0_DFP3b2 … #define ATOM_S0_DFP4b2 … #define ATOM_S0_DFP5b2 … #define ATOM_S0_THERMAL_STATE_MASKb3 … #define ATOM_S0_THERMAL_STATE_SHIFTb3 … #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 … #define ATOM_S0_LCD1_SHIFT … // BIOS_1_SCRATCH Definition #define ATOM_S1_ROM_LOCATION_MASK … #define ATOM_S1_PCI_BUS_DEV_MASK … // BIOS_2_SCRATCH Definition #define ATOM_S2_TV1_STANDARD_MASK … #define ATOM_S2_CURRENT_BL_LEVEL_MASK … #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT … #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK … #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT … #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE … #define ATOM_S2_DEVICE_DPMS_STATE … #define ATOM_S2_VRI_BRIGHT_ENABLE … #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE … #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE … #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE … #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE … #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT … #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK … //Byte aligned defintion for BIOS usage #define ATOM_S2_TV1_STANDARD_MASKb0 … #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 … #define ATOM_S2_DEVICE_DPMS_STATEb2 … #define ATOM_S2_TMDS_COHERENT_MODEb3 … #define ATOM_S2_VRI_BRIGHT_ENABLEb3 … #define ATOM_S2_ROTATION_STATE_MASKb3 … // BIOS_3_SCRATCH Definition #define ATOM_S3_CRT1_ACTIVE … #define ATOM_S3_LCD1_ACTIVE … #define ATOM_S3_TV1_ACTIVE … #define ATOM_S3_DFP1_ACTIVE … #define ATOM_S3_CRT2_ACTIVE … #define ATOM_S3_LCD2_ACTIVE … #define ATOM_S3_DFP6_ACTIVE … #define ATOM_S3_DFP2_ACTIVE … #define ATOM_S3_CV_ACTIVE … #define ATOM_S3_DFP3_ACTIVE … #define ATOM_S3_DFP4_ACTIVE … #define ATOM_S3_DFP5_ACTIVE … #define ATOM_S3_DEVICE_ACTIVE_MASK … #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE … #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE … #define ATOM_S3_CRT1_CRTC_ACTIVE … #define ATOM_S3_LCD1_CRTC_ACTIVE … #define ATOM_S3_TV1_CRTC_ACTIVE … #define ATOM_S3_DFP1_CRTC_ACTIVE … #define ATOM_S3_CRT2_CRTC_ACTIVE … #define ATOM_S3_LCD2_CRTC_ACTIVE … #define ATOM_S3_DFP6_CRTC_ACTIVE … #define ATOM_S3_DFP2_CRTC_ACTIVE … #define ATOM_S3_CV_CRTC_ACTIVE … #define ATOM_S3_DFP3_CRTC_ACTIVE … #define ATOM_S3_DFP4_CRTC_ACTIVE … #define ATOM_S3_DFP5_CRTC_ACTIVE … #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK … #define ATOM_S3_ASIC_GUI_ENGINE_HUNG … //Below two definitions are not supported in pplib, but in the old powerplay in DAL #define ATOM_S3_ALLOW_FAST_PWR_SWITCH … #define ATOM_S3_RQST_GPU_USE_MIN_PWR … //Byte aligned defintion for BIOS usage #define ATOM_S3_CRT1_ACTIVEb0 … #define ATOM_S3_LCD1_ACTIVEb0 … #define ATOM_S3_TV1_ACTIVEb0 … #define ATOM_S3_DFP1_ACTIVEb0 … #define ATOM_S3_CRT2_ACTIVEb0 … #define ATOM_S3_LCD2_ACTIVEb0 … #define ATOM_S3_DFP6_ACTIVEb0 … #define ATOM_S3_DFP2_ACTIVEb0 … #define ATOM_S3_CV_ACTIVEb1 … #define ATOM_S3_DFP3_ACTIVEb1 … #define ATOM_S3_DFP4_ACTIVEb1 … #define ATOM_S3_DFP5_ACTIVEb1 … #define ATOM_S3_ACTIVE_CRTC1w0 … #define ATOM_S3_CRT1_CRTC_ACTIVEb2 … #define ATOM_S3_LCD1_CRTC_ACTIVEb2 … #define ATOM_S3_TV1_CRTC_ACTIVEb2 … #define ATOM_S3_DFP1_CRTC_ACTIVEb2 … #define ATOM_S3_CRT2_CRTC_ACTIVEb2 … #define ATOM_S3_LCD2_CRTC_ACTIVEb2 … #define ATOM_S3_DFP6_CRTC_ACTIVEb2 … #define ATOM_S3_DFP2_CRTC_ACTIVEb2 … #define ATOM_S3_CV_CRTC_ACTIVEb3 … #define ATOM_S3_DFP3_CRTC_ACTIVEb3 … #define ATOM_S3_DFP4_CRTC_ACTIVEb3 … #define ATOM_S3_DFP5_CRTC_ACTIVEb3 … #define ATOM_S3_ACTIVE_CRTC2w1 … // BIOS_4_SCRATCH Definition #define ATOM_S4_LCD1_PANEL_ID_MASK … #define ATOM_S4_LCD1_REFRESH_MASK … #define ATOM_S4_LCD1_REFRESH_SHIFT … //Byte aligned defintion for BIOS usage #define ATOM_S4_LCD1_PANEL_ID_MASKb0 … #define ATOM_S4_LCD1_REFRESH_MASKb1 … #define ATOM_S4_VRAM_INFO_MASKb2 … // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! #define ATOM_S5_DOS_REQ_CRT1b0 … #define ATOM_S5_DOS_REQ_LCD1b0 … #define ATOM_S5_DOS_REQ_TV1b0 … #define ATOM_S5_DOS_REQ_DFP1b0 … #define ATOM_S5_DOS_REQ_CRT2b0 … #define ATOM_S5_DOS_REQ_LCD2b0 … #define ATOM_S5_DOS_REQ_DFP6b0 … #define ATOM_S5_DOS_REQ_DFP2b0 … #define ATOM_S5_DOS_REQ_CVb1 … #define ATOM_S5_DOS_REQ_DFP3b1 … #define ATOM_S5_DOS_REQ_DFP4b1 … #define ATOM_S5_DOS_REQ_DFP5b1 … #define ATOM_S5_DOS_REQ_DEVICEw0 … #define ATOM_S5_DOS_REQ_CRT1 … #define ATOM_S5_DOS_REQ_LCD1 … #define ATOM_S5_DOS_REQ_TV1 … #define ATOM_S5_DOS_REQ_DFP1 … #define ATOM_S5_DOS_REQ_CRT2 … #define ATOM_S5_DOS_REQ_LCD2 … #define ATOM_S5_DOS_REQ_DFP6 … #define ATOM_S5_DOS_REQ_DFP2 … #define ATOM_S5_DOS_REQ_CV … #define ATOM_S5_DOS_REQ_DFP3 … #define ATOM_S5_DOS_REQ_DFP4 … #define ATOM_S5_DOS_REQ_DFP5 … #define ATOM_S5_DOS_FORCE_CRT1b2 … #define ATOM_S5_DOS_FORCE_TV1b2 … #define ATOM_S5_DOS_FORCE_CRT2b2 … #define ATOM_S5_DOS_FORCE_CVb3 … #define ATOM_S5_DOS_FORCE_DEVICEw1 … // BIOS_6_SCRATCH Definition #define ATOM_S6_DEVICE_CHANGE … #define ATOM_S6_SCALER_CHANGE … #define ATOM_S6_LID_CHANGE … #define ATOM_S6_DOCKING_CHANGE … #define ATOM_S6_ACC_MODE … #define ATOM_S6_EXT_DESKTOP_MODE … #define ATOM_S6_LID_STATE … #define ATOM_S6_DOCK_STATE … #define ATOM_S6_CRITICAL_STATE … #define ATOM_S6_HW_I2C_BUSY_STATE … #define ATOM_S6_THERMAL_STATE_CHANGE … #define ATOM_S6_INTERRUPT_SET_BY_BIOS … #define ATOM_S6_REQ_LCD_EXPANSION_FULL … #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO … #define ATOM_S6_DISPLAY_STATE_CHANGE … #define ATOM_S6_I2C_STATE_CHANGE … #define ATOM_S6_ACC_REQ_CRT1 … #define ATOM_S6_ACC_REQ_LCD1 … #define ATOM_S6_ACC_REQ_TV1 … #define ATOM_S6_ACC_REQ_DFP1 … #define ATOM_S6_ACC_REQ_CRT2 … #define ATOM_S6_ACC_REQ_LCD2 … #define ATOM_S6_ACC_REQ_DFP6 … #define ATOM_S6_ACC_REQ_DFP2 … #define ATOM_S6_ACC_REQ_CV … #define ATOM_S6_ACC_REQ_DFP3 … #define ATOM_S6_ACC_REQ_DFP4 … #define ATOM_S6_ACC_REQ_DFP5 … #define ATOM_S6_ACC_REQ_MASK … #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE … #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH … #define ATOM_S6_VRI_BRIGHTNESS_CHANGE … #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK … //Byte aligned defintion for BIOS usage #define ATOM_S6_DEVICE_CHANGEb0 … #define ATOM_S6_SCALER_CHANGEb0 … #define ATOM_S6_LID_CHANGEb0 … #define ATOM_S6_DOCKING_CHANGEb0 … #define ATOM_S6_ACC_MODEb0 … #define ATOM_S6_EXT_DESKTOP_MODEb0 … #define ATOM_S6_LID_STATEb0 … #define ATOM_S6_DOCK_STATEb0 … #define ATOM_S6_CRITICAL_STATEb1 … #define ATOM_S6_HW_I2C_BUSY_STATEb1 … #define ATOM_S6_THERMAL_STATE_CHANGEb1 … #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 … #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 … #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 … #define ATOM_S6_ACC_REQ_CRT1b2 … #define ATOM_S6_ACC_REQ_LCD1b2 … #define ATOM_S6_ACC_REQ_TV1b2 … #define ATOM_S6_ACC_REQ_DFP1b2 … #define ATOM_S6_ACC_REQ_CRT2b2 … #define ATOM_S6_ACC_REQ_LCD2b2 … #define ATOM_S6_ACC_REQ_DFP6b2 … #define ATOM_S6_ACC_REQ_DFP2b2 … #define ATOM_S6_ACC_REQ_CVb3 … #define ATOM_S6_ACC_REQ_DFP3b3 … #define ATOM_S6_ACC_REQ_DFP4b3 … #define ATOM_S6_ACC_REQ_DFP5b3 … #define ATOM_S6_ACC_REQ_DEVICEw1 … #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 … #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 … #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 … #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 … #define ATOM_S6_DEVICE_CHANGE_SHIFT … #define ATOM_S6_SCALER_CHANGE_SHIFT … #define ATOM_S6_LID_CHANGE_SHIFT … #define ATOM_S6_DOCKING_CHANGE_SHIFT … #define ATOM_S6_ACC_MODE_SHIFT … #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT … #define ATOM_S6_LID_STATE_SHIFT … #define ATOM_S6_DOCK_STATE_SHIFT … #define ATOM_S6_CRITICAL_STATE_SHIFT … #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT … #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT … #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT … #define ATOM_S6_REQ_SCALER_SHIFT … #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT … #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT … #define ATOM_S6_I2C_STATE_CHANGE_SHIFT … #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT … #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT … #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT … #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT … // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! #define ATOM_S7_DOS_MODE_TYPEb0 … #define ATOM_S7_DOS_MODE_VGAb0 … #define ATOM_S7_DOS_MODE_VESAb0 … #define ATOM_S7_DOS_MODE_EXTb0 … #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 … #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 … #define ATOM_S7_DOS_8BIT_DAC_ENb1 … #define ATOM_S7_ASIC_INIT_COMPLETEb1 … #define ATOM_S7_ASIC_INIT_COMPLETE_MASK … #define ATOM_S7_DOS_MODE_NUMBERw1 … #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT … // BIOS_8_SCRATCH Definition #define ATOM_S8_I2C_CHANNEL_BUSY_MASK … #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK … #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT … #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT … // BIOS_9_SCRATCH Definition #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK … #endif #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK … #endif #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT … #endif #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT … #endif #define ATOM_FLAG_SET … #define ATOM_FLAG_CLEAR … #define CLEAR_ATOM_S6_ACC_MODE … #define SET_ATOM_S6_DEVICE_CHANGE … #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE … #define SET_ATOM_S6_SCALER_CHANGE … #define SET_ATOM_S6_LID_CHANGE … #define SET_ATOM_S6_LID_STATE … #define CLEAR_ATOM_S6_LID_STATE … #define SET_ATOM_S6_DOCK_CHANGE … #define SET_ATOM_S6_DOCK_STATE … #define CLEAR_ATOM_S6_DOCK_STATE … #define SET_ATOM_S6_THERMAL_STATE_CHANGE … #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE … #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS … #define SET_ATOM_S6_CRITICAL_STATE … #define CLEAR_ATOM_S6_CRITICAL_STATE … #define SET_ATOM_S6_REQ_SCALER … #define CLEAR_ATOM_S6_REQ_SCALER … #define SET_ATOM_S6_REQ_SCALER_ARATIO … #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO … #define SET_ATOM_S6_I2C_STATE_CHANGE … #define SET_ATOM_S6_DISPLAY_STATE_CHANGE … #define SET_ATOM_S6_DEVICE_RECONFIG … #define CLEAR_ATOM_S0_LCD1 … #define SET_ATOM_S7_DOS_8BIT_DAC_EN … #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN … /****************************************************************************/ //Portion II: Definitinos only used in Driver /****************************************************************************/ // Macros used by driver #ifdef __cplusplus #define GetIndexIntoMasterTable … #define GET_COMMAND_TABLE_COMMANDSET_REVISION … #define GET_COMMAND_TABLE_PARAMETER_REVISION … #else // not __cplusplus #define GetIndexIntoMasterTable(MasterOrData, FieldName) … #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) … #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) … #endif // __cplusplus #define GET_DATA_TABLE_MAJOR_REVISION … #define GET_DATA_TABLE_MINOR_REVISION … /****************************************************************************/ //Portion III: Definitinos only used in VBIOS /****************************************************************************/ #define ATOM_DAC_SRC … #define ATOM_SRC_DAC1 … #define ATOM_SRC_DAC2 … MEMORY_PLLINIT_PARAMETERS; #define MEMORY_PLLINIT_PS_ALLOCATION … #define GPIO_PIN_WRITE … #define GPIO_PIN_READ … GPIO_PIN_CONTROL_PARAMETERS; ENABLE_SCALER_PARAMETERS; #define ENABLE_SCALER_PS_ALLOCATION … //ucEnable: #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION … #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION … #define SCALER_ENABLE_2TAP_ALPHA_MODE … #define SCALER_ENABLE_MULTITAP_MODE … ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; ENABLE_GRAPH_SURFACE_PARAMETERS; ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; // ucEnable #define ATOM_GRAPH_CONTROL_SET_PITCH … #define ATOM_GRAPH_CONTROL_SET_DISP_START … ENABLE_GRAPH_SURFACE_PS_ALLOCATION; MEMORY_CLEAN_UP_PARAMETERS; #define MEMORY_CLEAN_UP_PS_ALLOCATION … GET_DISPLAY_SURFACE_SIZE_PARAMETERS; GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; PALETTE_DATA_CONTROL_PARAMETERS_V3; // ucAction: #define PALETTE_DATA_AUTO_FILL … #define PALETTE_DATA_READ … #define PALETTE_DATA_WRITE … INTERRUPT_SERVICE_PARAMETER_V2; // ucInterruptId #define HDP1_INTERRUPT_ID … #define HDP2_INTERRUPT_ID … #define HDP3_INTERRUPT_ID … #define HDP4_INTERRUPT_ID … #define HDP5_INTERRUPT_ID … #define HDP6_INTERRUPT_ID … #define SW_INTERRUPT_ID … // ucAction #define INTERRUPT_SERVICE_GEN_SW_INT … #define INTERRUPT_SERVICE_GET_STATUS … // ucStatus #define INTERRUPT_STATUS__INT_TRIGGER … #define INTERRUPT_STATUS__HPD_HIGH … EFUSE_INPUT_PARAMETER; // ReadEfuseValue command table input/output parameter READ_EFUSE_VALUE_PARAMETER; INDIRECT_IO_ACCESS; #define INDIRECT_READ … #define INDIRECT_WRITE … #define INDIRECT_IO_MM … #define INDIRECT_IO_PLL … #define INDIRECT_IO_MC … #define INDIRECT_IO_PCIE … #define INDIRECT_IO_PCIEP … #define INDIRECT_IO_NBMISC … #define INDIRECT_IO_SMU … #define INDIRECT_IO_PLL_READ … #define INDIRECT_IO_PLL_WRITE … #define INDIRECT_IO_MC_READ … #define INDIRECT_IO_MC_WRITE … #define INDIRECT_IO_PCIE_READ … #define INDIRECT_IO_PCIE_WRITE … #define INDIRECT_IO_PCIEP_READ … #define INDIRECT_IO_PCIEP_WRITE … #define INDIRECT_IO_NBMISC_READ … #define INDIRECT_IO_NBMISC_WRITE … #define INDIRECT_IO_SMU_READ … #define INDIRECT_IO_SMU_WRITE … ATOM_OEM_INFO; ATOM_TV_MODE; ATOM_BIOS_INT_TVSTD_MODE; ATOM_TV_MODE_SCALER_PTR; ATOM_STANDARD_VESA_TIMING; ATOM_STD_FORMAT; ATOM_VESA_TO_EXTENDED_MODE; ATOM_VESA_TO_INTENAL_MODE_LUT; /*************** ATOM Memory Related Data Structure ***********************/ ATOM_MEMORY_VENDOR_BLOCK; ATOM_MEMORY_SETTING_ID_CONFIG; ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; ATOM_MEMORY_SETTING_DATA_BLOCK; ATOM_INIT_REG_INDEX_FORMAT; ATOM_INIT_REG_BLOCK; #define END_OF_REG_INDEX_BLOCK … #define END_OF_REG_DATA_BLOCK … #define ATOM_INIT_REG_MASK_FLAG … #define CLOCK_RANGE_HIGHEST … #define VALUE_DWORD … #define VALUE_SAME_AS_ABOVE … #define VALUE_MASK_DWORD … #define INDEX_ACCESS_RANGE_BEGIN … #define INDEX_ACCESS_RANGE_END … #define VALUE_INDEX_ACCESS_SINGLE … //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code #define ACCESS_PLACEHOLDER … ATOM_MC_INIT_PARAM_TABLE; ATOM_REG_INIT_SETTING; ATOM_MC_INIT_PARAM_TABLE_V2_1; #define _4Mx16 … #define _4Mx32 … #define _8Mx16 … #define _8Mx32 … #define _8Mx128 … #define _16Mx16 … #define _16Mx32 … #define _16Mx128 … #define _32Mx16 … #define _32Mx32 … #define _32Mx128 … #define _64Mx8 … #define _64Mx16 … #define _64Mx32 … #define _64Mx128 … #define _128Mx8 … #define _128Mx16 … #define _128Mx32 … #define _256Mx8 … #define _256Mx16 … #define _256Mx32 … #define _512Mx8 … #define _512Mx16 … #define SAMSUNG … #define INFINEON … #define ELPIDA … #define ETRON … #define NANYA … #define HYNIX … #define MOSEL … #define WINBOND … #define ESMT … #define MICRON … #define QIMONDA … #define PROMOS … #define KRETON … #define ELIXIR … #define MEZZA … /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// #define UCODE_ROM_START_ADDRESS … #define UCODE_SIGNATURE … //uCode block header for reference MCuCodeHeader; ////////////////////////////////////////////////////////////////////////////////// #define ATOM_MAX_NUMBER_OF_VRAM_MODULE … #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK … ATOM_VRAM_MODULE_V1; ATOM_VRAM_MODULE_V2; ATOM_MEMORY_TIMING_FORMAT; ATOM_MEMORY_TIMING_FORMAT_V1; ATOM_MEMORY_TIMING_FORMAT_V2; ATOM_MEMORY_FORMAT; ATOM_VRAM_MODULE_V3; //ATOM_VRAM_MODULE_V3.ucNPL_RT #define NPL_RT_MASK … #define BATTERY_ODT_MASK … #define ATOM_VRAM_MODULE … ATOM_VRAM_MODULE_V4; #define VRAM_MODULE_V4_MISC_RANK_MASK … #define VRAM_MODULE_V4_MISC_DUAL_RANK … #define VRAM_MODULE_V4_MISC_BL_MASK … #define VRAM_MODULE_V4_MISC_BL8 … #define VRAM_MODULE_V4_MISC_DUAL_CS … ATOM_VRAM_MODULE_V5; ATOM_VRAM_MODULE_V6; ATOM_VRAM_MODULE_V7; ATOM_VRAM_MODULE_V8; ATOM_VRAM_INFO_V2; ATOM_VRAM_INFO_V3; #define ATOM_VRAM_INFO_LAST … ATOM_VRAM_INFO_V4; ATOM_VRAM_INFO_HEADER_V2_1; ATOM_VRAM_INFO_HEADER_V2_2; ATOM_DRAM_DATA_REMAP; ATOM_VRAM_GPIO_DETECTION_INFO; ATOM_MEMORY_TRAINING_INFO; ATOM_MEMORY_TRAINING_INFO_V3_1; SW_I2C_CNTL_DATA_PARAMETERS; #define SW_I2C_CNTL_DATA_PS_ALLOCATION … SW_I2C_IO_DATA_PARAMETERS; #define SW_I2C_IO_DATA_PS_ALLOCATION … /****************************SW I2C CNTL DEFINITIONS**********************/ #define SW_I2C_IO_RESET … #define SW_I2C_IO_GET … #define SW_I2C_IO_DRIVE … #define SW_I2C_IO_SET … #define SW_I2C_IO_START … #define SW_I2C_IO_CLOCK … #define SW_I2C_IO_DATA … #define SW_I2C_IO_ZERO … #define SW_I2C_IO_ONE … #define SW_I2C_CNTL_READ … #define SW_I2C_CNTL_WRITE … #define SW_I2C_CNTL_START … #define SW_I2C_CNTL_STOP … #define SW_I2C_CNTL_OPEN … #define SW_I2C_CNTL_CLOSE … #define SW_I2C_CNTL_WRITE1BIT … //==============================VESA definition Portion=============================== #define VESA_OEM_PRODUCT_REV … #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT … #define VESA_MODE_WIN_ATTRIBUTE … #define VESA_WIN_SIZE … PTR_32_BIT_STRUCTURE; PTR_32_BIT_UNION; VBE_1_2_INFO_BLOCK_UPDATABLE; VBE_2_0_INFO_BLOCK_UPDATABLE; VBE_VERSION_UNION; VBE_INFO_BLOCK; VBE_FP_INFO; VESA_MODE_INFO_BLOCK; // BIOS function CALLS #define ATOM_BIOS_EXTENDED_FUNCTION_CODE … #define ATOM_BIOS_FUNCTION_COP_MODE … #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 … #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 … #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 … #define ATOM_BIOS_FUNCTION_GET_DDC … #define ATOM_BIOS_FUNCTION_ASIC_DSTATE … #define ATOM_BIOS_FUNCTION_DEBUG_PLAY … #define ATOM_BIOS_FUNCTION_STV_STD … #define ATOM_BIOS_FUNCTION_DEVICE_DET … #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH … #define ATOM_BIOS_FUNCTION_PANEL_CONTROL … #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET … #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH … #define ATOM_BIOS_FUNCTION_HW_ICON … #define ATOM_BIOS_FUNCTION_SET_CMOS … #define SUB_FUNCTION_UPDATE_DISPLAY_INFO … #define SUB_FUNCTION_UPDATE_EXPANSION_INFO … #define ATOM_BIOS_FUNCTION_DISPLAY_INFO … #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF … #define ATOM_BIOS_FUNCTION_VIDEO_STATE … #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE … #define ATOM_SUB_FUNCTION_GET_LIDSTATE … #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE … #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE … #define ATOM_SUB_FUNCTION_SET_LIDSTATE … #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE … #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT … #define ATOM_BIOS_FUNCTION_VESA_DPMS … #define ATOM_SUB_FUNCTION_SET_DPMS … #define ATOM_SUB_FUNCTION_GET_DPMS … #define ATOM_PARAMETER_VESA_DPMS_ON … #define ATOM_PARAMETER_VESA_DPMS_STANDBY … #define ATOM_PARAMETER_VESA_DPMS_SUSPEND … #define ATOM_PARAMETER_VESA_DPMS_OFF … #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON … #define ATOM_BIOS_RETURN_CODE_MASK … #define ATOM_BIOS_REG_HIGH_MASK … #define ATOM_BIOS_REG_LOW_MASK … // structure used for VBIOS only //DispOutInfoTable ASIC_TRANSMITTER_INFO; #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE … #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE … #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK … #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A … #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B … #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C … #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D … #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E … #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F … ASIC_ENCODER_INFO; ATOM_DISP_OUT_INFO; ATOM_DISP_OUT_INFO_V2; ATOM_DISP_CLOCK_ID; // ucPpllAttribute #define CLOCK_SOURCE_SHAREABLE … #define CLOCK_SOURCE_DP_MODE … #define CLOCK_SOURCE_NONE_DP_MODE … //DispOutInfoTable ASIC_TRANSMITTER_INFO_V2; ATOM_DISP_OUT_INFO_V3; //ucDispCaps #define DISPLAY_CAPS__DP_PCLK_FROM_PPLL … #define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED … CORE_REF_CLK_SOURCE; // DispDevicePriorityInfo ATOM_DISPLAY_DEVICE_PRIORITY_INFO; //ProcessAuxChannelTransactionTable PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; //ProcessAuxChannelTransactionTable PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION … //GetSinkType DP_ENCODER_SERVICE_PARAMETERS; // ucAction #define ATOM_DP_ACTION_GET_SINK_TYPE … #define DP_ENCODER_SERVICE_PS_ALLOCATION … DP_ENCODER_SERVICE_PARAMETERS_V2; DP_ENCODER_SERVICE_PS_ALLOCATION_V2; // ucAction #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE … #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION … // DP_TRAINING_TABLE #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR … #define DPCD_SET_SS_CNTL_TBL_ADDR … #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR … #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR … #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR … #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR … #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR … #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR … #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR … #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR … #define DP_I2C_AUX_DDC_READ_TBL_ADDR … #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR … #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR … PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION … //ucFlag #define HW_I2C_WRITE … #define HW_I2C_READ … #define I2C_2BYTE_ADDR … /****************************************************************************/ // Structures used by HW_Misc_OperationTable /****************************************************************************/ ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; // Actions code #define ATOM_GET_SDI_SUPPORT … // Return code #define ATOM_UNKNOWN_CMD … #define ATOM_FEATURE_NOT_SUPPORTED … #define ATOM_FEATURE_SUPPORTED … ATOM_HW_MISC_OPERATION_PS_ALLOCATION; /****************************************************************************/ SET_HWBLOCK_INSTANCE_PARAMETER_V2; #define HWBLKINST_INSTANCE_MASK … #define HWBLKINST_HWBLK_MASK … #define HWBLKINST_HWBLK_SHIFT … //ucHWBlock #define SELECT_DISP_ENGINE … #define SELECT_DISP_PLL … #define SELECT_DCIO_UNIPHY_LINK0 … #define SELECT_DCIO_UNIPHY_LINK1 … #define SELECT_DCIO_IMPCAL … #define SELECT_DCIO_DIG … #define SELECT_CRTC_PIXEL_RATE … #define SELECT_VGA_BLK … // DIGTransmitterInfoTable structure used to program UNIPHY settings DIG_TRANSMITTER_INFO_HEADER_V3_1; DIG_TRANSMITTER_INFO_HEADER_V3_2; DIG_TRANSMITTER_INFO_HEADER_V3_3; CLOCK_CONDITION_REGESTER_INFO; CLOCK_CONDITION_SETTING_ENTRY; CLOCK_CONDITION_SETTING_INFO; PHY_CONDITION_REG_VAL; PHY_CONDITION_REG_VAL_V2; PHY_CONDITION_REG_INFO; PHY_CONDITION_REG_INFO_V2; PHY_ANALOG_SETTING_INFO; PHY_ANALOG_SETTING_INFO_V2; GFX_HAVESTING_PARAMETERS; //ucGfxBlkId #define GFX_HARVESTING_CU_ID … #define GFX_HARVESTING_RB_ID … #define GFX_HARVESTING_PRIM_ID … VBIOS_ROM_HEADER; /****************************************************************************/ //Portion VI: Definitinos for vbios MC scratch registers that driver used /****************************************************************************/ #define MC_MISC0__MEMORY_TYPE_MASK … #define MC_MISC0__MEMORY_TYPE__GDDR1 … #define MC_MISC0__MEMORY_TYPE__DDR2 … #define MC_MISC0__MEMORY_TYPE__GDDR3 … #define MC_MISC0__MEMORY_TYPE__GDDR4 … #define MC_MISC0__MEMORY_TYPE__GDDR5 … #define MC_MISC0__MEMORY_TYPE__HBM … #define MC_MISC0__MEMORY_TYPE__DDR3 … #define ATOM_MEM_TYPE_DDR_STRING … #define ATOM_MEM_TYPE_DDR2_STRING … #define ATOM_MEM_TYPE_GDDR3_STRING … #define ATOM_MEM_TYPE_GDDR4_STRING … #define ATOM_MEM_TYPE_GDDR5_STRING … #define ATOM_MEM_TYPE_HBM_STRING … #define ATOM_MEM_TYPE_DDR3_STRING … /****************************************************************************/ //Portion VII: Definitinos being oboselete /****************************************************************************/ //========================================================================================== //Remove the definitions below when driver is ready! ATOM_DAC_INFO; COMPASSIONATE_DATA; /****************************Supported Device Info Table Definitions**********************/ // ucConnectInfo: // [7:4] - connector type // = 1 - VGA connector // = 2 - DVI-I // = 3 - DVI-D // = 4 - DVI-A // = 5 - SVIDEO // = 6 - COMPOSITE // = 7 - LVDS // = 8 - DIGITAL LINK // = 9 - SCART // = 0xA - HDMI_type A // = 0xB - HDMI_type B // = 0xE - Special case1 (DVI+DIN) // Others=TBD // [3:0] - DAC Associated // = 0 - no DAC // = 1 - DACA // = 2 - DACB // = 3 - External DAC // Others=TBD // ATOM_CONNECTOR_INFO; ATOM_CONNECTOR_INFO_ACCESS; ATOM_CONNECTOR_INFO_I2C; ATOM_SUPPORTED_DEVICES_INFO; #define NO_INT_SRC_MAPPED … ATOM_CONNECTOR_INC_SRC_BITMAP; ATOM_SUPPORTED_DEVICES_INFO_2; ATOM_SUPPORTED_DEVICES_INFO_2d1; #define ATOM_SUPPORTED_DEVICES_INFO_LAST … ATOM_MISC_CONTROL_INFO; #define ATOM_MAX_MISC_INFO … ATOM_TMDS_INFO; ATOM_ENCODER_ANALOG_ATTRIBUTE; ATOM_ENCODER_DIGITAL_ATTRIBUTE; ATOM_ENCODER_ATTRIBUTE; DVO_ENCODER_CONTROL_PARAMETERS; DVO_ENCODER_CONTROL_PS_ALLOCATION; #define ATOM_XTMDS_ASIC_SI164_ID … #define ATOM_XTMDS_ASIC_SI178_ID … #define ATOM_XTMDS_ASIC_TFP513_ID … #define ATOM_XTMDS_SUPPORTED_SINGLELINK … #define ATOM_XTMDS_SUPPORTED_DUALLINK … #define ATOM_XTMDS_MVPU_FPGA … ATOM_XTMDS_INFO; DFP_DPMS_STATUS_CHANGE_PARAMETERS; /****************************Legacy Power Play Table Definitions **********************/ //Definitions for ulPowerPlayMiscInfo #define ATOM_PM_MISCINFO_SPLIT_CLOCK … #define ATOM_PM_MISCINFO_USING_MCLK_SRC … #define ATOM_PM_MISCINFO_USING_SCLK_SRC … #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT … #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH … #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN … #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN … #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN … #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE … #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN … #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN … #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN … #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN … #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE … #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE … #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE … #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE … #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE … #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE … #define ATOM_PM_MISCINFO_POWER_SAVING_MODE … #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE … #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK … #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT … #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE … #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 … #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 … #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN … #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN … #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN … #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK … #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT … #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS … #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE … #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT … #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN … #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO … #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE … #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN … #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE … //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC … #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN … #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE … //ucTableFormatRevision=1 //ucTableContentRevision=1 ATOM_POWERMODE_INFO; //ucTableFormatRevision=2 //ucTableContentRevision=1 ATOM_POWERMODE_INFO_V2; //ucTableFormatRevision=2 //ucTableContentRevision=2 ATOM_POWERMODE_INFO_V3; #define ATOM_MAX_NUMBEROF_POWER_BLOCK … #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN … #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE … #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 … #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 … #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 … #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 … #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 … #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 … #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 … ATOM_POWERPLAY_INFO; ATOM_POWERPLAY_INFO_V2; ATOM_POWERPLAY_INFO_V3; /**************************************************************************/ // Following definitions are for compatiblity issue in different SW components. #define ATOM_MASTER_DATA_TABLE_REVISION … #define Object_Info … #define AdjustARB_SEQ … #define VRAM_GPIO_DetectionInfo … #define ASIC_VDDCI_Info … #define ASIC_MVDDQ_Info … #define SS_Info … #define ASIC_MVDDC_Info … #define DispDevicePriorityInfo … #define DispOutInfo … #define ATOM_ENCODER_OBJECT_TABLE … #define ATOM_CONNECTOR_OBJECT_TABLE … //New device naming, remove them when both DAL/VBIOS is ready #define DFP2I_OUTPUT_CONTROL_PARAMETERS … #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION … #define DFP1X_OUTPUT_CONTROL_PARAMETERS … #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION … #define DFP1I_OUTPUT_CONTROL_PARAMETERS … #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION … #define ATOM_DEVICE_DFP1I_SUPPORT … #define ATOM_DEVICE_DFP1X_SUPPORT … #define ATOM_DEVICE_DFP1I_INDEX … #define ATOM_DEVICE_DFP1X_INDEX … #define ATOM_DEVICE_DFP2I_INDEX … #define ATOM_DEVICE_DFP2I_SUPPORT … #define ATOM_S0_DFP1I … #define ATOM_S0_DFP1X … #define ATOM_S0_DFP2I … #define ATOM_S0_DFP2Ib2 … #define ATOM_S2_DFP1I_DPMS_STATE … #define ATOM_S2_DFP1X_DPMS_STATE … #define ATOM_S2_DFP2I_DPMS_STATE … #define ATOM_S2_DFP2I_DPMS_STATEb3 … #define ATOM_S3_DFP2I_ACTIVEb1 … #define ATOM_S3_DFP1I_ACTIVE … #define ATOM_S3_DFP1X_ACTIVE … #define ATOM_S3_DFP2I_ACTIVE … #define ATOM_S3_DFP1I_CRTC_ACTIVE … #define ATOM_S3_DFP1X_CRTC_ACTIVE … #define ATOM_S3_DFP2I_CRTC_ACTIVE … #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 … #define ATOM_S5_DOS_REQ_DFP2Ib1 … #define ATOM_S5_DOS_REQ_DFP2I … #define ATOM_S6_ACC_REQ_DFP1I … #define ATOM_S6_ACC_REQ_DFP1X … #define ATOM_S6_ACC_REQ_DFP2Ib3 … #define ATOM_S6_ACC_REQ_DFP2I … #define TMDS1XEncoderControl … #define DFP1XOutputControl … #define ExternalDFPOutputControl … #define EnableExternalTMDS_Encoder … #define DFP1IOutputControl … #define DFP2IOutputControl … #define DAC1_ENCODER_CONTROL_PARAMETERS … #define DAC1_ENCODER_CONTROL_PS_ALLOCATION … #define DAC2_ENCODER_CONTROL_PARAMETERS … #define DAC2_ENCODER_CONTROL_PS_ALLOCATION … #define ucDac1Standard … #define ucDac2Standard … #define TMDS1EncoderControl … #define TMDS2EncoderControl … #define DFP1OutputControl … #define DFP2OutputControl … #define CRT1OutputControl … #define CRT2OutputControl … //These two lines will be removed for sure in a few days, will follow up with Michael V. #define EnableLVDS_SS … #define ENABLE_LVDS_SS_PARAMETERS_V3 … #define ATOM_S2_CRT1_DPMS_STATE … #define ATOM_S2_LCD1_DPMS_STATE … #define ATOM_S2_TV1_DPMS_STATE … #define ATOM_S2_DFP1_DPMS_STATE … #define ATOM_S2_CRT2_DPMS_STATE … #define ATOM_S6_ACC_REQ_TV2 … #define ATOM_DEVICE_TV2_INDEX … #define ATOM_DEVICE_TV2_SUPPORT … #define ATOM_S0_TV2 … #define ATOM_S3_TV2_ACTIVE … #define ATOM_S3_TV2_CRTC_ACTIVE … /*********************************************************************************/ #pragma pack() // BIOS data must use byte alignment #pragma pack(1) ATOM_HOLE_INFO; ATOM_SERVICE_DESCRIPTION; ATOM_SERVICE_INFO; #pragma pack() // BIOS data must use byte alignment // // AMD ACPI Table // #pragma pack(1) AMD_ACPI_DESCRIPTION_HEADER; /* //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h typedef struct { UINT32 Signature; //0x0 UINT32 Length; //0x4 UINT8 Revision; //0x8 UINT8 Checksum; //0x9 UINT8 OemId[6]; //0xA UINT64 OemTableId; //0x10 UINT32 OemRevision; //0x18 UINT32 CreatorId; //0x1C UINT32 CreatorRevision; //0x20 }EFI_ACPI_DESCRIPTION_HEADER; */ UEFI_ACPI_VFCT; VFCT_IMAGE_HEADER; GOP_VBIOS_CONTENT; GOP_LIB1_CONTENT; #pragma pack() #endif /* _ATOMBIOS_H */ #include "pptable.h"
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