/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _PSP_TEE_GFX_IF_H_ #define _PSP_TEE_GFX_IF_H_ #define PSP_GFX_CMD_BUF_VERSION … #define GFX_CMD_STATUS_MASK … #define GFX_CMD_ID_MASK … #define GFX_CMD_RESERVED_MASK … #define GFX_CMD_RESPONSE_MASK … /* USBC PD FW version retrieval command */ #define C2PMSG_CMD_GFX_USB_PD_FW_VER … /* TEE Gfx Command IDs for the register interface. * Command ID must be between 0x00010000 and 0x000F0000. */ enum psp_gfx_crtl_cmd_id { … }; /*----------------------------------------------------------------------------- NOTE: All physical addresses used in this interface are actually GPU Virtual Addresses. */ /* Control registers of the TEE Gfx interface. These are located in * SRBM-to-PSP mailbox registers (total 8 registers). */ struct psp_gfx_ctrl { … }; /* Response flag is set in the command when command is completed by PSP. * Used in the GFX_CTRL.CmdResp. * When PSP GFX I/F is initialized, the flag is set. */ #define GFX_FLAG_RESPONSE … /* TEE Gfx Command IDs for the ring buffer interface. */ enum psp_gfx_cmd_id { … }; /* PSP boot config sub-commands */ enum psp_gfx_boot_config_cmd { … }; /* PSP boot config bitmask values */ enum psp_gfx_boot_config { … }; /* Command to load Trusted Application binary into PSP OS. */ struct psp_gfx_cmd_load_ta { … }; /* Command to Unload Trusted Application binary from PSP OS. */ struct psp_gfx_cmd_unload_ta { … }; /* Shared buffers for InvokeCommand. */ struct psp_gfx_buf_desc { … }; /* Max number of descriptors for one shared buffer (in how many different * physical locations one shared buffer can be stored). If buffer is too much * fragmented, error will be returned. */ #define GFX_BUF_MAX_DESC … struct psp_gfx_buf_list { … }; /* Command to execute InvokeCommand entry point of the TA. */ struct psp_gfx_cmd_invoke_cmd { … }; /* Command to setup TMR region. */ struct psp_gfx_cmd_setup_tmr { … }; /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ enum psp_gfx_fw_type { … }; /* Command to load HW IP FW. */ struct psp_gfx_cmd_load_ip_fw { … }; /* Command to save/restore HW IP FW. */ struct psp_gfx_cmd_save_restore_ip_fw { … }; /* Command to setup register program */ struct psp_gfx_cmd_reg_prog { … }; /* Command to load TOC */ struct psp_gfx_cmd_load_toc { … }; /* Dynamic boot configuration */ struct psp_gfx_cmd_boot_cfg { … }; struct psp_gfx_cmd_sriov_spatial_part { … }; /* All GFX ring buffer commands. */ psp_gfx_commands; struct psp_gfx_uresp_reserved { … }; /* Command-specific response for Fw Attestation Db */ struct psp_gfx_uresp_fwar_db_info { … }; /* Command-specific response for boot config. */ struct psp_gfx_uresp_bootcfg { … }; /* Union of command-specific responses for GPCOM ring. */ psp_gfx_uresp; /* Structure of GFX Response buffer. * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI * it is separate buffer. */ struct psp_gfx_resp { … }; /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi * and psp_gfx_rb_frame.cmd_buf_addr_lo. */ struct psp_gfx_cmd_resp { … }; #define FRAME_TYPE_DESTROY … /* Structure of the Ring Buffer Frame */ struct psp_gfx_rb_frame { … }; #define PSP_ERR_UNKNOWN_COMMAND … enum tee_error_code { … }; #endif /* _PSP_TEE_GFX_IF_H_ */
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