/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __AMDGPU_VCN_H__ #define __AMDGPU_VCN_H__ #include "amdgpu_ras.h" #define AMDGPU_VCN_STACK_SIZE … #define AMDGPU_VCN_CONTEXT_SIZE … #define AMDGPU_VCN_FIRMWARE_OFFSET … #define AMDGPU_VCN_MAX_ENC_RINGS … #define AMDGPU_MAX_VCN_INSTANCES … #define AMDGPU_MAX_VCN_ENC_RINGS … #define AMDGPU_VCN_HARVEST_VCN0 … #define AMDGPU_VCN_HARVEST_VCN1 … #define VCN_DEC_KMD_CMD … #define VCN_DEC_CMD_FENCE … #define VCN_DEC_CMD_TRAP … #define VCN_DEC_CMD_WRITE_REG … #define VCN_DEC_CMD_REG_READ_COND_WAIT … #define VCN_DEC_CMD_PACKET_START … #define VCN_DEC_CMD_PACKET_END … #define VCN_DEC_SW_CMD_NO_OP … #define VCN_DEC_SW_CMD_END … #define VCN_DEC_SW_CMD_IB … #define VCN_DEC_SW_CMD_FENCE … #define VCN_DEC_SW_CMD_TRAP … #define VCN_DEC_SW_CMD_IB_AUTO … #define VCN_DEC_SW_CMD_SEMAPHORE … #define VCN_DEC_SW_CMD_PREEMPT_FENCE … #define VCN_DEC_SW_CMD_REG_WRITE … #define VCN_DEC_SW_CMD_REG_WAIT … #define VCN_ENC_CMD_NO_OP … #define VCN_ENC_CMD_END … #define VCN_ENC_CMD_IB … #define VCN_ENC_CMD_FENCE … #define VCN_ENC_CMD_TRAP … #define VCN_ENC_CMD_REG_WRITE … #define VCN_ENC_CMD_REG_WAIT … #define VCN_AON_SOC_ADDRESS_2_0 … #define VCN1_AON_SOC_ADDRESS_3_0 … #define VCN_VID_IP_ADDRESS_2_0 … #define VCN_AON_IP_ADDRESS_2_0 … #define mmUVD_RBC_XX_IB_REG_CHECK … #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX … #define mmUVD_REG_XX_MASK … #define mmUVD_REG_XX_MASK_BASE_IDX … /* 1 second timeout */ #define VCN_IDLE_TIMEOUT … #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) … #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) … #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) … #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) … #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) … #define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) … #define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect) … #define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE … #define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT … #define AMDGPU_VCN_FW_SHARED_FLAG_0_RB … #define AMDGPU_VCN_MULTI_QUEUE_FLAG … #define AMDGPU_VCN_SW_RING_FLAG … #define AMDGPU_VCN_FW_LOGGING_FLAG … #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG … #define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG … #define AMDGPU_VCN_VF_RB_SETUP_FLAG … #define AMDGPU_VCN_VF_RB_DECOUPLE_FLAG … #define MAX_NUM_VCN_RB_SETUP … #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER … #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER … #define VCN_CODEC_DISABLE_MASK_AV1 … #define VCN_CODEC_DISABLE_MASK_VP9 … #define VCN_CODEC_DISABLE_MASK_HEVC … #define VCN_CODEC_DISABLE_MASK_H264 … #define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU … #define AMDGPU_VCN_SMU_DPM_INTERFACE_APU … #define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING … enum fw_queue_mode { … }; enum engine_status_constants { … }; enum internal_dpg_state { … }; struct dpg_pause_state { … }; struct amdgpu_vcn_reg{ … }; struct amdgpu_vcn_fw_shared { … }; struct amdgpu_vcn_inst { … }; struct amdgpu_vcn_ras { … }; struct amdgpu_vcn { … }; struct amdgpu_fw_shared_rb_ptrs_struct { … }; struct amdgpu_fw_shared_multi_queue { … }; struct amdgpu_fw_shared_sw_ring { … }; struct amdgpu_fw_shared_unified_queue_struct { … }; struct amdgpu_fw_shared_fw_logging { … }; struct amdgpu_fw_shared_smu_interface_info { … }; struct amdgpu_fw_shared { … }; struct amdgpu_vcn_rb_setup_info { … }; struct amdgpu_fw_shared_rb_setup { … }; struct amdgpu_fw_shared_drm_key_wa { … }; struct amdgpu_fw_shared_queue_decouple { … }; struct amdgpu_vcn4_fw_shared { … }; struct amdgpu_vcn_fwlog { … }; struct amdgpu_vcn_decode_buffer { … }; struct amdgpu_vcn_rb_metadata { … }; struct amdgpu_vcn5_fw_shared { … }; #define VCN_BLOCK_ENCODE_DISABLE_MASK … #define VCN_BLOCK_DECODE_DISABLE_MASK … #define VCN_BLOCK_QUEUE_DISABLE_MASK … enum vcn_ring_type { … }; int amdgpu_vcn_early_init(struct amdgpu_device *adev); int amdgpu_vcn_sw_init(struct amdgpu_device *adev); int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); int amdgpu_vcn_suspend(struct amdgpu_device *adev); int amdgpu_vcn_resume(struct amdgpu_device *adev); void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance); int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout); int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout); int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring); void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev); void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn); void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, struct amdgpu_vcn_inst *vcn); int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry); int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev); int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, enum AMDGPU_UCODE_ID ucode_id); #endif
Codebase Browser
linux