/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __AMDGPU_JPEG_H__ #define __AMDGPU_JPEG_H__ #include "amdgpu_ras.h" #define AMDGPU_MAX_JPEG_INSTANCES … #define AMDGPU_MAX_JPEG_RINGS … #define AMDGPU_JPEG_HARVEST_JPEG0 … #define AMDGPU_JPEG_HARVEST_JPEG1 … #define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect) … #define RREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, mask_en) … #define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect) … #define RREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, mask_en) … #define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect) … struct amdgpu_jpeg_reg{ … }; struct amdgpu_jpeg_inst { … }; struct amdgpu_jpeg_ras { … }; struct amdgpu_jpeg { … }; int amdgpu_jpeg_sw_init(struct amdgpu_device *adev); int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev); int amdgpu_jpeg_suspend(struct amdgpu_device *adev); int amdgpu_jpeg_resume(struct amdgpu_device *adev); void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring); void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring); int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry); int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev); int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, enum AMDGPU_UCODE_ID ucode_id); #endif /*__AMDGPU_JPEG_H__*/
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