/* SPDX-License-Identifier: MIT */ /* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __AMDGPU_UMSCH_MM_H__ #define __AMDGPU_UMSCH_MM_H__ enum UMSCH_SWIP_ENGINE_TYPE { … }; enum UMSCH_CONTEXT_PRIORITY_LEVEL { … }; struct umsch_mm_set_resource_input { … }; struct amdgpu_umsch_fwlog { … }; struct umsch_mm_add_queue_input { … }; struct umsch_mm_remove_queue_input { … }; struct MQD_INFO { … }; struct amdgpu_umsch_mm; struct umsch_mm_funcs { … }; struct amdgpu_umsch_mm { … }; int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws); int amdgpu_umsch_mm_query_fence(struct amdgpu_umsch_mm *umsch); int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch); int amdgpu_umsch_mm_allocate_ucode_buffer(struct amdgpu_umsch_mm *umsch); int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch); int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch); int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch); void amdgpu_debugfs_umsch_fwlog_init(struct amdgpu_device *adev, struct amdgpu_umsch_mm *umsch); void amdgpu_umsch_fwlog_init(struct amdgpu_umsch_mm *umsch_mm); #define WREG32_SOC15_UMSCH(reg, value) … #define umsch_mm_set_hw_resources(umsch) … #define umsch_mm_add_queue(umsch, input) … #define umsch_mm_remove_queue(umsch, input) … #define umsch_mm_set_regs(umsch) … #define umsch_mm_init_microcode(umsch) … #define umsch_mm_load_microcode(umsch) … #define umsch_mm_ring_init(umsch) … #define umsch_mm_ring_start(umsch) … #define umsch_mm_ring_stop(umsch) … #define umsch_mm_ring_fini(umsch) … static inline void amdgpu_umsch_mm_lock(struct amdgpu_umsch_mm *umsch) { … } static inline void amdgpu_umsch_mm_unlock(struct amdgpu_umsch_mm *umsch) { … } extern const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block; #endif
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