/* * Copyright 2018 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * */ #ifndef __AMDGPU_GMC_H__ #define __AMDGPU_GMC_H__ #include <linux/types.h> #include "amdgpu_irq.h" #include "amdgpu_ras.h" /* VA hole for 48bit addresses on Vega10 */ #define AMDGPU_GMC_HOLE_START … #define AMDGPU_GMC_HOLE_END … /* * Hardware is programmed as if the hole doesn't exists with start and end * address values. * * This mask is used to remove the upper 16bits of the VA and so come up with * the linear addr value. */ #define AMDGPU_GMC_HOLE_MASK … /* * Ring size as power of two for the log of recent faults. */ #define AMDGPU_GMC_FAULT_RING_ORDER … #define AMDGPU_GMC_FAULT_RING_SIZE … /* * Hash size as power of two for the log of recent faults */ #define AMDGPU_GMC_FAULT_HASH_ORDER … #define AMDGPU_GMC_FAULT_HASH_SIZE … /* * Number of IH timestamp ticks until a fault is considered handled */ #define AMDGPU_GMC_FAULT_TIMEOUT … struct firmware; enum amdgpu_memory_partition { … }; /* * GMC page fault information */ struct amdgpu_gmc_fault { … }; /* * VMHUB structures, functions & helpers */ struct amdgpu_vmhub_funcs { … }; struct amdgpu_vmhub { … }; /* * GPU MC structures, functions & helpers */ struct amdgpu_gmc_funcs { … }; struct amdgpu_xgmi_ras { … }; struct amdgpu_xgmi { … }; struct amdgpu_mem_partition_info { … }; #define INVALID_PFN … struct amdgpu_gmc_memrange { … }; enum amdgpu_gart_placement { … }; struct amdgpu_gmc { … }; #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) … #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) … #define amdgpu_gmc_map_mtype(adev, flags) … #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) … #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) … #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) … #define amdgpu_gmc_get_vbios_fb_size(adev) … /** * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR * * @adev: amdgpu_device pointer * * Returns: * True if full VRAM is visible through the BAR */ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) { … } /** * amdgpu_gmc_sign_extend - sign extend the given gmc address * * @addr: address to extend */ static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) { … } int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, uint64_t *addr, uint64_t *flags); int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, uint32_t gpu_page_idx, uint64_t addr, uint64_t flags); uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, u64 base); void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, enum amdgpu_gart_placement gart_placement); void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, struct amdgpu_gmc *mc); bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, uint64_t addr, uint16_t pasid, uint64_t timestamp); void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, uint16_t pasid); int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t vmhub, uint32_t flush_type); int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst); void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask, uint32_t xcc_inst); extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); extern void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, bool enable); void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges, int exp_ranges); #endif
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