/* * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __AMDGPU_DM_H__ #define __AMDGPU_DM_H__ #include <drm/display/drm_dp_mst_helper.h> #include <drm/drm_atomic.h> #include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include <drm/drm_plane.h> #include "link_service_types.h" #include <drm/drm_writeback.h> /* * This file contains the definition for amdgpu_display_manager * and its API for amdgpu driver's use. * This component provides all the display related functionality * and this is the only component that calls DAL API. * The API contained here intended for amdgpu driver use. * The API that is called directly from KMS framework is located * in amdgpu_dm_kms.h file */ #define AMDGPU_DM_MAX_DISPLAY_INDEX … #define AMDGPU_DM_MAX_CRTC … #define AMDGPU_DM_MAX_NUM_EDP … #define AMDGPU_DMUB_NOTIFICATION_MAX … #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID … #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE … #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 … #define AMDGPU_HDR_MULT_DEFAULT … /* #include "include/amdgpu_dal_power_if.h" #include "amdgpu_dm_irq.h" */ #include "irq_types.h" #include "signal_types.h" #include "amdgpu_dm_crc.h" #include "mod_info_packet.h" struct aux_payload; struct set_config_cmd_payload; enum aux_return_code_type; enum set_config_status; /* Forward declarations */ struct amdgpu_device; struct amdgpu_crtc; struct drm_device; struct dc; struct amdgpu_bo; struct dmub_srv; struct dc_plane_state; struct dmub_notification; struct amd_vsdb_block { … }; struct common_irq_params { … }; /** * struct dm_compressor_info - Buffer info used by frame buffer compression * @cpu_addr: MMIO cpu addr * @bo_ptr: Pointer to the buffer object * @gpu_addr: MMIO gpu addr */ struct dm_compressor_info { … }; dmub_notify_interrupt_callback_t; /** * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ * * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq * @dmub_notify: notification for callback function * @adev: amdgpu_device pointer */ struct dmub_hpd_work { … }; /** * struct vblank_control_work - Work data for vblank control * @work: Kernel work data for the work event * @dm: amdgpu display manager device * @acrtc: amdgpu CRTC instance for which the event has occurred * @stream: DC stream for which the event has occurred * @enable: true if enabling vblank */ struct vblank_control_work { … }; /** * struct idle_workqueue - Work data for periodic action in idle * @work: Kernel work data for the work event * @dm: amdgpu display manager device * @enable: true if idle worker is enabled * @running: true if idle worker is running */ struct idle_workqueue { … }; /** * struct amdgpu_dm_backlight_caps - Information about backlight * * Describe the backlight support for ACPI or eDP AUX. */ struct amdgpu_dm_backlight_caps { … }; /** * struct dal_allocation - Tracks mapped FB memory for SMU communication * @list: list of dal allocations * @bo: GPU buffer object * @cpu_ptr: CPU virtual address of the GPU buffer object * @gpu_addr: GPU virtual address of the GPU buffer object */ struct dal_allocation { … }; /** * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq * offload work */ struct hpd_rx_irq_offload_work_queue { … }; /** * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure */ struct hpd_rx_irq_offload_work { … }; /** * struct amdgpu_display_manager - Central amdgpu display manager device * * @dc: Display Core control structure * @adev: AMDGPU base driver structure * @ddev: DRM base driver structure * @display_indexes_num: Max number of display streams supported * @irq_handler_list_table_lock: Synchronizes access to IRQ tables * @backlight_dev: Backlight control device * @backlight_link: Link on which to control backlight * @backlight_caps: Capabilities of the backlight device * @freesync_module: Module handling freesync calculations * @hdcp_workqueue: AMDGPU content protection queue * @fw_dmcu: Reference to DMCU firmware * @dmcu_fw_version: Version of the DMCU firmware * @soc_bounding_box: SOC bounding box values provided by gpu_info FW * @cached_state: Caches device atomic state for suspend/resume * @cached_dc_state: Cached state of content streams * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info * @force_timing_sync: set via debugfs. When set, indicates that all connected * displays will be forced to synchronize. * @dmcub_trace_event_en: enable dmcub trace events * @dmub_outbox_params: DMUB Outbox parameters * @num_of_edps: number of backlight eDPs * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the * driver when true * @dmub_aux_transfer_done: struct completion used to indicate when DMUB * transfers are done * @delayed_hpd_wq: work queue used to delay DMUB HPD work */ struct amdgpu_display_manager { … }; enum dsc_clock_force_state { … }; struct dsc_preferred_settings { … }; enum mst_progress_status { … }; /** * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info * * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this * struct is useful to keep track of the display-specific information about * FreeSync. */ struct amdgpu_hdmi_vsdb_info { … }; struct amdgpu_dm_connector { … }; static inline void amdgpu_dm_set_mst_status(uint8_t *status, uint8_t flags, bool set) { … } #define to_amdgpu_dm_connector(x) … struct amdgpu_dm_wb_connector { … }; #define to_amdgpu_dm_wb_connector(x) … extern const struct amdgpu_ip_block_version dm_ip_block; /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. * * It includes standardized transfer functions and pure power functions. The * transfer function coefficients are available at modules/color/color_gamma.c */ enum amdgpu_transfer_function { … }; struct dm_plane_state { … }; enum amdgpu_dm_cursor_mode { … }; struct dm_crtc_state { … }; #define to_dm_crtc_state(x) … struct dm_atomic_state { … }; #define to_dm_atomic_state(x) … struct dm_connector_state { … }; #define to_dm_connector_state(x) … void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); struct drm_connector_state * amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, struct drm_connector_state *state, struct drm_property *property, uint64_t val); int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, const struct drm_connector_state *state, struct drm_property *property, uint64_t *val); int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector, int connector_type, struct dc_link *link, int link_index); enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode); void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, struct edid *edid); void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); /* 3D LUT max size is 17x17x17 (4913 entries) */ #define MAX_COLOR_3DLUT_SIZE … #define MAX_COLOR_3DLUT_BITDEPTH … int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, struct drm_plane_state *plane_state); /* 1D LUT size */ #define MAX_COLOR_LUT_ENTRIES … /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ #define MAX_COLOR_LEGACY_LUT_ENTRIES … void amdgpu_dm_init_color_mod(void); int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state); void amdgpu_dm_update_connector_after_detect( struct amdgpu_dm_connector *aconnector); extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, struct aux_payload *payload, enum aux_return_code_type *operation_result); int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, struct set_config_cmd_payload *payload, enum set_config_status *operation_result); struct dc_stream_state * create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state, const struct dc_stream_state *old_stream); int dm_atomic_get_state(struct drm_atomic_state *state, struct dm_atomic_state **dm_state); struct drm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, struct drm_crtc *crtc); int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); void *dm_allocate_gpu_mem(struct amdgpu_device *adev, enum dc_gpu_mem_alloc_type type, size_t size, long long *addr); bool amdgpu_dm_is_headless(struct amdgpu_device *adev); #endif /* __AMDGPU_DM_H__ */