/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __AMD_PCIE_H__ #define __AMD_PCIE_H__ /* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */ #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 … #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 … #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 … #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 … #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5 … #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK … #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT … /* Following flags shows PCIe link speed supported by ASIC H/W.*/ #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 … #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 … #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 … #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 … #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5 … #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK … #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT … /* gen: chipset 1/2, asic 1/2/3 */ #define AMDGPU_DEFAULT_PCIE_GEN_MASK … /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */ #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 … #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 … #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 … #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 … #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 … #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 … #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 … #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT … /* 1/2/4/8/16 lanes */ #define AMDGPU_DEFAULT_PCIE_MLW_MASK … #endif
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