/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Author: [email protected] */ #ifndef AMDGPU_VIRT_H #define AMDGPU_VIRT_H #include "amdgv_sriovmsg.h" #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS … #define AMDGPU_SRIOV_CAPS_ENABLE_IOV … #define AMDGPU_SRIOV_CAPS_IS_VF … #define AMDGPU_PASSTHROUGH_MODE … #define AMDGPU_SRIOV_CAPS_RUNTIME … #define AMDGPU_VF_MMIO_ACCESS_PROTECT … /* flags for indirect register access path supported by rlcg for sriov */ #define AMDGPU_RLCG_GC_WRITE_LEGACY … #define AMDGPU_RLCG_GC_WRITE … #define AMDGPU_RLCG_GC_READ … #define AMDGPU_RLCG_MMHUB_WRITE … /* error code for indirect register access path supported by rlcg for sriov */ #define AMDGPU_RLCG_VFGATE_DISABLED … #define AMDGPU_RLCG_WRONG_OPERATION_TYPE … #define AMDGPU_RLCG_REG_NOT_IN_RANGE … #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK … #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK … /* all asic after AI use this offset */ #define mmRCC_IOV_FUNC_IDENTIFIER … /* tonga/fiji use this offset */ #define mmBIF_IOV_FUNC_IDENTIFIER … #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT … enum amdgpu_sriov_vf_mode { … }; struct amdgpu_mm_table { … }; #define AMDGPU_VF_ERROR_ENTRY_SIZE … /* struct error_entry - amdgpu VF error information. */ struct amdgpu_vf_error_buffer { … }; enum idh_request; /** * struct amdgpu_virt_ops - amdgpu device virt operations */ struct amdgpu_virt_ops { … }; /* * Firmware Reserve Frame buffer */ struct amdgpu_virt_fw_reserve { … }; /* * Legacy GIM header * * Defination between PF and VF * Structures forcibly aligned to 4 to keep the same style as PF. */ #define AMDGIM_DATAEXCHANGE_OFFSET … #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) … enum AMDGIM_FEATURE_FLAG { … }; enum AMDGIM_REG_ACCESS_FLAG { … }; struct amdgim_pf2vf_info_v1 { … } __aligned(…); struct amdgim_vf2pf_info_v1 { … } __aligned(…); struct amdgim_vf2pf_info_v2 { … } __aligned(…); struct amdgpu_virt_ras_err_handler_data { … }; /* GPU virtualization */ struct amdgpu_virt { … }; struct amdgpu_video_codec_info; #define amdgpu_sriov_enabled(adev) … #define amdgpu_sriov_vf(adev) … #define amdgpu_sriov_bios(adev) … #define amdgpu_sriov_runtime(adev) … #define amdgpu_sriov_fullaccess(adev) … #define amdgpu_sriov_reg_indirect_en(adev) … #define amdgpu_sriov_reg_indirect_ih(adev) … #define amdgpu_sriov_reg_indirect_mmhub(adev) … #define amdgpu_sriov_reg_indirect_gc(adev) … #define amdgpu_sriov_rlcg_error_report_enabled(adev) … #define amdgpu_passthrough(adev) … #define amdgpu_sriov_vf_mmio_access_protection(adev) … static inline bool is_virtual_machine(void) { … } #define amdgpu_sriov_is_pp_one_vf(adev) … #define amdgpu_sriov_is_debug(adev) … #define amdgpu_sriov_is_normal(adev) … #define amdgpu_sriov_is_av1_support(adev) … #define amdgpu_sriov_is_vcn_rb_decouple(adev) … #define amdgpu_sriov_is_mes_info_enable(adev) … bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); void amdgpu_virt_init_setting(struct amdgpu_device *adev); int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); void amdgpu_virt_request_init_data(struct amdgpu_device *adev); void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); int amdgpu_virt_wait_reset(struct amdgpu_device *adev); int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev); void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); void amdgpu_virt_exchange_data(struct amdgpu_device *adev); void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); void amdgpu_detect_virtualization(struct amdgpu_device *adev); bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); void amdgpu_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip, u32 xcc_id); u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id); void amdgpu_virt_post_reset(struct amdgpu_device *adev); bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip, bool write, u32 *rlcg_flag); u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); #endif
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