/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __AMDGPU_MES_CTX_H__ #define __AMDGPU_MES_CTX_H__ #include "v10_structs.h" enum { … }; enum { … }; #define AMDGPU_MES_CTX_MAX_GFX_RINGS … #define AMDGPU_MES_CTX_MAX_COMPUTE_RINGS … #define AMDGPU_MES_CTX_MAX_SDMA_RINGS … #define AMDGPU_MES_CTX_MAX_RINGS … #define AMDGPU_CSA_SDMA_SIZE … #define GFX10_MEC_HPD_SIZE … struct amdgpu_wb_slot { … }; struct amdgpu_mes_ctx_meta_data { … }; struct amdgpu_mes_ctx_data { … }; #define AMDGPU_FENCE_MES_QUEUE_FLAG … #define AMDGPU_FENCE_MES_QUEUE_ID_MASK … #define AMDGPU_FENCE_MES_QUEUE_FLAG … #define AMDGPU_FENCE_MES_QUEUE_ID_MASK … #endif
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