#ifndef __AMDGPU_MES_H__
#define __AMDGPU_MES_H__
#include "amdgpu_irq.h"
#include "kgd_kfd_interface.h"
#include "amdgpu_gfx.h"
#include "amdgpu_doorbell.h"
#include <linux/sched/mm.h>
#define AMDGPU_MES_MAX_COMPUTE_PIPES …
#define AMDGPU_MES_MAX_GFX_PIPES …
#define AMDGPU_MES_MAX_SDMA_PIPES …
#define AMDGPU_MES_API_VERSION_SHIFT …
#define AMDGPU_MES_FEAT_VERSION_SHIFT …
#define AMDGPU_MES_VERSION_MASK …
#define AMDGPU_MES_API_VERSION_MASK …
#define AMDGPU_MES_FEAT_VERSION_MASK …
enum amdgpu_mes_priority_level { … };
#define AMDGPU_MES_PROC_CTX_SIZE …
#define AMDGPU_MES_GANG_CTX_SIZE …
struct amdgpu_mes_funcs;
enum admgpu_mes_pipe { … };
struct amdgpu_mes { … };
struct amdgpu_mes_process { … };
struct amdgpu_mes_gang { … };
struct amdgpu_mes_queue { … };
struct amdgpu_mes_queue_properties { … };
struct amdgpu_mes_gang_properties { … };
struct mes_add_queue_input { … };
struct mes_remove_queue_input { … };
struct mes_map_legacy_queue_input { … };
struct mes_unmap_legacy_queue_input { … };
struct mes_suspend_gang_input { … };
struct mes_resume_gang_input { … };
enum mes_misc_opcode { … };
struct mes_misc_op_input { … };
struct amdgpu_mes_funcs { … };
#define amdgpu_mes_kiq_hw_init(adev) …
#define amdgpu_mes_kiq_hw_fini(adev) …
int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
int amdgpu_mes_init(struct amdgpu_device *adev);
void amdgpu_mes_fini(struct amdgpu_device *adev);
int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,
struct amdgpu_vm *vm);
void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid);
int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,
struct amdgpu_mes_gang_properties *gprops,
int *gang_id);
int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id);
int amdgpu_mes_suspend(struct amdgpu_device *adev);
int amdgpu_mes_resume(struct amdgpu_device *adev);
int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
struct amdgpu_mes_queue_properties *qprops,
int *queue_id);
int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);
int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
struct amdgpu_ring *ring);
int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
struct amdgpu_ring *ring,
enum amdgpu_unmap_queues_action action,
u64 gpu_addr, u64 seq);
uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
int amdgpu_mes_wreg(struct amdgpu_device *adev,
uint32_t reg, uint32_t val);
int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
uint32_t val, uint32_t mask);
int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
uint32_t reg0, uint32_t reg1,
uint32_t ref, uint32_t mask);
int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
uint32_t flags,
bool trap_en);
int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
uint64_t process_context_addr);
int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
int queue_type, int idx,
struct amdgpu_mes_ctx_data *ctx_data,
struct amdgpu_ring **out);
void amdgpu_mes_remove_ring(struct amdgpu_device *adev,
struct amdgpu_ring *ring);
uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
enum amdgpu_mes_priority_level prio);
int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
struct amdgpu_mes_ctx_data *ctx_data);
void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data);
int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
struct amdgpu_mes_ctx_data *ctx_data);
int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
struct amdgpu_mes_ctx_data *ctx_data);
int amdgpu_mes_self_test(struct amdgpu_device *adev);
int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
{ … }
static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
{ … }
#endif