/* * Copyright (C) 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __AMDGPU_MCA_H__ #define __AMDGPU_MCA_H__ #include "amdgpu_ras.h" #define MCA_MAX_REGS_COUNT … #define MCA_REG_FIELD(x, h, l) … #define MCA_REG__STATUS__VAL(x) … #define MCA_REG__STATUS__OVERFLOW(x) … #define MCA_REG__STATUS__UC(x) … #define MCA_REG__STATUS__EN(x) … #define MCA_REG__STATUS__MISCV(x) … #define MCA_REG__STATUS__ADDRV(x) … #define MCA_REG__STATUS__PCC(x) … #define MCA_REG__STATUS__ERRCOREIDVAL(x) … #define MCA_REG__STATUS__TCC(x) … #define MCA_REG__STATUS__SYNDV(x) … #define MCA_REG__STATUS__CECC(x) … #define MCA_REG__STATUS__UECC(x) … #define MCA_REG__STATUS__DEFERRED(x) … #define MCA_REG__STATUS__POISON(x) … #define MCA_REG__STATUS__SCRUB(x) … #define MCA_REG__STATUS__ERRCOREID(x) … #define MCA_REG__STATUS__ADDRLSB(x) … #define MCA_REG__STATUS__ERRORCODEEXT(x) … #define MCA_REG__STATUS__ERRORCODE(x) … #define MCA_REG__MISC0__ERRCNT(x) … #define MCA_REG__SYND__ERRORINFORMATION(x) … enum amdgpu_mca_ip { … }; enum amdgpu_mca_error_type { … }; struct amdgpu_mca_ras_block { … }; struct amdgpu_mca_ras { … }; struct mca_bank_set { … }; struct mca_bank_cache { … }; struct amdgpu_mca { … }; enum mca_reg_idx { … }; struct mca_bank_info { … }; struct mca_bank_entry { … }; struct mca_bank_node { … }; struct amdgpu_mca_smu_funcs { … }; void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev, uint64_t mc_status_addr, unsigned long *error_count); void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev, uint64_t mc_status_addr, unsigned long *error_count); void amdgpu_mca_reset_error_count(struct amdgpu_device *adev, uint64_t mc_status_addr); void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, uint64_t mc_status_addr, void *ras_error_status); int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev); int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev); int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev); void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs); int amdgpu_mca_init(struct amdgpu_device *adev); void amdgpu_mca_fini(struct amdgpu_device *adev); int amdgpu_mca_reset(struct amdgpu_device *adev); int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable); int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, uint32_t *total); void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root); int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data, struct ras_query_context *qctx); #endif
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