#include <linux/module.h>
#ifdef CONFIG_X86
#include <asm/hypervisor.h>
#endif
#include <drm/drm_drv.h>
#include <xen/xen.h>
#include "amdgpu.h"
#include "amdgpu_ras.h"
#include "amdgpu_reset.h"
#include "vi.h"
#include "soc15.h"
#include "nv.h"
#define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) …
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_init_setting(struct amdgpu_device *adev)
{ … }
int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
{ … }
int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
{ … }
int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev)
{ … }
int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
{ … }
int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
{ … }
bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev)
{ … }
unsigned int amd_sriov_msg_checksum(void *obj,
unsigned long obj_size,
unsigned int key,
unsigned int checksum)
{ … }
static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
{ … }
static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
{ … }
static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
struct eeprom_table_record *bps, int pages)
{ … }
static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
{ … }
static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
uint64_t retired_page)
{ … }
static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
uint64_t bp_block_offset, uint32_t bp_block_size)
{ … }
static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
{ … }
static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
{ … }
static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
{ … }
static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
{ … }
void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
{ … }
void amdgpu_detect_virtualization(struct amdgpu_device *adev)
{ … }
static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
{ … }
static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
{ … }
int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
{ … }
enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
{ … }
void amdgpu_virt_post_reset(struct amdgpu_device *adev)
{ … }
bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)
{ … }
void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)
{ … }
bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
u32 acc_flags, u32 hwip,
bool write, u32 *rlcg_flag)
{ … }
u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
{ … }
void amdgpu_sriov_wreg(struct amdgpu_device *adev,
u32 offset, u32 value,
u32 acc_flags, u32 hwip, u32 xcc_id)
{ … }
u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id)
{ … }
bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev)
{ … }