/* * Copyright (C) 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _soc15_hw_ip_HEADER #define _soc15_hw_ip_HEADER // HW ID #define MP1_HWID … #define MP2_HWID … #define THM_HWID … #define SMUIO_HWID … #define FUSE_HWID … #define CLKA_HWID … #define PWR_HWID … #define GC_HWID … #define UVD_HWID … #define VCN_HWID … #define AUDIO_AZ_HWID … #define ACP_HWID … #define DCI_HWID … #define DMU_HWID … #define DCO_HWID … #define DIO_HWID … #define XDMA_HWID … #define DCEAZ_HWID … #define DAZ_HWID … #define SDPMUX_HWID … #define NTB_HWID … #define VPE_HWID … #define IOHC_HWID … #define L2IMU_HWID … #define VCE_HWID … #define MMHUB_HWID … #define ATHUB_HWID … #define DBGU_NBIO_HWID … #define DFX_HWID … #define DBGU0_HWID … #define DBGU1_HWID … #define OSSSYS_HWID … #define HDP_HWID … #define SDMA0_HWID … #define SDMA1_HWID … #define ISP_HWID … #define DBGU_IO_HWID … #define DF_HWID … #define CLKB_HWID … #define FCH_HWID … #define DFX_DAP_HWID … #define L1IMU_PCIE_HWID … #define L1IMU_NBIF_HWID … #define L1IMU_IOAGR_HWID … #define L1IMU3_HWID … #define L1IMU4_HWID … #define L1IMU5_HWID … #define L1IMU6_HWID … #define L1IMU7_HWID … #define L1IMU8_HWID … #define L1IMU9_HWID … #define L1IMU10_HWID … #define L1IMU11_HWID … #define L1IMU12_HWID … #define L1IMU13_HWID … #define L1IMU14_HWID … #define L1IMU15_HWID … #define WAFLC_HWID … #define FCH_USB_PD_HWID … #define SDMA2_HWID … #define SDMA3_HWID … #define PCIE_HWID … #define PCS_HWID … #define DDCL_HWID … #define SST_HWID … #define LSDMA_HWID … #define IOAGR_HWID … #define NBIF_HWID … #define IOAPIC_HWID … #define SYSTEMHUB_HWID … #define NTBCCP_HWID … #define UMC_HWID … #define SATA_HWID … #define USB_HWID … #define CCXSEC_HWID … #define XGMI_HWID … #define XGBE_HWID … #define MP0_HWID … #endif
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