/* * Copyright (C) 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _df_3_6_OFFSET_HEADER #define _df_3_6_OFFSET_HEADER #define mmFabricConfigAccessControl … #define mmFabricConfigAccessControl_BASE_IDX … #define mmDF_PIE_AON0_DfGlobalClkGater … #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX … #define mmDF_CS_UMC_AON0_DfGlobalCtrl … #define mmDF_CS_UMC_AON0_DfGlobalCtrl_BASE_IDX … #define mmDF_CS_UMC_AON0_DramBaseAddress0 … #define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX … #define mmDF_GCM_AON0_DramMegaBaseAddress0 … #define mmDF_GCM_AON0_DramMegaBaseAddress0_BASE_IDX … #define smnPerfMonCtlLo0 … #define smnPerfMonCtlHi0 … #define smnPerfMonCtlLo1 … #define smnPerfMonCtlHi1 … #define smnPerfMonCtlLo2 … #define smnPerfMonCtlHi2 … #define smnPerfMonCtlLo3 … #define smnPerfMonCtlHi3 … #define smnPerfMonCtlLo4 … #define smnPerfMonCtlHi4 … #define smnPerfMonCtlLo5 … #define smnPerfMonCtlHi5 … #define smnPerfMonCtlLo6 … #define smnPerfMonCtlHi6 … #define smnPerfMonCtlLo7 … #define smnPerfMonCtlHi7 … #define smnPerfMonCtrLo0 … #define smnPerfMonCtrHi0 … #define smnPerfMonCtrLo1 … #define smnPerfMonCtrHi1 … #define smnPerfMonCtrLo2 … #define smnPerfMonCtrHi2 … #define smnPerfMonCtrLo3 … #define smnPerfMonCtrHi3 … #define smnPerfMonCtrLo4 … #define smnPerfMonCtrHi4 … #define smnPerfMonCtrLo5 … #define smnPerfMonCtrHi5 … #define smnPerfMonCtrLo6 … #define smnPerfMonCtrHi6 … #define smnPerfMonCtrLo7 … #define smnPerfMonCtrHi7 … #define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3 … #define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3 … #define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3 … #define smnDF_CS_UMC_AON0_DramBaseAddress0 … #define smnDF_CS_UMC_AON0_DramLimitAddress0 … #define mmDF_CS_UMC_AON0_HardwareAssertMaskLow … #define mmDF_CS_UMC_AON0_HardwareAssertMaskLow_BASE_IDX … #define mmDF_NCS_PG0_HardwareAssertMaskHigh … #define mmDF_NCS_PG0_HardwareAssertMaskHigh_BASE_IDX … #endif
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