linux/drivers/gpu/drm/amd/include/asic_reg/xgmi/xgmi_6_1_0_sh_mask.h

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _xgmi_6_1_0_SH_MASK_HEADER
#define _xgmi_6_1_0_SH_MASK_HEADER

//PCS_XGMI3X16_PCS_ERROR_STATUS
#define PCS_XGMI3X16_PCS_ERROR_STATUS__DataLossErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__TrainingErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__FlowCtrlAckErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RxFifoUnderflowErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RxFifoOverflowErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__CRCErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__BERExceededErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__TxVcidDataErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReplayBufParityErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__DataParityErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReplayFifoOverflowErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReplayFifoUnderflowErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ElasticFifoOverflowErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__DeskewErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__FlowCtrlCRCErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__DataStartupLimitErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__FCInitTimeoutErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RecoveryTimeoutErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReadySerialTimeoutErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReadySerialAttemptErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RecoveryAttemptErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RecoveryRelockAttemptErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReplayAttemptErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__SyncHdrErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__TxReplayTimeoutErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RxReplayTimeoutErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__LinkSubTxTimeoutErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__LinkSubRxTimeoutErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RxCMDPktErr__SHIFT
#define PCS_XGMI3X16_PCS_ERROR_STATUS__DataLossErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__TrainingErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__FlowCtrlAckErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RxFifoUnderflowErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RxFifoOverflowErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__CRCErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__BERExceededErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__TxVcidDataErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReplayBufParityErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__DataParityErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReplayFifoOverflowErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReplayFifoUnderflowErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ElasticFifoOverflowErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__DeskewErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__FlowCtrlCRCErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__DataStartupLimitErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__FCInitTimeoutErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RecoveryTimeoutErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReadySerialTimeoutErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReadySerialAttemptErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RecoveryAttemptErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RecoveryRelockAttemptErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__ReplayAttemptErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__SyncHdrErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__TxReplayTimeoutErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RxReplayTimeoutErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__LinkSubTxTimeoutErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__LinkSubRxTimeoutErr_MASK
#define PCS_XGMI3X16_PCS_ERROR_STATUS__RxCMDPktErr_MASK

#endif