/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "amdgpu_vm.h" #include "amdgpu_job.h" #include "amdgpu_object.h" #include "amdgpu_trace.h" #define AMDGPU_VM_SDMA_MIN_NUM_DW … #define AMDGPU_VM_SDMA_MAX_NUM_DW … /** * amdgpu_vm_sdma_map_table - make sure new PDs/PTs are GTT mapped * * @table: newly allocated or validated PD/PT */ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table) { … } /* Allocate a new job for @count PTE updates */ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p, unsigned int count) { … } /** * amdgpu_vm_sdma_prepare - prepare SDMA command submission * * @p: see amdgpu_vm_update_params definition * @resv: reservation object with embedded fence * @sync_mode: synchronization mode * * Returns: * Negativ errno, 0 for success. */ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p, struct dma_resv *resv, enum amdgpu_sync_mode sync_mode) { … } /** * amdgpu_vm_sdma_commit - commit SDMA command submission * * @p: see amdgpu_vm_update_params definition * @fence: resulting fence * * Returns: * Negativ errno, 0 for success. */ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, struct dma_fence **fence) { … } /** * amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping * * @p: see amdgpu_vm_update_params definition * @bo: PD/PT to update * @pe: addr of the page entry * @count: number of page entries to copy * * Traces the parameters and calls the DMA function to copy the PTEs. */ static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p, struct amdgpu_bo *bo, uint64_t pe, unsigned count) { … } /** * amdgpu_vm_sdma_set_ptes - helper to call the right asic function * * @p: see amdgpu_vm_update_params definition * @bo: PD/PT to update * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB * @addr: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes * @flags: hw access flags * * Traces the parameters and calls the right asic functions * to setup the page table using the DMA. */ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p, struct amdgpu_bo *bo, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags) { … } /** * amdgpu_vm_sdma_update - execute VM update * * @p: see amdgpu_vm_update_params definition * @vmbo: PD/PT to update * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB * @addr: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes * @flags: hw access flags * * Reserve space in the IB, setup mapping buffer on demand and write commands to * the IB. */ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, struct amdgpu_bo_vm *vmbo, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags) { … } const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs = …;
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