/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _umc_6_7_0_OFFSET_HEADER #define _umc_6_7_0_OFFSET_HEADER // addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map // base address: 0x50f00 #define regMCA_UMC_UMC0_MCUMC_STATUST0 … #define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX … #define regMCA_UMC_UMC0_MCUMC_ADDRT0 … #define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX … #define regMCA_UMC_UMC0_MCUMC_MISC0T0 … #define regMCA_UMC_UMC0_MCUMC_MISC0T0_BASE_IDX … #define regMCA_UMC_UMC0_MCUMC_IPIDT0 … #define regMCA_UMC_UMC0_MCUMC_IPIDT0_BASE_IDX … #define regMCA_UMC_UMC0_MCUMC_SYNDT0 … #define regMCA_UMC_UMC0_MCUMC_SYNDT0_BASE_IDX … // addressBlock: umc_w_phy_umc0_umcch0_umcchdec // base address: 0x50000 #define regUMCCH0_0_BaseAddrCS0 … #define regUMCCH0_0_BaseAddrCS0_BASE_IDX … #define regUMCCH0_0_AddrMaskCS01 … #define regUMCCH0_0_AddrMaskCS01_BASE_IDX … #define regUMCCH0_0_AddrSelCS01 … #define regUMCCH0_0_AddrSelCS01_BASE_IDX … #define regUMCCH0_0_AddrHashBank0 … #define regUMCCH0_0_AddrHashBank0_BASE_IDX … #define regUMCCH0_0_AddrHashBank1 … #define regUMCCH0_0_AddrHashBank1_BASE_IDX … #define regUMCCH0_0_AddrHashBank2 … #define regUMCCH0_0_AddrHashBank2_BASE_IDX … #define regUMCCH0_0_AddrHashBank3 … #define regUMCCH0_0_AddrHashBank3_BASE_IDX … #define regUMCCH0_0_AddrHashBank4 … #define regUMCCH0_0_AddrHashBank4_BASE_IDX … #define regUMCCH0_0_AddrHashBank5 … #define regUMCCH0_0_AddrHashBank5_BASE_IDX … #define regUMCCH0_0_UMC_CONFIG … #define regUMCCH0_0_UMC_CONFIG_BASE_IDX … #define regUMCCH0_0_EccCtrl … #define regUMCCH0_0_EccCtrl_BASE_IDX … #define regUMCCH0_0_UmcLocalCap … #define regUMCCH0_0_UmcLocalCap_BASE_IDX … #define regUMCCH0_0_EccErrCntSel … #define regUMCCH0_0_EccErrCntSel_BASE_IDX … #define regUMCCH0_0_EccErrCnt … #define regUMCCH0_0_EccErrCnt_BASE_IDX … #define regUMCCH0_0_PerfMonCtlClk … #define regUMCCH0_0_PerfMonCtlClk_BASE_IDX … #define regUMCCH0_0_PerfMonCtrClk_Lo … #define regUMCCH0_0_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtrClk_Hi … #define regUMCCH0_0_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH0_0_PerfMonCtl1 … #define regUMCCH0_0_PerfMonCtl1_BASE_IDX … #define regUMCCH0_0_PerfMonCtr1_Lo … #define regUMCCH0_0_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtr1_Hi … #define regUMCCH0_0_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH0_0_PerfMonCtl2 … #define regUMCCH0_0_PerfMonCtl2_BASE_IDX … #define regUMCCH0_0_PerfMonCtr2_Lo … #define regUMCCH0_0_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtr2_Hi … #define regUMCCH0_0_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH0_0_PerfMonCtl3 … #define regUMCCH0_0_PerfMonCtl3_BASE_IDX … #define regUMCCH0_0_PerfMonCtr3_Lo … #define regUMCCH0_0_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtr3_Hi … #define regUMCCH0_0_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH0_0_PerfMonCtl4 … #define regUMCCH0_0_PerfMonCtl4_BASE_IDX … #define regUMCCH0_0_PerfMonCtr4_Lo … #define regUMCCH0_0_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtr4_Hi … #define regUMCCH0_0_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH0_0_PerfMonCtl5 … #define regUMCCH0_0_PerfMonCtl5_BASE_IDX … #define regUMCCH0_0_PerfMonCtr5_Lo … #define regUMCCH0_0_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtr5_Hi … #define regUMCCH0_0_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH0_0_PerfMonCtl6 … #define regUMCCH0_0_PerfMonCtl6_BASE_IDX … #define regUMCCH0_0_PerfMonCtr6_Lo … #define regUMCCH0_0_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtr6_Hi … #define regUMCCH0_0_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH0_0_PerfMonCtl7 … #define regUMCCH0_0_PerfMonCtl7_BASE_IDX … #define regUMCCH0_0_PerfMonCtr7_Lo … #define regUMCCH0_0_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtr7_Hi … #define regUMCCH0_0_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH0_0_PerfMonCtl8 … #define regUMCCH0_0_PerfMonCtl8_BASE_IDX … #define regUMCCH0_0_PerfMonCtr8_Lo … #define regUMCCH0_0_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH0_0_PerfMonCtr8_Hi … #define regUMCCH0_0_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc0_umcch1_umcchdec // base address: 0x51000 #define regUMCCH1_0_BaseAddrCS0 … #define regUMCCH1_0_BaseAddrCS0_BASE_IDX … #define regUMCCH1_0_AddrMaskCS01 … #define regUMCCH1_0_AddrMaskCS01_BASE_IDX … #define regUMCCH1_0_AddrSelCS01 … #define regUMCCH1_0_AddrSelCS01_BASE_IDX … #define regUMCCH1_0_AddrHashBank0 … #define regUMCCH1_0_AddrHashBank0_BASE_IDX … #define regUMCCH1_0_AddrHashBank1 … #define regUMCCH1_0_AddrHashBank1_BASE_IDX … #define regUMCCH1_0_AddrHashBank2 … #define regUMCCH1_0_AddrHashBank2_BASE_IDX … #define regUMCCH1_0_AddrHashBank3 … #define regUMCCH1_0_AddrHashBank3_BASE_IDX … #define regUMCCH1_0_AddrHashBank4 … #define regUMCCH1_0_AddrHashBank4_BASE_IDX … #define regUMCCH1_0_AddrHashBank5 … #define regUMCCH1_0_AddrHashBank5_BASE_IDX … #define regUMCCH1_0_UMC_CONFIG … #define regUMCCH1_0_UMC_CONFIG_BASE_IDX … #define regUMCCH1_0_EccCtrl … #define regUMCCH1_0_EccCtrl_BASE_IDX … #define regUMCCH1_0_UmcLocalCap … #define regUMCCH1_0_UmcLocalCap_BASE_IDX … #define regUMCCH1_0_EccErrCntSel … #define regUMCCH1_0_EccErrCntSel_BASE_IDX … #define regUMCCH1_0_EccErrCnt … #define regUMCCH1_0_EccErrCnt_BASE_IDX … #define regUMCCH1_0_PerfMonCtlClk … #define regUMCCH1_0_PerfMonCtlClk_BASE_IDX … #define regUMCCH1_0_PerfMonCtrClk_Lo … #define regUMCCH1_0_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtrClk_Hi … #define regUMCCH1_0_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH1_0_PerfMonCtl1 … #define regUMCCH1_0_PerfMonCtl1_BASE_IDX … #define regUMCCH1_0_PerfMonCtr1_Lo … #define regUMCCH1_0_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtr1_Hi … #define regUMCCH1_0_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH1_0_PerfMonCtl2 … #define regUMCCH1_0_PerfMonCtl2_BASE_IDX … #define regUMCCH1_0_PerfMonCtr2_Lo … #define regUMCCH1_0_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtr2_Hi … #define regUMCCH1_0_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH1_0_PerfMonCtl3 … #define regUMCCH1_0_PerfMonCtl3_BASE_IDX … #define regUMCCH1_0_PerfMonCtr3_Lo … #define regUMCCH1_0_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtr3_Hi … #define regUMCCH1_0_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH1_0_PerfMonCtl4 … #define regUMCCH1_0_PerfMonCtl4_BASE_IDX … #define regUMCCH1_0_PerfMonCtr4_Lo … #define regUMCCH1_0_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtr4_Hi … #define regUMCCH1_0_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH1_0_PerfMonCtl5 … #define regUMCCH1_0_PerfMonCtl5_BASE_IDX … #define regUMCCH1_0_PerfMonCtr5_Lo … #define regUMCCH1_0_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtr5_Hi … #define regUMCCH1_0_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH1_0_PerfMonCtl6 … #define regUMCCH1_0_PerfMonCtl6_BASE_IDX … #define regUMCCH1_0_PerfMonCtr6_Lo … #define regUMCCH1_0_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtr6_Hi … #define regUMCCH1_0_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH1_0_PerfMonCtl7 … #define regUMCCH1_0_PerfMonCtl7_BASE_IDX … #define regUMCCH1_0_PerfMonCtr7_Lo … #define regUMCCH1_0_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtr7_Hi … #define regUMCCH1_0_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH1_0_PerfMonCtl8 … #define regUMCCH1_0_PerfMonCtl8_BASE_IDX … #define regUMCCH1_0_PerfMonCtr8_Lo … #define regUMCCH1_0_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH1_0_PerfMonCtr8_Hi … #define regUMCCH1_0_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc0_umcch2_umcchdec // base address: 0x52000 #define regUMCCH2_0_BaseAddrCS0 … #define regUMCCH2_0_BaseAddrCS0_BASE_IDX … #define regUMCCH2_0_AddrMaskCS01 … #define regUMCCH2_0_AddrMaskCS01_BASE_IDX … #define regUMCCH2_0_AddrSelCS01 … #define regUMCCH2_0_AddrSelCS01_BASE_IDX … #define regUMCCH2_0_AddrHashBank0 … #define regUMCCH2_0_AddrHashBank0_BASE_IDX … #define regUMCCH2_0_AddrHashBank1 … #define regUMCCH2_0_AddrHashBank1_BASE_IDX … #define regUMCCH2_0_AddrHashBank2 … #define regUMCCH2_0_AddrHashBank2_BASE_IDX … #define regUMCCH2_0_AddrHashBank3 … #define regUMCCH2_0_AddrHashBank3_BASE_IDX … #define regUMCCH2_0_AddrHashBank4 … #define regUMCCH2_0_AddrHashBank4_BASE_IDX … #define regUMCCH2_0_AddrHashBank5 … #define regUMCCH2_0_AddrHashBank5_BASE_IDX … #define regUMCCH2_0_UMC_CONFIG … #define regUMCCH2_0_UMC_CONFIG_BASE_IDX … #define regUMCCH2_0_EccCtrl … #define regUMCCH2_0_EccCtrl_BASE_IDX … #define regUMCCH2_0_UmcLocalCap … #define regUMCCH2_0_UmcLocalCap_BASE_IDX … #define regUMCCH2_0_EccErrCntSel … #define regUMCCH2_0_EccErrCntSel_BASE_IDX … #define regUMCCH2_0_EccErrCnt … #define regUMCCH2_0_EccErrCnt_BASE_IDX … #define regUMCCH2_0_PerfMonCtlClk … #define regUMCCH2_0_PerfMonCtlClk_BASE_IDX … #define regUMCCH2_0_PerfMonCtrClk_Lo … #define regUMCCH2_0_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtrClk_Hi … #define regUMCCH2_0_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH2_0_PerfMonCtl1 … #define regUMCCH2_0_PerfMonCtl1_BASE_IDX … #define regUMCCH2_0_PerfMonCtr1_Lo … #define regUMCCH2_0_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtr1_Hi … #define regUMCCH2_0_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH2_0_PerfMonCtl2 … #define regUMCCH2_0_PerfMonCtl2_BASE_IDX … #define regUMCCH2_0_PerfMonCtr2_Lo … #define regUMCCH2_0_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtr2_Hi … #define regUMCCH2_0_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH2_0_PerfMonCtl3 … #define regUMCCH2_0_PerfMonCtl3_BASE_IDX … #define regUMCCH2_0_PerfMonCtr3_Lo … #define regUMCCH2_0_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtr3_Hi … #define regUMCCH2_0_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH2_0_PerfMonCtl4 … #define regUMCCH2_0_PerfMonCtl4_BASE_IDX … #define regUMCCH2_0_PerfMonCtr4_Lo … #define regUMCCH2_0_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtr4_Hi … #define regUMCCH2_0_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH2_0_PerfMonCtl5 … #define regUMCCH2_0_PerfMonCtl5_BASE_IDX … #define regUMCCH2_0_PerfMonCtr5_Lo … #define regUMCCH2_0_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtr5_Hi … #define regUMCCH2_0_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH2_0_PerfMonCtl6 … #define regUMCCH2_0_PerfMonCtl6_BASE_IDX … #define regUMCCH2_0_PerfMonCtr6_Lo … #define regUMCCH2_0_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtr6_Hi … #define regUMCCH2_0_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH2_0_PerfMonCtl7 … #define regUMCCH2_0_PerfMonCtl7_BASE_IDX … #define regUMCCH2_0_PerfMonCtr7_Lo … #define regUMCCH2_0_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtr7_Hi … #define regUMCCH2_0_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH2_0_PerfMonCtl8 … #define regUMCCH2_0_PerfMonCtl8_BASE_IDX … #define regUMCCH2_0_PerfMonCtr8_Lo … #define regUMCCH2_0_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH2_0_PerfMonCtr8_Hi … #define regUMCCH2_0_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc0_umcch3_umcchdec // base address: 0x53000 #define regUMCCH3_0_BaseAddrCS0 … #define regUMCCH3_0_BaseAddrCS0_BASE_IDX … #define regUMCCH3_0_AddrMaskCS01 … #define regUMCCH3_0_AddrMaskCS01_BASE_IDX … #define regUMCCH3_0_AddrSelCS01 … #define regUMCCH3_0_AddrSelCS01_BASE_IDX … #define regUMCCH3_0_AddrHashBank0 … #define regUMCCH3_0_AddrHashBank0_BASE_IDX … #define regUMCCH3_0_AddrHashBank1 … #define regUMCCH3_0_AddrHashBank1_BASE_IDX … #define regUMCCH3_0_AddrHashBank2 … #define regUMCCH3_0_AddrHashBank2_BASE_IDX … #define regUMCCH3_0_AddrHashBank3 … #define regUMCCH3_0_AddrHashBank3_BASE_IDX … #define regUMCCH3_0_AddrHashBank4 … #define regUMCCH3_0_AddrHashBank4_BASE_IDX … #define regUMCCH3_0_AddrHashBank5 … #define regUMCCH3_0_AddrHashBank5_BASE_IDX … #define regUMCCH3_0_UMC_CONFIG … #define regUMCCH3_0_UMC_CONFIG_BASE_IDX … #define regUMCCH3_0_EccCtrl … #define regUMCCH3_0_EccCtrl_BASE_IDX … #define regUMCCH3_0_UmcLocalCap … #define regUMCCH3_0_UmcLocalCap_BASE_IDX … #define regUMCCH3_0_EccErrCntSel … #define regUMCCH3_0_EccErrCntSel_BASE_IDX … #define regUMCCH3_0_EccErrCnt … #define regUMCCH3_0_EccErrCnt_BASE_IDX … #define regUMCCH3_0_PerfMonCtlClk … #define regUMCCH3_0_PerfMonCtlClk_BASE_IDX … #define regUMCCH3_0_PerfMonCtrClk_Lo … #define regUMCCH3_0_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtrClk_Hi … #define regUMCCH3_0_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH3_0_PerfMonCtl1 … #define regUMCCH3_0_PerfMonCtl1_BASE_IDX … #define regUMCCH3_0_PerfMonCtr1_Lo … #define regUMCCH3_0_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtr1_Hi … #define regUMCCH3_0_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH3_0_PerfMonCtl2 … #define regUMCCH3_0_PerfMonCtl2_BASE_IDX … #define regUMCCH3_0_PerfMonCtr2_Lo … #define regUMCCH3_0_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtr2_Hi … #define regUMCCH3_0_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH3_0_PerfMonCtl3 … #define regUMCCH3_0_PerfMonCtl3_BASE_IDX … #define regUMCCH3_0_PerfMonCtr3_Lo … #define regUMCCH3_0_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtr3_Hi … #define regUMCCH3_0_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH3_0_PerfMonCtl4 … #define regUMCCH3_0_PerfMonCtl4_BASE_IDX … #define regUMCCH3_0_PerfMonCtr4_Lo … #define regUMCCH3_0_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtr4_Hi … #define regUMCCH3_0_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH3_0_PerfMonCtl5 … #define regUMCCH3_0_PerfMonCtl5_BASE_IDX … #define regUMCCH3_0_PerfMonCtr5_Lo … #define regUMCCH3_0_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtr5_Hi … #define regUMCCH3_0_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH3_0_PerfMonCtl6 … #define regUMCCH3_0_PerfMonCtl6_BASE_IDX … #define regUMCCH3_0_PerfMonCtr6_Lo … #define regUMCCH3_0_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtr6_Hi … #define regUMCCH3_0_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH3_0_PerfMonCtl7 … #define regUMCCH3_0_PerfMonCtl7_BASE_IDX … #define regUMCCH3_0_PerfMonCtr7_Lo … #define regUMCCH3_0_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtr7_Hi … #define regUMCCH3_0_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH3_0_PerfMonCtl8 … #define regUMCCH3_0_PerfMonCtl8_BASE_IDX … #define regUMCCH3_0_PerfMonCtr8_Lo … #define regUMCCH3_0_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH3_0_PerfMonCtr8_Hi … #define regUMCCH3_0_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc0_umcch4_umcchdec // base address: 0x150000 #define regUMCCH4_0_BaseAddrCS0 … #define regUMCCH4_0_BaseAddrCS0_BASE_IDX … #define regUMCCH4_0_AddrMaskCS01 … #define regUMCCH4_0_AddrMaskCS01_BASE_IDX … #define regUMCCH4_0_AddrSelCS01 … #define regUMCCH4_0_AddrSelCS01_BASE_IDX … #define regUMCCH4_0_AddrHashBank0 … #define regUMCCH4_0_AddrHashBank0_BASE_IDX … #define regUMCCH4_0_AddrHashBank1 … #define regUMCCH4_0_AddrHashBank1_BASE_IDX … #define regUMCCH4_0_AddrHashBank2 … #define regUMCCH4_0_AddrHashBank2_BASE_IDX … #define regUMCCH4_0_AddrHashBank3 … #define regUMCCH4_0_AddrHashBank3_BASE_IDX … #define regUMCCH4_0_AddrHashBank4 … #define regUMCCH4_0_AddrHashBank4_BASE_IDX … #define regUMCCH4_0_AddrHashBank5 … #define regUMCCH4_0_AddrHashBank5_BASE_IDX … #define regUMCCH4_0_EccErrCntSel … #define regUMCCH4_0_EccErrCntSel_BASE_IDX … #define regUMCCH4_0_EccErrCnt … #define regUMCCH4_0_EccErrCnt_BASE_IDX … #define regUMCCH4_0_PerfMonCtlClk … #define regUMCCH4_0_PerfMonCtlClk_BASE_IDX … #define regUMCCH4_0_PerfMonCtrClk_Lo … #define regUMCCH4_0_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtrClk_Hi … #define regUMCCH4_0_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH4_0_PerfMonCtl1 … #define regUMCCH4_0_PerfMonCtl1_BASE_IDX … #define regUMCCH4_0_PerfMonCtr1_Lo … #define regUMCCH4_0_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtr1_Hi … #define regUMCCH4_0_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH4_0_PerfMonCtl2 … #define regUMCCH4_0_PerfMonCtl2_BASE_IDX … #define regUMCCH4_0_PerfMonCtr2_Lo … #define regUMCCH4_0_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtr2_Hi … #define regUMCCH4_0_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH4_0_PerfMonCtl3 … #define regUMCCH4_0_PerfMonCtl3_BASE_IDX … #define regUMCCH4_0_PerfMonCtr3_Lo … #define regUMCCH4_0_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtr3_Hi … #define regUMCCH4_0_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH4_0_PerfMonCtl4 … #define regUMCCH4_0_PerfMonCtl4_BASE_IDX … #define regUMCCH4_0_PerfMonCtr4_Lo … #define regUMCCH4_0_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtr4_Hi … #define regUMCCH4_0_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH4_0_PerfMonCtl5 … #define regUMCCH4_0_PerfMonCtl5_BASE_IDX … #define regUMCCH4_0_PerfMonCtr5_Lo … #define regUMCCH4_0_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtr5_Hi … #define regUMCCH4_0_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH4_0_PerfMonCtl6 … #define regUMCCH4_0_PerfMonCtl6_BASE_IDX … #define regUMCCH4_0_PerfMonCtr6_Lo … #define regUMCCH4_0_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtr6_Hi … #define regUMCCH4_0_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH4_0_PerfMonCtl7 … #define regUMCCH4_0_PerfMonCtl7_BASE_IDX … #define regUMCCH4_0_PerfMonCtr7_Lo … #define regUMCCH4_0_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtr7_Hi … #define regUMCCH4_0_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH4_0_PerfMonCtl8 … #define regUMCCH4_0_PerfMonCtl8_BASE_IDX … #define regUMCCH4_0_PerfMonCtr8_Lo … #define regUMCCH4_0_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH4_0_PerfMonCtr8_Hi … #define regUMCCH4_0_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc0_umcch5_umcchdec // base address: 0x151000 #define regUMCCH5_0_BaseAddrCS0 … #define regUMCCH5_0_BaseAddrCS0_BASE_IDX … #define regUMCCH5_0_AddrMaskCS01 … #define regUMCCH5_0_AddrMaskCS01_BASE_IDX … #define regUMCCH5_0_AddrSelCS01 … #define regUMCCH5_0_AddrSelCS01_BASE_IDX … #define regUMCCH5_0_AddrHashBank0 … #define regUMCCH5_0_AddrHashBank0_BASE_IDX … #define regUMCCH5_0_AddrHashBank1 … #define regUMCCH5_0_AddrHashBank1_BASE_IDX … #define regUMCCH5_0_AddrHashBank2 … #define regUMCCH5_0_AddrHashBank2_BASE_IDX … #define regUMCCH5_0_AddrHashBank3 … #define regUMCCH5_0_AddrHashBank3_BASE_IDX … #define regUMCCH5_0_AddrHashBank4 … #define regUMCCH5_0_AddrHashBank4_BASE_IDX … #define regUMCCH5_0_AddrHashBank5 … #define regUMCCH5_0_AddrHashBank5_BASE_IDX … #define regUMCCH5_0_EccErrCntSel … #define regUMCCH5_0_EccErrCntSel_BASE_IDX … #define regUMCCH5_0_EccErrCnt … #define regUMCCH5_0_EccErrCnt_BASE_IDX … #define regUMCCH5_0_PerfMonCtlClk … #define regUMCCH5_0_PerfMonCtlClk_BASE_IDX … #define regUMCCH5_0_PerfMonCtrClk_Lo … #define regUMCCH5_0_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtrClk_Hi … #define regUMCCH5_0_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH5_0_PerfMonCtl1 … #define regUMCCH5_0_PerfMonCtl1_BASE_IDX … #define regUMCCH5_0_PerfMonCtr1_Lo … #define regUMCCH5_0_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtr1_Hi … #define regUMCCH5_0_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH5_0_PerfMonCtl2 … #define regUMCCH5_0_PerfMonCtl2_BASE_IDX … #define regUMCCH5_0_PerfMonCtr2_Lo … #define regUMCCH5_0_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtr2_Hi … #define regUMCCH5_0_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH5_0_PerfMonCtl3 … #define regUMCCH5_0_PerfMonCtl3_BASE_IDX … #define regUMCCH5_0_PerfMonCtr3_Lo … #define regUMCCH5_0_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtr3_Hi … #define regUMCCH5_0_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH5_0_PerfMonCtl4 … #define regUMCCH5_0_PerfMonCtl4_BASE_IDX … #define regUMCCH5_0_PerfMonCtr4_Lo … #define regUMCCH5_0_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtr4_Hi … #define regUMCCH5_0_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH5_0_PerfMonCtl5 … #define regUMCCH5_0_PerfMonCtl5_BASE_IDX … #define regUMCCH5_0_PerfMonCtr5_Lo … #define regUMCCH5_0_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtr5_Hi … #define regUMCCH5_0_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH5_0_PerfMonCtl6 … #define regUMCCH5_0_PerfMonCtl6_BASE_IDX … #define regUMCCH5_0_PerfMonCtr6_Lo … #define regUMCCH5_0_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtr6_Hi … #define regUMCCH5_0_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH5_0_PerfMonCtl7 … #define regUMCCH5_0_PerfMonCtl7_BASE_IDX … #define regUMCCH5_0_PerfMonCtr7_Lo … #define regUMCCH5_0_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtr7_Hi … #define regUMCCH5_0_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH5_0_PerfMonCtl8 … #define regUMCCH5_0_PerfMonCtl8_BASE_IDX … #define regUMCCH5_0_PerfMonCtr8_Lo … #define regUMCCH5_0_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH5_0_PerfMonCtr8_Hi … #define regUMCCH5_0_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc0_umcch6_umcchdec // base address: 0x152000 #define regUMCCH6_0_BaseAddrCS0 … #define regUMCCH6_0_BaseAddrCS0_BASE_IDX … #define regUMCCH6_0_AddrMaskCS01 … #define regUMCCH6_0_AddrMaskCS01_BASE_IDX … #define regUMCCH6_0_AddrSelCS01 … #define regUMCCH6_0_AddrSelCS01_BASE_IDX … #define regUMCCH6_0_AddrHashBank0 … #define regUMCCH6_0_AddrHashBank0_BASE_IDX … #define regUMCCH6_0_AddrHashBank1 … #define regUMCCH6_0_AddrHashBank1_BASE_IDX … #define regUMCCH6_0_AddrHashBank2 … #define regUMCCH6_0_AddrHashBank2_BASE_IDX … #define regUMCCH6_0_AddrHashBank3 … #define regUMCCH6_0_AddrHashBank3_BASE_IDX … #define regUMCCH6_0_AddrHashBank4 … #define regUMCCH6_0_AddrHashBank4_BASE_IDX … #define regUMCCH6_0_AddrHashBank5 … #define regUMCCH6_0_AddrHashBank5_BASE_IDX … #define regUMCCH6_0_EccErrCntSel … #define regUMCCH6_0_EccErrCntSel_BASE_IDX … #define regUMCCH6_0_EccErrCnt … #define regUMCCH6_0_EccErrCnt_BASE_IDX … #define regUMCCH6_0_PerfMonCtlClk … #define regUMCCH6_0_PerfMonCtlClk_BASE_IDX … #define regUMCCH6_0_PerfMonCtrClk_Lo … #define regUMCCH6_0_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtrClk_Hi … #define regUMCCH6_0_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH6_0_PerfMonCtl1 … #define regUMCCH6_0_PerfMonCtl1_BASE_IDX … #define regUMCCH6_0_PerfMonCtr1_Lo … #define regUMCCH6_0_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtr1_Hi … #define regUMCCH6_0_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH6_0_PerfMonCtl2 … #define regUMCCH6_0_PerfMonCtl2_BASE_IDX … #define regUMCCH6_0_PerfMonCtr2_Lo … #define regUMCCH6_0_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtr2_Hi … #define regUMCCH6_0_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH6_0_PerfMonCtl3 … #define regUMCCH6_0_PerfMonCtl3_BASE_IDX … #define regUMCCH6_0_PerfMonCtr3_Lo … #define regUMCCH6_0_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtr3_Hi … #define regUMCCH6_0_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH6_0_PerfMonCtl4 … #define regUMCCH6_0_PerfMonCtl4_BASE_IDX … #define regUMCCH6_0_PerfMonCtr4_Lo … #define regUMCCH6_0_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtr4_Hi … #define regUMCCH6_0_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH6_0_PerfMonCtl5 … #define regUMCCH6_0_PerfMonCtl5_BASE_IDX … #define regUMCCH6_0_PerfMonCtr5_Lo … #define regUMCCH6_0_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtr5_Hi … #define regUMCCH6_0_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH6_0_PerfMonCtl6 … #define regUMCCH6_0_PerfMonCtl6_BASE_IDX … #define regUMCCH6_0_PerfMonCtr6_Lo … #define regUMCCH6_0_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtr6_Hi … #define regUMCCH6_0_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH6_0_PerfMonCtl7 … #define regUMCCH6_0_PerfMonCtl7_BASE_IDX … #define regUMCCH6_0_PerfMonCtr7_Lo … #define regUMCCH6_0_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtr7_Hi … #define regUMCCH6_0_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH6_0_PerfMonCtl8 … #define regUMCCH6_0_PerfMonCtl8_BASE_IDX … #define regUMCCH6_0_PerfMonCtr8_Lo … #define regUMCCH6_0_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH6_0_PerfMonCtr8_Hi … #define regUMCCH6_0_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc0_umcch7_umcchdec // base address: 0x153000 #define regUMCCH7_0_BaseAddrCS0 … #define regUMCCH7_0_BaseAddrCS0_BASE_IDX … #define regUMCCH7_0_AddrMaskCS01 … #define regUMCCH7_0_AddrMaskCS01_BASE_IDX … #define regUMCCH7_0_AddrSelCS01 … #define regUMCCH7_0_AddrSelCS01_BASE_IDX … #define regUMCCH7_0_AddrHashBank0 … #define regUMCCH7_0_AddrHashBank0_BASE_IDX … #define regUMCCH7_0_AddrHashBank1 … #define regUMCCH7_0_AddrHashBank1_BASE_IDX … #define regUMCCH7_0_AddrHashBank2 … #define regUMCCH7_0_AddrHashBank2_BASE_IDX … #define regUMCCH7_0_AddrHashBank3 … #define regUMCCH7_0_AddrHashBank3_BASE_IDX … #define regUMCCH7_0_AddrHashBank4 … #define regUMCCH7_0_AddrHashBank4_BASE_IDX … #define regUMCCH7_0_AddrHashBank5 … #define regUMCCH7_0_AddrHashBank5_BASE_IDX … #define regUMCCH7_0_EccErrCntSel … #define regUMCCH7_0_EccErrCntSel_BASE_IDX … #define regUMCCH7_0_EccErrCnt … #define regUMCCH7_0_EccErrCnt_BASE_IDX … #define regUMCCH7_0_PerfMonCtlClk … #define regUMCCH7_0_PerfMonCtlClk_BASE_IDX … #define regUMCCH7_0_PerfMonCtrClk_Lo … #define regUMCCH7_0_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtrClk_Hi … #define regUMCCH7_0_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH7_0_PerfMonCtl1 … #define regUMCCH7_0_PerfMonCtl1_BASE_IDX … #define regUMCCH7_0_PerfMonCtr1_Lo … #define regUMCCH7_0_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtr1_Hi … #define regUMCCH7_0_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH7_0_PerfMonCtl2 … #define regUMCCH7_0_PerfMonCtl2_BASE_IDX … #define regUMCCH7_0_PerfMonCtr2_Lo … #define regUMCCH7_0_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtr2_Hi … #define regUMCCH7_0_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH7_0_PerfMonCtl3 … #define regUMCCH7_0_PerfMonCtl3_BASE_IDX … #define regUMCCH7_0_PerfMonCtr3_Lo … #define regUMCCH7_0_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtr3_Hi … #define regUMCCH7_0_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH7_0_PerfMonCtl4 … #define regUMCCH7_0_PerfMonCtl4_BASE_IDX … #define regUMCCH7_0_PerfMonCtr4_Lo … #define regUMCCH7_0_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtr4_Hi … #define regUMCCH7_0_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH7_0_PerfMonCtl5 … #define regUMCCH7_0_PerfMonCtl5_BASE_IDX … #define regUMCCH7_0_PerfMonCtr5_Lo … #define regUMCCH7_0_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtr5_Hi … #define regUMCCH7_0_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH7_0_PerfMonCtl6 … #define regUMCCH7_0_PerfMonCtl6_BASE_IDX … #define regUMCCH7_0_PerfMonCtr6_Lo … #define regUMCCH7_0_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtr6_Hi … #define regUMCCH7_0_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH7_0_PerfMonCtl7 … #define regUMCCH7_0_PerfMonCtl7_BASE_IDX … #define regUMCCH7_0_PerfMonCtr7_Lo … #define regUMCCH7_0_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtr7_Hi … #define regUMCCH7_0_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH7_0_PerfMonCtl8 … #define regUMCCH7_0_PerfMonCtl8_BASE_IDX … #define regUMCCH7_0_PerfMonCtr8_Lo … #define regUMCCH7_0_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH7_0_PerfMonCtr8_Hi … #define regUMCCH7_0_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc1_umcch0_umcchdec // base address: 0x250000 #define regUMCCH0_1_BaseAddrCS0 … #define regUMCCH0_1_BaseAddrCS0_BASE_IDX … #define regUMCCH0_1_AddrMaskCS01 … #define regUMCCH0_1_AddrMaskCS01_BASE_IDX … #define regUMCCH0_1_AddrSelCS01 … #define regUMCCH0_1_AddrSelCS01_BASE_IDX … #define regUMCCH0_1_AddrHashBank0 … #define regUMCCH0_1_AddrHashBank0_BASE_IDX … #define regUMCCH0_1_AddrHashBank1 … #define regUMCCH0_1_AddrHashBank1_BASE_IDX … #define regUMCCH0_1_AddrHashBank2 … #define regUMCCH0_1_AddrHashBank2_BASE_IDX … #define regUMCCH0_1_AddrHashBank3 … #define regUMCCH0_1_AddrHashBank3_BASE_IDX … #define regUMCCH0_1_AddrHashBank4 … #define regUMCCH0_1_AddrHashBank4_BASE_IDX … #define regUMCCH0_1_AddrHashBank5 … #define regUMCCH0_1_AddrHashBank5_BASE_IDX … #define regUMCCH0_1_EccErrCntSel … #define regUMCCH0_1_EccErrCntSel_BASE_IDX … #define regUMCCH0_1_EccErrCnt … #define regUMCCH0_1_EccErrCnt_BASE_IDX … #define regUMCCH0_1_PerfMonCtlClk … #define regUMCCH0_1_PerfMonCtlClk_BASE_IDX … #define regUMCCH0_1_PerfMonCtrClk_Lo … #define regUMCCH0_1_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtrClk_Hi … #define regUMCCH0_1_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH0_1_PerfMonCtl1 … #define regUMCCH0_1_PerfMonCtl1_BASE_IDX … #define regUMCCH0_1_PerfMonCtr1_Lo … #define regUMCCH0_1_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtr1_Hi … #define regUMCCH0_1_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH0_1_PerfMonCtl2 … #define regUMCCH0_1_PerfMonCtl2_BASE_IDX … #define regUMCCH0_1_PerfMonCtr2_Lo … #define regUMCCH0_1_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtr2_Hi … #define regUMCCH0_1_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH0_1_PerfMonCtl3 … #define regUMCCH0_1_PerfMonCtl3_BASE_IDX … #define regUMCCH0_1_PerfMonCtr3_Lo … #define regUMCCH0_1_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtr3_Hi … #define regUMCCH0_1_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH0_1_PerfMonCtl4 … #define regUMCCH0_1_PerfMonCtl4_BASE_IDX … #define regUMCCH0_1_PerfMonCtr4_Lo … #define regUMCCH0_1_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtr4_Hi … #define regUMCCH0_1_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH0_1_PerfMonCtl5 … #define regUMCCH0_1_PerfMonCtl5_BASE_IDX … #define regUMCCH0_1_PerfMonCtr5_Lo … #define regUMCCH0_1_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtr5_Hi … #define regUMCCH0_1_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH0_1_PerfMonCtl6 … #define regUMCCH0_1_PerfMonCtl6_BASE_IDX … #define regUMCCH0_1_PerfMonCtr6_Lo … #define regUMCCH0_1_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtr6_Hi … #define regUMCCH0_1_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH0_1_PerfMonCtl7 … #define regUMCCH0_1_PerfMonCtl7_BASE_IDX … #define regUMCCH0_1_PerfMonCtr7_Lo … #define regUMCCH0_1_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtr7_Hi … #define regUMCCH0_1_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH0_1_PerfMonCtl8 … #define regUMCCH0_1_PerfMonCtl8_BASE_IDX … #define regUMCCH0_1_PerfMonCtr8_Lo … #define regUMCCH0_1_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH0_1_PerfMonCtr8_Hi … #define regUMCCH0_1_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc1_umcch1_umcchdec // base address: 0x251000 #define regUMCCH1_1_BaseAddrCS0 … #define regUMCCH1_1_BaseAddrCS0_BASE_IDX … #define regUMCCH1_1_AddrMaskCS01 … #define regUMCCH1_1_AddrMaskCS01_BASE_IDX … #define regUMCCH1_1_AddrSelCS01 … #define regUMCCH1_1_AddrSelCS01_BASE_IDX … #define regUMCCH1_1_AddrHashBank0 … #define regUMCCH1_1_AddrHashBank0_BASE_IDX … #define regUMCCH1_1_AddrHashBank1 … #define regUMCCH1_1_AddrHashBank1_BASE_IDX … #define regUMCCH1_1_AddrHashBank2 … #define regUMCCH1_1_AddrHashBank2_BASE_IDX … #define regUMCCH1_1_AddrHashBank3 … #define regUMCCH1_1_AddrHashBank3_BASE_IDX … #define regUMCCH1_1_AddrHashBank4 … #define regUMCCH1_1_AddrHashBank4_BASE_IDX … #define regUMCCH1_1_AddrHashBank5 … #define regUMCCH1_1_AddrHashBank5_BASE_IDX … #define regUMCCH1_1_EccErrCntSel … #define regUMCCH1_1_EccErrCntSel_BASE_IDX … #define regUMCCH1_1_EccErrCnt … #define regUMCCH1_1_EccErrCnt_BASE_IDX … #define regUMCCH1_1_PerfMonCtlClk … #define regUMCCH1_1_PerfMonCtlClk_BASE_IDX … #define regUMCCH1_1_PerfMonCtrClk_Lo … #define regUMCCH1_1_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtrClk_Hi … #define regUMCCH1_1_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH1_1_PerfMonCtl1 … #define regUMCCH1_1_PerfMonCtl1_BASE_IDX … #define regUMCCH1_1_PerfMonCtr1_Lo … #define regUMCCH1_1_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtr1_Hi … #define regUMCCH1_1_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH1_1_PerfMonCtl2 … #define regUMCCH1_1_PerfMonCtl2_BASE_IDX … #define regUMCCH1_1_PerfMonCtr2_Lo … #define regUMCCH1_1_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtr2_Hi … #define regUMCCH1_1_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH1_1_PerfMonCtl3 … #define regUMCCH1_1_PerfMonCtl3_BASE_IDX … #define regUMCCH1_1_PerfMonCtr3_Lo … #define regUMCCH1_1_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtr3_Hi … #define regUMCCH1_1_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH1_1_PerfMonCtl4 … #define regUMCCH1_1_PerfMonCtl4_BASE_IDX … #define regUMCCH1_1_PerfMonCtr4_Lo … #define regUMCCH1_1_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtr4_Hi … #define regUMCCH1_1_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH1_1_PerfMonCtl5 … #define regUMCCH1_1_PerfMonCtl5_BASE_IDX … #define regUMCCH1_1_PerfMonCtr5_Lo … #define regUMCCH1_1_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtr5_Hi … #define regUMCCH1_1_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH1_1_PerfMonCtl6 … #define regUMCCH1_1_PerfMonCtl6_BASE_IDX … #define regUMCCH1_1_PerfMonCtr6_Lo … #define regUMCCH1_1_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtr6_Hi … #define regUMCCH1_1_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH1_1_PerfMonCtl7 … #define regUMCCH1_1_PerfMonCtl7_BASE_IDX … #define regUMCCH1_1_PerfMonCtr7_Lo … #define regUMCCH1_1_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtr7_Hi … #define regUMCCH1_1_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH1_1_PerfMonCtl8 … #define regUMCCH1_1_PerfMonCtl8_BASE_IDX … #define regUMCCH1_1_PerfMonCtr8_Lo … #define regUMCCH1_1_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH1_1_PerfMonCtr8_Hi … #define regUMCCH1_1_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc1_umcch2_umcchdec // base address: 0x252000 #define regUMCCH2_1_BaseAddrCS0 … #define regUMCCH2_1_BaseAddrCS0_BASE_IDX … #define regUMCCH2_1_AddrMaskCS01 … #define regUMCCH2_1_AddrMaskCS01_BASE_IDX … #define regUMCCH2_1_AddrSelCS01 … #define regUMCCH2_1_AddrSelCS01_BASE_IDX … #define regUMCCH2_1_AddrHashBank0 … #define regUMCCH2_1_AddrHashBank0_BASE_IDX … #define regUMCCH2_1_AddrHashBank1 … #define regUMCCH2_1_AddrHashBank1_BASE_IDX … #define regUMCCH2_1_AddrHashBank2 … #define regUMCCH2_1_AddrHashBank2_BASE_IDX … #define regUMCCH2_1_AddrHashBank3 … #define regUMCCH2_1_AddrHashBank3_BASE_IDX … #define regUMCCH2_1_AddrHashBank4 … #define regUMCCH2_1_AddrHashBank4_BASE_IDX … #define regUMCCH2_1_AddrHashBank5 … #define regUMCCH2_1_AddrHashBank5_BASE_IDX … #define regUMCCH2_1_EccErrCntSel … #define regUMCCH2_1_EccErrCntSel_BASE_IDX … #define regUMCCH2_1_EccErrCnt … #define regUMCCH2_1_EccErrCnt_BASE_IDX … #define regUMCCH2_1_PerfMonCtlClk … #define regUMCCH2_1_PerfMonCtlClk_BASE_IDX … #define regUMCCH2_1_PerfMonCtrClk_Lo … #define regUMCCH2_1_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtrClk_Hi … #define regUMCCH2_1_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH2_1_PerfMonCtl1 … #define regUMCCH2_1_PerfMonCtl1_BASE_IDX … #define regUMCCH2_1_PerfMonCtr1_Lo … #define regUMCCH2_1_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtr1_Hi … #define regUMCCH2_1_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH2_1_PerfMonCtl2 … #define regUMCCH2_1_PerfMonCtl2_BASE_IDX … #define regUMCCH2_1_PerfMonCtr2_Lo … #define regUMCCH2_1_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtr2_Hi … #define regUMCCH2_1_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH2_1_PerfMonCtl3 … #define regUMCCH2_1_PerfMonCtl3_BASE_IDX … #define regUMCCH2_1_PerfMonCtr3_Lo … #define regUMCCH2_1_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtr3_Hi … #define regUMCCH2_1_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH2_1_PerfMonCtl4 … #define regUMCCH2_1_PerfMonCtl4_BASE_IDX … #define regUMCCH2_1_PerfMonCtr4_Lo … #define regUMCCH2_1_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtr4_Hi … #define regUMCCH2_1_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH2_1_PerfMonCtl5 … #define regUMCCH2_1_PerfMonCtl5_BASE_IDX … #define regUMCCH2_1_PerfMonCtr5_Lo … #define regUMCCH2_1_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtr5_Hi … #define regUMCCH2_1_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH2_1_PerfMonCtl6 … #define regUMCCH2_1_PerfMonCtl6_BASE_IDX … #define regUMCCH2_1_PerfMonCtr6_Lo … #define regUMCCH2_1_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtr6_Hi … #define regUMCCH2_1_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH2_1_PerfMonCtl7 … #define regUMCCH2_1_PerfMonCtl7_BASE_IDX … #define regUMCCH2_1_PerfMonCtr7_Lo … #define regUMCCH2_1_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtr7_Hi … #define regUMCCH2_1_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH2_1_PerfMonCtl8 … #define regUMCCH2_1_PerfMonCtl8_BASE_IDX … #define regUMCCH2_1_PerfMonCtr8_Lo … #define regUMCCH2_1_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH2_1_PerfMonCtr8_Hi … #define regUMCCH2_1_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc1_umcch3_umcchdec // base address: 0x253000 #define regUMCCH3_1_BaseAddrCS0 … #define regUMCCH3_1_BaseAddrCS0_BASE_IDX … #define regUMCCH3_1_AddrMaskCS01 … #define regUMCCH3_1_AddrMaskCS01_BASE_IDX … #define regUMCCH3_1_AddrSelCS01 … #define regUMCCH3_1_AddrSelCS01_BASE_IDX … #define regUMCCH3_1_AddrHashBank0 … #define regUMCCH3_1_AddrHashBank0_BASE_IDX … #define regUMCCH3_1_AddrHashBank1 … #define regUMCCH3_1_AddrHashBank1_BASE_IDX … #define regUMCCH3_1_AddrHashBank2 … #define regUMCCH3_1_AddrHashBank2_BASE_IDX … #define regUMCCH3_1_AddrHashBank3 … #define regUMCCH3_1_AddrHashBank3_BASE_IDX … #define regUMCCH3_1_AddrHashBank4 … #define regUMCCH3_1_AddrHashBank4_BASE_IDX … #define regUMCCH3_1_AddrHashBank5 … #define regUMCCH3_1_AddrHashBank5_BASE_IDX … #define regUMCCH3_1_EccErrCntSel … #define regUMCCH3_1_EccErrCntSel_BASE_IDX … #define regUMCCH3_1_EccErrCnt … #define regUMCCH3_1_EccErrCnt_BASE_IDX … #define regUMCCH3_1_PerfMonCtlClk … #define regUMCCH3_1_PerfMonCtlClk_BASE_IDX … #define regUMCCH3_1_PerfMonCtrClk_Lo … #define regUMCCH3_1_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtrClk_Hi … #define regUMCCH3_1_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH3_1_PerfMonCtl1 … #define regUMCCH3_1_PerfMonCtl1_BASE_IDX … #define regUMCCH3_1_PerfMonCtr1_Lo … #define regUMCCH3_1_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtr1_Hi … #define regUMCCH3_1_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH3_1_PerfMonCtl2 … #define regUMCCH3_1_PerfMonCtl2_BASE_IDX … #define regUMCCH3_1_PerfMonCtr2_Lo … #define regUMCCH3_1_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtr2_Hi … #define regUMCCH3_1_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH3_1_PerfMonCtl3 … #define regUMCCH3_1_PerfMonCtl3_BASE_IDX … #define regUMCCH3_1_PerfMonCtr3_Lo … #define regUMCCH3_1_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtr3_Hi … #define regUMCCH3_1_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH3_1_PerfMonCtl4 … #define regUMCCH3_1_PerfMonCtl4_BASE_IDX … #define regUMCCH3_1_PerfMonCtr4_Lo … #define regUMCCH3_1_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtr4_Hi … #define regUMCCH3_1_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH3_1_PerfMonCtl5 … #define regUMCCH3_1_PerfMonCtl5_BASE_IDX … #define regUMCCH3_1_PerfMonCtr5_Lo … #define regUMCCH3_1_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtr5_Hi … #define regUMCCH3_1_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH3_1_PerfMonCtl6 … #define regUMCCH3_1_PerfMonCtl6_BASE_IDX … #define regUMCCH3_1_PerfMonCtr6_Lo … #define regUMCCH3_1_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtr6_Hi … #define regUMCCH3_1_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH3_1_PerfMonCtl7 … #define regUMCCH3_1_PerfMonCtl7_BASE_IDX … #define regUMCCH3_1_PerfMonCtr7_Lo … #define regUMCCH3_1_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtr7_Hi … #define regUMCCH3_1_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH3_1_PerfMonCtl8 … #define regUMCCH3_1_PerfMonCtl8_BASE_IDX … #define regUMCCH3_1_PerfMonCtr8_Lo … #define regUMCCH3_1_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH3_1_PerfMonCtr8_Hi … #define regUMCCH3_1_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc1_umcch4_umcchdec // base address: 0x350000 #define regUMCCH4_1_BaseAddrCS0 … #define regUMCCH4_1_BaseAddrCS0_BASE_IDX … #define regUMCCH4_1_AddrMaskCS01 … #define regUMCCH4_1_AddrMaskCS01_BASE_IDX … #define regUMCCH4_1_AddrSelCS01 … #define regUMCCH4_1_AddrSelCS01_BASE_IDX … #define regUMCCH4_1_AddrHashBank0 … #define regUMCCH4_1_AddrHashBank0_BASE_IDX … #define regUMCCH4_1_AddrHashBank1 … #define regUMCCH4_1_AddrHashBank1_BASE_IDX … #define regUMCCH4_1_AddrHashBank2 … #define regUMCCH4_1_AddrHashBank2_BASE_IDX … #define regUMCCH4_1_AddrHashBank3 … #define regUMCCH4_1_AddrHashBank3_BASE_IDX … #define regUMCCH4_1_AddrHashBank4 … #define regUMCCH4_1_AddrHashBank4_BASE_IDX … #define regUMCCH4_1_AddrHashBank5 … #define regUMCCH4_1_AddrHashBank5_BASE_IDX … #define regUMCCH4_1_EccErrCntSel … #define regUMCCH4_1_EccErrCntSel_BASE_IDX … #define regUMCCH4_1_EccErrCnt … #define regUMCCH4_1_EccErrCnt_BASE_IDX … #define regUMCCH4_1_PerfMonCtlClk … #define regUMCCH4_1_PerfMonCtlClk_BASE_IDX … #define regUMCCH4_1_PerfMonCtrClk_Lo … #define regUMCCH4_1_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtrClk_Hi … #define regUMCCH4_1_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH4_1_PerfMonCtl1 … #define regUMCCH4_1_PerfMonCtl1_BASE_IDX … #define regUMCCH4_1_PerfMonCtr1_Lo … #define regUMCCH4_1_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtr1_Hi … #define regUMCCH4_1_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH4_1_PerfMonCtl2 … #define regUMCCH4_1_PerfMonCtl2_BASE_IDX … #define regUMCCH4_1_PerfMonCtr2_Lo … #define regUMCCH4_1_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtr2_Hi … #define regUMCCH4_1_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH4_1_PerfMonCtl3 … #define regUMCCH4_1_PerfMonCtl3_BASE_IDX … #define regUMCCH4_1_PerfMonCtr3_Lo … #define regUMCCH4_1_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtr3_Hi … #define regUMCCH4_1_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH4_1_PerfMonCtl4 … #define regUMCCH4_1_PerfMonCtl4_BASE_IDX … #define regUMCCH4_1_PerfMonCtr4_Lo … #define regUMCCH4_1_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtr4_Hi … #define regUMCCH4_1_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH4_1_PerfMonCtl5 … #define regUMCCH4_1_PerfMonCtl5_BASE_IDX … #define regUMCCH4_1_PerfMonCtr5_Lo … #define regUMCCH4_1_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtr5_Hi … #define regUMCCH4_1_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH4_1_PerfMonCtl6 … #define regUMCCH4_1_PerfMonCtl6_BASE_IDX … #define regUMCCH4_1_PerfMonCtr6_Lo … #define regUMCCH4_1_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtr6_Hi … #define regUMCCH4_1_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH4_1_PerfMonCtl7 … #define regUMCCH4_1_PerfMonCtl7_BASE_IDX … #define regUMCCH4_1_PerfMonCtr7_Lo … #define regUMCCH4_1_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtr7_Hi … #define regUMCCH4_1_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH4_1_PerfMonCtl8 … #define regUMCCH4_1_PerfMonCtl8_BASE_IDX … #define regUMCCH4_1_PerfMonCtr8_Lo … #define regUMCCH4_1_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH4_1_PerfMonCtr8_Hi … #define regUMCCH4_1_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc1_umcch5_umcchdec // base address: 0x351000 #define regUMCCH5_1_BaseAddrCS0 … #define regUMCCH5_1_BaseAddrCS0_BASE_IDX … #define regUMCCH5_1_AddrMaskCS01 … #define regUMCCH5_1_AddrMaskCS01_BASE_IDX … #define regUMCCH5_1_AddrSelCS01 … #define regUMCCH5_1_AddrSelCS01_BASE_IDX … #define regUMCCH5_1_AddrHashBank0 … #define regUMCCH5_1_AddrHashBank0_BASE_IDX … #define regUMCCH5_1_AddrHashBank1 … #define regUMCCH5_1_AddrHashBank1_BASE_IDX … #define regUMCCH5_1_AddrHashBank2 … #define regUMCCH5_1_AddrHashBank2_BASE_IDX … #define regUMCCH5_1_AddrHashBank3 … #define regUMCCH5_1_AddrHashBank3_BASE_IDX … #define regUMCCH5_1_AddrHashBank4 … #define regUMCCH5_1_AddrHashBank4_BASE_IDX … #define regUMCCH5_1_AddrHashBank5 … #define regUMCCH5_1_AddrHashBank5_BASE_IDX … #define regUMCCH5_1_EccErrCntSel … #define regUMCCH5_1_EccErrCntSel_BASE_IDX … #define regUMCCH5_1_EccErrCnt … #define regUMCCH5_1_EccErrCnt_BASE_IDX … #define regUMCCH5_1_PerfMonCtlClk … #define regUMCCH5_1_PerfMonCtlClk_BASE_IDX … #define regUMCCH5_1_PerfMonCtrClk_Lo … #define regUMCCH5_1_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtrClk_Hi … #define regUMCCH5_1_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH5_1_PerfMonCtl1 … #define regUMCCH5_1_PerfMonCtl1_BASE_IDX … #define regUMCCH5_1_PerfMonCtr1_Lo … #define regUMCCH5_1_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtr1_Hi … #define regUMCCH5_1_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH5_1_PerfMonCtl2 … #define regUMCCH5_1_PerfMonCtl2_BASE_IDX … #define regUMCCH5_1_PerfMonCtr2_Lo … #define regUMCCH5_1_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtr2_Hi … #define regUMCCH5_1_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH5_1_PerfMonCtl3 … #define regUMCCH5_1_PerfMonCtl3_BASE_IDX … #define regUMCCH5_1_PerfMonCtr3_Lo … #define regUMCCH5_1_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtr3_Hi … #define regUMCCH5_1_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH5_1_PerfMonCtl4 … #define regUMCCH5_1_PerfMonCtl4_BASE_IDX … #define regUMCCH5_1_PerfMonCtr4_Lo … #define regUMCCH5_1_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtr4_Hi … #define regUMCCH5_1_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH5_1_PerfMonCtl5 … #define regUMCCH5_1_PerfMonCtl5_BASE_IDX … #define regUMCCH5_1_PerfMonCtr5_Lo … #define regUMCCH5_1_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtr5_Hi … #define regUMCCH5_1_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH5_1_PerfMonCtl6 … #define regUMCCH5_1_PerfMonCtl6_BASE_IDX … #define regUMCCH5_1_PerfMonCtr6_Lo … #define regUMCCH5_1_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtr6_Hi … #define regUMCCH5_1_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH5_1_PerfMonCtl7 … #define regUMCCH5_1_PerfMonCtl7_BASE_IDX … #define regUMCCH5_1_PerfMonCtr7_Lo … #define regUMCCH5_1_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtr7_Hi … #define regUMCCH5_1_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH5_1_PerfMonCtl8 … #define regUMCCH5_1_PerfMonCtl8_BASE_IDX … #define regUMCCH5_1_PerfMonCtr8_Lo … #define regUMCCH5_1_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH5_1_PerfMonCtr8_Hi … #define regUMCCH5_1_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc1_umcch6_umcchdec // base address: 0x352000 #define regUMCCH6_1_BaseAddrCS0 … #define regUMCCH6_1_BaseAddrCS0_BASE_IDX … #define regUMCCH6_1_AddrMaskCS01 … #define regUMCCH6_1_AddrMaskCS01_BASE_IDX … #define regUMCCH6_1_AddrSelCS01 … #define regUMCCH6_1_AddrSelCS01_BASE_IDX … #define regUMCCH6_1_AddrHashBank0 … #define regUMCCH6_1_AddrHashBank0_BASE_IDX … #define regUMCCH6_1_AddrHashBank1 … #define regUMCCH6_1_AddrHashBank1_BASE_IDX … #define regUMCCH6_1_AddrHashBank2 … #define regUMCCH6_1_AddrHashBank2_BASE_IDX … #define regUMCCH6_1_AddrHashBank3 … #define regUMCCH6_1_AddrHashBank3_BASE_IDX … #define regUMCCH6_1_AddrHashBank4 … #define regUMCCH6_1_AddrHashBank4_BASE_IDX … #define regUMCCH6_1_AddrHashBank5 … #define regUMCCH6_1_AddrHashBank5_BASE_IDX … #define regUMCCH6_1_EccErrCntSel … #define regUMCCH6_1_EccErrCntSel_BASE_IDX … #define regUMCCH6_1_EccErrCnt … #define regUMCCH6_1_EccErrCnt_BASE_IDX … #define regUMCCH6_1_PerfMonCtlClk … #define regUMCCH6_1_PerfMonCtlClk_BASE_IDX … #define regUMCCH6_1_PerfMonCtrClk_Lo … #define regUMCCH6_1_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtrClk_Hi … #define regUMCCH6_1_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH6_1_PerfMonCtl1 … #define regUMCCH6_1_PerfMonCtl1_BASE_IDX … #define regUMCCH6_1_PerfMonCtr1_Lo … #define regUMCCH6_1_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtr1_Hi … #define regUMCCH6_1_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH6_1_PerfMonCtl2 … #define regUMCCH6_1_PerfMonCtl2_BASE_IDX … #define regUMCCH6_1_PerfMonCtr2_Lo … #define regUMCCH6_1_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtr2_Hi … #define regUMCCH6_1_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH6_1_PerfMonCtl3 … #define regUMCCH6_1_PerfMonCtl3_BASE_IDX … #define regUMCCH6_1_PerfMonCtr3_Lo … #define regUMCCH6_1_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtr3_Hi … #define regUMCCH6_1_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH6_1_PerfMonCtl4 … #define regUMCCH6_1_PerfMonCtl4_BASE_IDX … #define regUMCCH6_1_PerfMonCtr4_Lo … #define regUMCCH6_1_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtr4_Hi … #define regUMCCH6_1_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH6_1_PerfMonCtl5 … #define regUMCCH6_1_PerfMonCtl5_BASE_IDX … #define regUMCCH6_1_PerfMonCtr5_Lo … #define regUMCCH6_1_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtr5_Hi … #define regUMCCH6_1_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH6_1_PerfMonCtl6 … #define regUMCCH6_1_PerfMonCtl6_BASE_IDX … #define regUMCCH6_1_PerfMonCtr6_Lo … #define regUMCCH6_1_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtr6_Hi … #define regUMCCH6_1_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH6_1_PerfMonCtl7 … #define regUMCCH6_1_PerfMonCtl7_BASE_IDX … #define regUMCCH6_1_PerfMonCtr7_Lo … #define regUMCCH6_1_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtr7_Hi … #define regUMCCH6_1_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH6_1_PerfMonCtl8 … #define regUMCCH6_1_PerfMonCtl8_BASE_IDX … #define regUMCCH6_1_PerfMonCtr8_Lo … #define regUMCCH6_1_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH6_1_PerfMonCtr8_Hi … #define regUMCCH6_1_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc1_umcch7_umcchdec // base address: 0x353000 #define regUMCCH7_1_BaseAddrCS0 … #define regUMCCH7_1_BaseAddrCS0_BASE_IDX … #define regUMCCH7_1_AddrMaskCS01 … #define regUMCCH7_1_AddrMaskCS01_BASE_IDX … #define regUMCCH7_1_AddrSelCS01 … #define regUMCCH7_1_AddrSelCS01_BASE_IDX … #define regUMCCH7_1_AddrHashBank0 … #define regUMCCH7_1_AddrHashBank0_BASE_IDX … #define regUMCCH7_1_AddrHashBank1 … #define regUMCCH7_1_AddrHashBank1_BASE_IDX … #define regUMCCH7_1_AddrHashBank2 … #define regUMCCH7_1_AddrHashBank2_BASE_IDX … #define regUMCCH7_1_AddrHashBank3 … #define regUMCCH7_1_AddrHashBank3_BASE_IDX … #define regUMCCH7_1_AddrHashBank4 … #define regUMCCH7_1_AddrHashBank4_BASE_IDX … #define regUMCCH7_1_AddrHashBank5 … #define regUMCCH7_1_AddrHashBank5_BASE_IDX … #define regUMCCH7_1_EccErrCntSel … #define regUMCCH7_1_EccErrCntSel_BASE_IDX … #define regUMCCH7_1_EccErrCnt … #define regUMCCH7_1_EccErrCnt_BASE_IDX … #define regUMCCH7_1_PerfMonCtlClk … #define regUMCCH7_1_PerfMonCtlClk_BASE_IDX … #define regUMCCH7_1_PerfMonCtrClk_Lo … #define regUMCCH7_1_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtrClk_Hi … #define regUMCCH7_1_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH7_1_PerfMonCtl1 … #define regUMCCH7_1_PerfMonCtl1_BASE_IDX … #define regUMCCH7_1_PerfMonCtr1_Lo … #define regUMCCH7_1_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtr1_Hi … #define regUMCCH7_1_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH7_1_PerfMonCtl2 … #define regUMCCH7_1_PerfMonCtl2_BASE_IDX … #define regUMCCH7_1_PerfMonCtr2_Lo … #define regUMCCH7_1_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtr2_Hi … #define regUMCCH7_1_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH7_1_PerfMonCtl3 … #define regUMCCH7_1_PerfMonCtl3_BASE_IDX … #define regUMCCH7_1_PerfMonCtr3_Lo … #define regUMCCH7_1_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtr3_Hi … #define regUMCCH7_1_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH7_1_PerfMonCtl4 … #define regUMCCH7_1_PerfMonCtl4_BASE_IDX … #define regUMCCH7_1_PerfMonCtr4_Lo … #define regUMCCH7_1_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtr4_Hi … #define regUMCCH7_1_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH7_1_PerfMonCtl5 … #define regUMCCH7_1_PerfMonCtl5_BASE_IDX … #define regUMCCH7_1_PerfMonCtr5_Lo … #define regUMCCH7_1_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtr5_Hi … #define regUMCCH7_1_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH7_1_PerfMonCtl6 … #define regUMCCH7_1_PerfMonCtl6_BASE_IDX … #define regUMCCH7_1_PerfMonCtr6_Lo … #define regUMCCH7_1_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtr6_Hi … #define regUMCCH7_1_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH7_1_PerfMonCtl7 … #define regUMCCH7_1_PerfMonCtl7_BASE_IDX … #define regUMCCH7_1_PerfMonCtr7_Lo … #define regUMCCH7_1_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtr7_Hi … #define regUMCCH7_1_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH7_1_PerfMonCtl8 … #define regUMCCH7_1_PerfMonCtl8_BASE_IDX … #define regUMCCH7_1_PerfMonCtr8_Lo … #define regUMCCH7_1_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH7_1_PerfMonCtr8_Hi … #define regUMCCH7_1_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc2_umcch0_umcchdec // base address: 0x450000 #define regUMCCH0_2_BaseAddrCS0 … #define regUMCCH0_2_BaseAddrCS0_BASE_IDX … #define regUMCCH0_2_AddrMaskCS01 … #define regUMCCH0_2_AddrMaskCS01_BASE_IDX … #define regUMCCH0_2_AddrSelCS01 … #define regUMCCH0_2_AddrSelCS01_BASE_IDX … #define regUMCCH0_2_AddrHashBank0 … #define regUMCCH0_2_AddrHashBank0_BASE_IDX … #define regUMCCH0_2_AddrHashBank1 … #define regUMCCH0_2_AddrHashBank1_BASE_IDX … #define regUMCCH0_2_AddrHashBank2 … #define regUMCCH0_2_AddrHashBank2_BASE_IDX … #define regUMCCH0_2_AddrHashBank3 … #define regUMCCH0_2_AddrHashBank3_BASE_IDX … #define regUMCCH0_2_AddrHashBank4 … #define regUMCCH0_2_AddrHashBank4_BASE_IDX … #define regUMCCH0_2_AddrHashBank5 … #define regUMCCH0_2_AddrHashBank5_BASE_IDX … #define regUMCCH0_2_EccErrCntSel … #define regUMCCH0_2_EccErrCntSel_BASE_IDX … #define regUMCCH0_2_EccErrCnt … #define regUMCCH0_2_EccErrCnt_BASE_IDX … #define regUMCCH0_2_PerfMonCtlClk … #define regUMCCH0_2_PerfMonCtlClk_BASE_IDX … #define regUMCCH0_2_PerfMonCtrClk_Lo … #define regUMCCH0_2_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtrClk_Hi … #define regUMCCH0_2_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH0_2_PerfMonCtl1 … #define regUMCCH0_2_PerfMonCtl1_BASE_IDX … #define regUMCCH0_2_PerfMonCtr1_Lo … #define regUMCCH0_2_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtr1_Hi … #define regUMCCH0_2_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH0_2_PerfMonCtl2 … #define regUMCCH0_2_PerfMonCtl2_BASE_IDX … #define regUMCCH0_2_PerfMonCtr2_Lo … #define regUMCCH0_2_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtr2_Hi … #define regUMCCH0_2_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH0_2_PerfMonCtl3 … #define regUMCCH0_2_PerfMonCtl3_BASE_IDX … #define regUMCCH0_2_PerfMonCtr3_Lo … #define regUMCCH0_2_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtr3_Hi … #define regUMCCH0_2_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH0_2_PerfMonCtl4 … #define regUMCCH0_2_PerfMonCtl4_BASE_IDX … #define regUMCCH0_2_PerfMonCtr4_Lo … #define regUMCCH0_2_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtr4_Hi … #define regUMCCH0_2_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH0_2_PerfMonCtl5 … #define regUMCCH0_2_PerfMonCtl5_BASE_IDX … #define regUMCCH0_2_PerfMonCtr5_Lo … #define regUMCCH0_2_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtr5_Hi … #define regUMCCH0_2_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH0_2_PerfMonCtl6 … #define regUMCCH0_2_PerfMonCtl6_BASE_IDX … #define regUMCCH0_2_PerfMonCtr6_Lo … #define regUMCCH0_2_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtr6_Hi … #define regUMCCH0_2_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH0_2_PerfMonCtl7 … #define regUMCCH0_2_PerfMonCtl7_BASE_IDX … #define regUMCCH0_2_PerfMonCtr7_Lo … #define regUMCCH0_2_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtr7_Hi … #define regUMCCH0_2_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH0_2_PerfMonCtl8 … #define regUMCCH0_2_PerfMonCtl8_BASE_IDX … #define regUMCCH0_2_PerfMonCtr8_Lo … #define regUMCCH0_2_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH0_2_PerfMonCtr8_Hi … #define regUMCCH0_2_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc2_umcch1_umcchdec // base address: 0x451000 #define regUMCCH1_2_BaseAddrCS0 … #define regUMCCH1_2_BaseAddrCS0_BASE_IDX … #define regUMCCH1_2_AddrMaskCS01 … #define regUMCCH1_2_AddrMaskCS01_BASE_IDX … #define regUMCCH1_2_AddrSelCS01 … #define regUMCCH1_2_AddrSelCS01_BASE_IDX … #define regUMCCH1_2_AddrHashBank0 … #define regUMCCH1_2_AddrHashBank0_BASE_IDX … #define regUMCCH1_2_AddrHashBank1 … #define regUMCCH1_2_AddrHashBank1_BASE_IDX … #define regUMCCH1_2_AddrHashBank2 … #define regUMCCH1_2_AddrHashBank2_BASE_IDX … #define regUMCCH1_2_AddrHashBank3 … #define regUMCCH1_2_AddrHashBank3_BASE_IDX … #define regUMCCH1_2_AddrHashBank4 … #define regUMCCH1_2_AddrHashBank4_BASE_IDX … #define regUMCCH1_2_AddrHashBank5 … #define regUMCCH1_2_AddrHashBank5_BASE_IDX … #define regUMCCH1_2_EccErrCntSel … #define regUMCCH1_2_EccErrCntSel_BASE_IDX … #define regUMCCH1_2_EccErrCnt … #define regUMCCH1_2_EccErrCnt_BASE_IDX … #define regUMCCH1_2_PerfMonCtlClk … #define regUMCCH1_2_PerfMonCtlClk_BASE_IDX … #define regUMCCH1_2_PerfMonCtrClk_Lo … #define regUMCCH1_2_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtrClk_Hi … #define regUMCCH1_2_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH1_2_PerfMonCtl1 … #define regUMCCH1_2_PerfMonCtl1_BASE_IDX … #define regUMCCH1_2_PerfMonCtr1_Lo … #define regUMCCH1_2_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtr1_Hi … #define regUMCCH1_2_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH1_2_PerfMonCtl2 … #define regUMCCH1_2_PerfMonCtl2_BASE_IDX … #define regUMCCH1_2_PerfMonCtr2_Lo … #define regUMCCH1_2_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtr2_Hi … #define regUMCCH1_2_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH1_2_PerfMonCtl3 … #define regUMCCH1_2_PerfMonCtl3_BASE_IDX … #define regUMCCH1_2_PerfMonCtr3_Lo … #define regUMCCH1_2_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtr3_Hi … #define regUMCCH1_2_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH1_2_PerfMonCtl4 … #define regUMCCH1_2_PerfMonCtl4_BASE_IDX … #define regUMCCH1_2_PerfMonCtr4_Lo … #define regUMCCH1_2_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtr4_Hi … #define regUMCCH1_2_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH1_2_PerfMonCtl5 … #define regUMCCH1_2_PerfMonCtl5_BASE_IDX … #define regUMCCH1_2_PerfMonCtr5_Lo … #define regUMCCH1_2_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtr5_Hi … #define regUMCCH1_2_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH1_2_PerfMonCtl6 … #define regUMCCH1_2_PerfMonCtl6_BASE_IDX … #define regUMCCH1_2_PerfMonCtr6_Lo … #define regUMCCH1_2_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtr6_Hi … #define regUMCCH1_2_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH1_2_PerfMonCtl7 … #define regUMCCH1_2_PerfMonCtl7_BASE_IDX … #define regUMCCH1_2_PerfMonCtr7_Lo … #define regUMCCH1_2_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtr7_Hi … #define regUMCCH1_2_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH1_2_PerfMonCtl8 … #define regUMCCH1_2_PerfMonCtl8_BASE_IDX … #define regUMCCH1_2_PerfMonCtr8_Lo … #define regUMCCH1_2_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH1_2_PerfMonCtr8_Hi … #define regUMCCH1_2_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc2_umcch2_umcchdec // base address: 0x452000 #define regUMCCH2_2_BaseAddrCS0 … #define regUMCCH2_2_BaseAddrCS0_BASE_IDX … #define regUMCCH2_2_AddrMaskCS01 … #define regUMCCH2_2_AddrMaskCS01_BASE_IDX … #define regUMCCH2_2_AddrSelCS01 … #define regUMCCH2_2_AddrSelCS01_BASE_IDX … #define regUMCCH2_2_AddrHashBank0 … #define regUMCCH2_2_AddrHashBank0_BASE_IDX … #define regUMCCH2_2_AddrHashBank1 … #define regUMCCH2_2_AddrHashBank1_BASE_IDX … #define regUMCCH2_2_AddrHashBank2 … #define regUMCCH2_2_AddrHashBank2_BASE_IDX … #define regUMCCH2_2_AddrHashBank3 … #define regUMCCH2_2_AddrHashBank3_BASE_IDX … #define regUMCCH2_2_AddrHashBank4 … #define regUMCCH2_2_AddrHashBank4_BASE_IDX … #define regUMCCH2_2_AddrHashBank5 … #define regUMCCH2_2_AddrHashBank5_BASE_IDX … #define regUMCCH2_2_EccErrCntSel … #define regUMCCH2_2_EccErrCntSel_BASE_IDX … #define regUMCCH2_2_EccErrCnt … #define regUMCCH2_2_EccErrCnt_BASE_IDX … #define regUMCCH2_2_PerfMonCtlClk … #define regUMCCH2_2_PerfMonCtlClk_BASE_IDX … #define regUMCCH2_2_PerfMonCtrClk_Lo … #define regUMCCH2_2_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtrClk_Hi … #define regUMCCH2_2_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH2_2_PerfMonCtl1 … #define regUMCCH2_2_PerfMonCtl1_BASE_IDX … #define regUMCCH2_2_PerfMonCtr1_Lo … #define regUMCCH2_2_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtr1_Hi … #define regUMCCH2_2_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH2_2_PerfMonCtl2 … #define regUMCCH2_2_PerfMonCtl2_BASE_IDX … #define regUMCCH2_2_PerfMonCtr2_Lo … #define regUMCCH2_2_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtr2_Hi … #define regUMCCH2_2_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH2_2_PerfMonCtl3 … #define regUMCCH2_2_PerfMonCtl3_BASE_IDX … #define regUMCCH2_2_PerfMonCtr3_Lo … #define regUMCCH2_2_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtr3_Hi … #define regUMCCH2_2_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH2_2_PerfMonCtl4 … #define regUMCCH2_2_PerfMonCtl4_BASE_IDX … #define regUMCCH2_2_PerfMonCtr4_Lo … #define regUMCCH2_2_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtr4_Hi … #define regUMCCH2_2_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH2_2_PerfMonCtl5 … #define regUMCCH2_2_PerfMonCtl5_BASE_IDX … #define regUMCCH2_2_PerfMonCtr5_Lo … #define regUMCCH2_2_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtr5_Hi … #define regUMCCH2_2_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH2_2_PerfMonCtl6 … #define regUMCCH2_2_PerfMonCtl6_BASE_IDX … #define regUMCCH2_2_PerfMonCtr6_Lo … #define regUMCCH2_2_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtr6_Hi … #define regUMCCH2_2_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH2_2_PerfMonCtl7 … #define regUMCCH2_2_PerfMonCtl7_BASE_IDX … #define regUMCCH2_2_PerfMonCtr7_Lo … #define regUMCCH2_2_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtr7_Hi … #define regUMCCH2_2_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH2_2_PerfMonCtl8 … #define regUMCCH2_2_PerfMonCtl8_BASE_IDX … #define regUMCCH2_2_PerfMonCtr8_Lo … #define regUMCCH2_2_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH2_2_PerfMonCtr8_Hi … #define regUMCCH2_2_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc2_umcch3_umcchdec // base address: 0x453000 #define regUMCCH3_2_BaseAddrCS0 … #define regUMCCH3_2_BaseAddrCS0_BASE_IDX … #define regUMCCH3_2_AddrMaskCS01 … #define regUMCCH3_2_AddrMaskCS01_BASE_IDX … #define regUMCCH3_2_AddrSelCS01 … #define regUMCCH3_2_AddrSelCS01_BASE_IDX … #define regUMCCH3_2_AddrHashBank0 … #define regUMCCH3_2_AddrHashBank0_BASE_IDX … #define regUMCCH3_2_AddrHashBank1 … #define regUMCCH3_2_AddrHashBank1_BASE_IDX … #define regUMCCH3_2_AddrHashBank2 … #define regUMCCH3_2_AddrHashBank2_BASE_IDX … #define regUMCCH3_2_AddrHashBank3 … #define regUMCCH3_2_AddrHashBank3_BASE_IDX … #define regUMCCH3_2_AddrHashBank4 … #define regUMCCH3_2_AddrHashBank4_BASE_IDX … #define regUMCCH3_2_AddrHashBank5 … #define regUMCCH3_2_AddrHashBank5_BASE_IDX … #define regUMCCH3_2_EccErrCntSel … #define regUMCCH3_2_EccErrCntSel_BASE_IDX … #define regUMCCH3_2_EccErrCnt … #define regUMCCH3_2_EccErrCnt_BASE_IDX … #define regUMCCH3_2_PerfMonCtlClk … #define regUMCCH3_2_PerfMonCtlClk_BASE_IDX … #define regUMCCH3_2_PerfMonCtrClk_Lo … #define regUMCCH3_2_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtrClk_Hi … #define regUMCCH3_2_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH3_2_PerfMonCtl1 … #define regUMCCH3_2_PerfMonCtl1_BASE_IDX … #define regUMCCH3_2_PerfMonCtr1_Lo … #define regUMCCH3_2_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtr1_Hi … #define regUMCCH3_2_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH3_2_PerfMonCtl2 … #define regUMCCH3_2_PerfMonCtl2_BASE_IDX … #define regUMCCH3_2_PerfMonCtr2_Lo … #define regUMCCH3_2_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtr2_Hi … #define regUMCCH3_2_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH3_2_PerfMonCtl3 … #define regUMCCH3_2_PerfMonCtl3_BASE_IDX … #define regUMCCH3_2_PerfMonCtr3_Lo … #define regUMCCH3_2_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtr3_Hi … #define regUMCCH3_2_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH3_2_PerfMonCtl4 … #define regUMCCH3_2_PerfMonCtl4_BASE_IDX … #define regUMCCH3_2_PerfMonCtr4_Lo … #define regUMCCH3_2_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtr4_Hi … #define regUMCCH3_2_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH3_2_PerfMonCtl5 … #define regUMCCH3_2_PerfMonCtl5_BASE_IDX … #define regUMCCH3_2_PerfMonCtr5_Lo … #define regUMCCH3_2_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtr5_Hi … #define regUMCCH3_2_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH3_2_PerfMonCtl6 … #define regUMCCH3_2_PerfMonCtl6_BASE_IDX … #define regUMCCH3_2_PerfMonCtr6_Lo … #define regUMCCH3_2_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtr6_Hi … #define regUMCCH3_2_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH3_2_PerfMonCtl7 … #define regUMCCH3_2_PerfMonCtl7_BASE_IDX … #define regUMCCH3_2_PerfMonCtr7_Lo … #define regUMCCH3_2_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtr7_Hi … #define regUMCCH3_2_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH3_2_PerfMonCtl8 … #define regUMCCH3_2_PerfMonCtl8_BASE_IDX … #define regUMCCH3_2_PerfMonCtr8_Lo … #define regUMCCH3_2_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH3_2_PerfMonCtr8_Hi … #define regUMCCH3_2_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc2_umcch4_umcchdec // base address: 0x550000 #define regUMCCH4_2_BaseAddrCS0 … #define regUMCCH4_2_BaseAddrCS0_BASE_IDX … #define regUMCCH4_2_AddrMaskCS01 … #define regUMCCH4_2_AddrMaskCS01_BASE_IDX … #define regUMCCH4_2_AddrSelCS01 … #define regUMCCH4_2_AddrSelCS01_BASE_IDX … #define regUMCCH4_2_AddrHashBank0 … #define regUMCCH4_2_AddrHashBank0_BASE_IDX … #define regUMCCH4_2_AddrHashBank1 … #define regUMCCH4_2_AddrHashBank1_BASE_IDX … #define regUMCCH4_2_AddrHashBank2 … #define regUMCCH4_2_AddrHashBank2_BASE_IDX … #define regUMCCH4_2_AddrHashBank3 … #define regUMCCH4_2_AddrHashBank3_BASE_IDX … #define regUMCCH4_2_AddrHashBank4 … #define regUMCCH4_2_AddrHashBank4_BASE_IDX … #define regUMCCH4_2_AddrHashBank5 … #define regUMCCH4_2_AddrHashBank5_BASE_IDX … #define regUMCCH4_2_EccErrCntSel … #define regUMCCH4_2_EccErrCntSel_BASE_IDX … #define regUMCCH4_2_EccErrCnt … #define regUMCCH4_2_EccErrCnt_BASE_IDX … #define regUMCCH4_2_PerfMonCtlClk … #define regUMCCH4_2_PerfMonCtlClk_BASE_IDX … #define regUMCCH4_2_PerfMonCtrClk_Lo … #define regUMCCH4_2_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtrClk_Hi … #define regUMCCH4_2_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH4_2_PerfMonCtl1 … #define regUMCCH4_2_PerfMonCtl1_BASE_IDX … #define regUMCCH4_2_PerfMonCtr1_Lo … #define regUMCCH4_2_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtr1_Hi … #define regUMCCH4_2_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH4_2_PerfMonCtl2 … #define regUMCCH4_2_PerfMonCtl2_BASE_IDX … #define regUMCCH4_2_PerfMonCtr2_Lo … #define regUMCCH4_2_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtr2_Hi … #define regUMCCH4_2_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH4_2_PerfMonCtl3 … #define regUMCCH4_2_PerfMonCtl3_BASE_IDX … #define regUMCCH4_2_PerfMonCtr3_Lo … #define regUMCCH4_2_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtr3_Hi … #define regUMCCH4_2_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH4_2_PerfMonCtl4 … #define regUMCCH4_2_PerfMonCtl4_BASE_IDX … #define regUMCCH4_2_PerfMonCtr4_Lo … #define regUMCCH4_2_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtr4_Hi … #define regUMCCH4_2_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH4_2_PerfMonCtl5 … #define regUMCCH4_2_PerfMonCtl5_BASE_IDX … #define regUMCCH4_2_PerfMonCtr5_Lo … #define regUMCCH4_2_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtr5_Hi … #define regUMCCH4_2_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH4_2_PerfMonCtl6 … #define regUMCCH4_2_PerfMonCtl6_BASE_IDX … #define regUMCCH4_2_PerfMonCtr6_Lo … #define regUMCCH4_2_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtr6_Hi … #define regUMCCH4_2_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH4_2_PerfMonCtl7 … #define regUMCCH4_2_PerfMonCtl7_BASE_IDX … #define regUMCCH4_2_PerfMonCtr7_Lo … #define regUMCCH4_2_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtr7_Hi … #define regUMCCH4_2_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH4_2_PerfMonCtl8 … #define regUMCCH4_2_PerfMonCtl8_BASE_IDX … #define regUMCCH4_2_PerfMonCtr8_Lo … #define regUMCCH4_2_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH4_2_PerfMonCtr8_Hi … #define regUMCCH4_2_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc2_umcch5_umcchdec // base address: 0x551000 #define regUMCCH5_2_BaseAddrCS0 … #define regUMCCH5_2_BaseAddrCS0_BASE_IDX … #define regUMCCH5_2_AddrMaskCS01 … #define regUMCCH5_2_AddrMaskCS01_BASE_IDX … #define regUMCCH5_2_AddrSelCS01 … #define regUMCCH5_2_AddrSelCS01_BASE_IDX … #define regUMCCH5_2_AddrHashBank0 … #define regUMCCH5_2_AddrHashBank0_BASE_IDX … #define regUMCCH5_2_AddrHashBank1 … #define regUMCCH5_2_AddrHashBank1_BASE_IDX … #define regUMCCH5_2_AddrHashBank2 … #define regUMCCH5_2_AddrHashBank2_BASE_IDX … #define regUMCCH5_2_AddrHashBank3 … #define regUMCCH5_2_AddrHashBank3_BASE_IDX … #define regUMCCH5_2_AddrHashBank4 … #define regUMCCH5_2_AddrHashBank4_BASE_IDX … #define regUMCCH5_2_AddrHashBank5 … #define regUMCCH5_2_AddrHashBank5_BASE_IDX … #define regUMCCH5_2_EccErrCntSel … #define regUMCCH5_2_EccErrCntSel_BASE_IDX … #define regUMCCH5_2_EccErrCnt … #define regUMCCH5_2_EccErrCnt_BASE_IDX … #define regUMCCH5_2_PerfMonCtlClk … #define regUMCCH5_2_PerfMonCtlClk_BASE_IDX … #define regUMCCH5_2_PerfMonCtrClk_Lo … #define regUMCCH5_2_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtrClk_Hi … #define regUMCCH5_2_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH5_2_PerfMonCtl1 … #define regUMCCH5_2_PerfMonCtl1_BASE_IDX … #define regUMCCH5_2_PerfMonCtr1_Lo … #define regUMCCH5_2_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtr1_Hi … #define regUMCCH5_2_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH5_2_PerfMonCtl2 … #define regUMCCH5_2_PerfMonCtl2_BASE_IDX … #define regUMCCH5_2_PerfMonCtr2_Lo … #define regUMCCH5_2_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtr2_Hi … #define regUMCCH5_2_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH5_2_PerfMonCtl3 … #define regUMCCH5_2_PerfMonCtl3_BASE_IDX … #define regUMCCH5_2_PerfMonCtr3_Lo … #define regUMCCH5_2_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtr3_Hi … #define regUMCCH5_2_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH5_2_PerfMonCtl4 … #define regUMCCH5_2_PerfMonCtl4_BASE_IDX … #define regUMCCH5_2_PerfMonCtr4_Lo … #define regUMCCH5_2_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtr4_Hi … #define regUMCCH5_2_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH5_2_PerfMonCtl5 … #define regUMCCH5_2_PerfMonCtl5_BASE_IDX … #define regUMCCH5_2_PerfMonCtr5_Lo … #define regUMCCH5_2_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtr5_Hi … #define regUMCCH5_2_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH5_2_PerfMonCtl6 … #define regUMCCH5_2_PerfMonCtl6_BASE_IDX … #define regUMCCH5_2_PerfMonCtr6_Lo … #define regUMCCH5_2_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtr6_Hi … #define regUMCCH5_2_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH5_2_PerfMonCtl7 … #define regUMCCH5_2_PerfMonCtl7_BASE_IDX … #define regUMCCH5_2_PerfMonCtr7_Lo … #define regUMCCH5_2_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtr7_Hi … #define regUMCCH5_2_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH5_2_PerfMonCtl8 … #define regUMCCH5_2_PerfMonCtl8_BASE_IDX … #define regUMCCH5_2_PerfMonCtr8_Lo … #define regUMCCH5_2_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH5_2_PerfMonCtr8_Hi … #define regUMCCH5_2_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc2_umcch6_umcchdec // base address: 0x552000 #define regUMCCH6_2_BaseAddrCS0 … #define regUMCCH6_2_BaseAddrCS0_BASE_IDX … #define regUMCCH6_2_AddrMaskCS01 … #define regUMCCH6_2_AddrMaskCS01_BASE_IDX … #define regUMCCH6_2_AddrSelCS01 … #define regUMCCH6_2_AddrSelCS01_BASE_IDX … #define regUMCCH6_2_AddrHashBank0 … #define regUMCCH6_2_AddrHashBank0_BASE_IDX … #define regUMCCH6_2_AddrHashBank1 … #define regUMCCH6_2_AddrHashBank1_BASE_IDX … #define regUMCCH6_2_AddrHashBank2 … #define regUMCCH6_2_AddrHashBank2_BASE_IDX … #define regUMCCH6_2_AddrHashBank3 … #define regUMCCH6_2_AddrHashBank3_BASE_IDX … #define regUMCCH6_2_AddrHashBank4 … #define regUMCCH6_2_AddrHashBank4_BASE_IDX … #define regUMCCH6_2_AddrHashBank5 … #define regUMCCH6_2_AddrHashBank5_BASE_IDX … #define regUMCCH6_2_EccErrCntSel … #define regUMCCH6_2_EccErrCntSel_BASE_IDX … #define regUMCCH6_2_EccErrCnt … #define regUMCCH6_2_EccErrCnt_BASE_IDX … #define regUMCCH6_2_PerfMonCtlClk … #define regUMCCH6_2_PerfMonCtlClk_BASE_IDX … #define regUMCCH6_2_PerfMonCtrClk_Lo … #define regUMCCH6_2_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtrClk_Hi … #define regUMCCH6_2_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH6_2_PerfMonCtl1 … #define regUMCCH6_2_PerfMonCtl1_BASE_IDX … #define regUMCCH6_2_PerfMonCtr1_Lo … #define regUMCCH6_2_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtr1_Hi … #define regUMCCH6_2_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH6_2_PerfMonCtl2 … #define regUMCCH6_2_PerfMonCtl2_BASE_IDX … #define regUMCCH6_2_PerfMonCtr2_Lo … #define regUMCCH6_2_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtr2_Hi … #define regUMCCH6_2_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH6_2_PerfMonCtl3 … #define regUMCCH6_2_PerfMonCtl3_BASE_IDX … #define regUMCCH6_2_PerfMonCtr3_Lo … #define regUMCCH6_2_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtr3_Hi … #define regUMCCH6_2_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH6_2_PerfMonCtl4 … #define regUMCCH6_2_PerfMonCtl4_BASE_IDX … #define regUMCCH6_2_PerfMonCtr4_Lo … #define regUMCCH6_2_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtr4_Hi … #define regUMCCH6_2_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH6_2_PerfMonCtl5 … #define regUMCCH6_2_PerfMonCtl5_BASE_IDX … #define regUMCCH6_2_PerfMonCtr5_Lo … #define regUMCCH6_2_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtr5_Hi … #define regUMCCH6_2_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH6_2_PerfMonCtl6 … #define regUMCCH6_2_PerfMonCtl6_BASE_IDX … #define regUMCCH6_2_PerfMonCtr6_Lo … #define regUMCCH6_2_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtr6_Hi … #define regUMCCH6_2_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH6_2_PerfMonCtl7 … #define regUMCCH6_2_PerfMonCtl7_BASE_IDX … #define regUMCCH6_2_PerfMonCtr7_Lo … #define regUMCCH6_2_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtr7_Hi … #define regUMCCH6_2_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH6_2_PerfMonCtl8 … #define regUMCCH6_2_PerfMonCtl8_BASE_IDX … #define regUMCCH6_2_PerfMonCtr8_Lo … #define regUMCCH6_2_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH6_2_PerfMonCtr8_Hi … #define regUMCCH6_2_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc2_umcch7_umcchdec // base address: 0x553000 #define regUMCCH7_2_BaseAddrCS0 … #define regUMCCH7_2_BaseAddrCS0_BASE_IDX … #define regUMCCH7_2_AddrMaskCS01 … #define regUMCCH7_2_AddrMaskCS01_BASE_IDX … #define regUMCCH7_2_AddrSelCS01 … #define regUMCCH7_2_AddrSelCS01_BASE_IDX … #define regUMCCH7_2_AddrHashBank0 … #define regUMCCH7_2_AddrHashBank0_BASE_IDX … #define regUMCCH7_2_AddrHashBank1 … #define regUMCCH7_2_AddrHashBank1_BASE_IDX … #define regUMCCH7_2_AddrHashBank2 … #define regUMCCH7_2_AddrHashBank2_BASE_IDX … #define regUMCCH7_2_AddrHashBank3 … #define regUMCCH7_2_AddrHashBank3_BASE_IDX … #define regUMCCH7_2_AddrHashBank4 … #define regUMCCH7_2_AddrHashBank4_BASE_IDX … #define regUMCCH7_2_AddrHashBank5 … #define regUMCCH7_2_AddrHashBank5_BASE_IDX … #define regUMCCH7_2_EccErrCntSel … #define regUMCCH7_2_EccErrCntSel_BASE_IDX … #define regUMCCH7_2_EccErrCnt … #define regUMCCH7_2_EccErrCnt_BASE_IDX … #define regUMCCH7_2_PerfMonCtlClk … #define regUMCCH7_2_PerfMonCtlClk_BASE_IDX … #define regUMCCH7_2_PerfMonCtrClk_Lo … #define regUMCCH7_2_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtrClk_Hi … #define regUMCCH7_2_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH7_2_PerfMonCtl1 … #define regUMCCH7_2_PerfMonCtl1_BASE_IDX … #define regUMCCH7_2_PerfMonCtr1_Lo … #define regUMCCH7_2_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtr1_Hi … #define regUMCCH7_2_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH7_2_PerfMonCtl2 … #define regUMCCH7_2_PerfMonCtl2_BASE_IDX … #define regUMCCH7_2_PerfMonCtr2_Lo … #define regUMCCH7_2_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtr2_Hi … #define regUMCCH7_2_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH7_2_PerfMonCtl3 … #define regUMCCH7_2_PerfMonCtl3_BASE_IDX … #define regUMCCH7_2_PerfMonCtr3_Lo … #define regUMCCH7_2_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtr3_Hi … #define regUMCCH7_2_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH7_2_PerfMonCtl4 … #define regUMCCH7_2_PerfMonCtl4_BASE_IDX … #define regUMCCH7_2_PerfMonCtr4_Lo … #define regUMCCH7_2_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtr4_Hi … #define regUMCCH7_2_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH7_2_PerfMonCtl5 … #define regUMCCH7_2_PerfMonCtl5_BASE_IDX … #define regUMCCH7_2_PerfMonCtr5_Lo … #define regUMCCH7_2_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtr5_Hi … #define regUMCCH7_2_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH7_2_PerfMonCtl6 … #define regUMCCH7_2_PerfMonCtl6_BASE_IDX … #define regUMCCH7_2_PerfMonCtr6_Lo … #define regUMCCH7_2_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtr6_Hi … #define regUMCCH7_2_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH7_2_PerfMonCtl7 … #define regUMCCH7_2_PerfMonCtl7_BASE_IDX … #define regUMCCH7_2_PerfMonCtr7_Lo … #define regUMCCH7_2_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtr7_Hi … #define regUMCCH7_2_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH7_2_PerfMonCtl8 … #define regUMCCH7_2_PerfMonCtl8_BASE_IDX … #define regUMCCH7_2_PerfMonCtr8_Lo … #define regUMCCH7_2_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH7_2_PerfMonCtr8_Hi … #define regUMCCH7_2_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc3_umcch0_umcchdec // base address: 0x650000 #define regUMCCH0_3_BaseAddrCS0 … #define regUMCCH0_3_BaseAddrCS0_BASE_IDX … #define regUMCCH0_3_AddrMaskCS01 … #define regUMCCH0_3_AddrMaskCS01_BASE_IDX … #define regUMCCH0_3_AddrSelCS01 … #define regUMCCH0_3_AddrSelCS01_BASE_IDX … #define regUMCCH0_3_AddrHashBank0 … #define regUMCCH0_3_AddrHashBank0_BASE_IDX … #define regUMCCH0_3_AddrHashBank1 … #define regUMCCH0_3_AddrHashBank1_BASE_IDX … #define regUMCCH0_3_AddrHashBank2 … #define regUMCCH0_3_AddrHashBank2_BASE_IDX … #define regUMCCH0_3_AddrHashBank3 … #define regUMCCH0_3_AddrHashBank3_BASE_IDX … #define regUMCCH0_3_AddrHashBank4 … #define regUMCCH0_3_AddrHashBank4_BASE_IDX … #define regUMCCH0_3_AddrHashBank5 … #define regUMCCH0_3_AddrHashBank5_BASE_IDX … #define regUMCCH0_3_EccErrCntSel … #define regUMCCH0_3_EccErrCntSel_BASE_IDX … #define regUMCCH0_3_EccErrCnt … #define regUMCCH0_3_EccErrCnt_BASE_IDX … #define regUMCCH0_3_PerfMonCtlClk … #define regUMCCH0_3_PerfMonCtlClk_BASE_IDX … #define regUMCCH0_3_PerfMonCtrClk_Lo … #define regUMCCH0_3_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtrClk_Hi … #define regUMCCH0_3_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH0_3_PerfMonCtl1 … #define regUMCCH0_3_PerfMonCtl1_BASE_IDX … #define regUMCCH0_3_PerfMonCtr1_Lo … #define regUMCCH0_3_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtr1_Hi … #define regUMCCH0_3_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH0_3_PerfMonCtl2 … #define regUMCCH0_3_PerfMonCtl2_BASE_IDX … #define regUMCCH0_3_PerfMonCtr2_Lo … #define regUMCCH0_3_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtr2_Hi … #define regUMCCH0_3_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH0_3_PerfMonCtl3 … #define regUMCCH0_3_PerfMonCtl3_BASE_IDX … #define regUMCCH0_3_PerfMonCtr3_Lo … #define regUMCCH0_3_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtr3_Hi … #define regUMCCH0_3_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH0_3_PerfMonCtl4 … #define regUMCCH0_3_PerfMonCtl4_BASE_IDX … #define regUMCCH0_3_PerfMonCtr4_Lo … #define regUMCCH0_3_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtr4_Hi … #define regUMCCH0_3_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH0_3_PerfMonCtl5 … #define regUMCCH0_3_PerfMonCtl5_BASE_IDX … #define regUMCCH0_3_PerfMonCtr5_Lo … #define regUMCCH0_3_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtr5_Hi … #define regUMCCH0_3_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH0_3_PerfMonCtl6 … #define regUMCCH0_3_PerfMonCtl6_BASE_IDX … #define regUMCCH0_3_PerfMonCtr6_Lo … #define regUMCCH0_3_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtr6_Hi … #define regUMCCH0_3_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH0_3_PerfMonCtl7 … #define regUMCCH0_3_PerfMonCtl7_BASE_IDX … #define regUMCCH0_3_PerfMonCtr7_Lo … #define regUMCCH0_3_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtr7_Hi … #define regUMCCH0_3_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH0_3_PerfMonCtl8 … #define regUMCCH0_3_PerfMonCtl8_BASE_IDX … #define regUMCCH0_3_PerfMonCtr8_Lo … #define regUMCCH0_3_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH0_3_PerfMonCtr8_Hi … #define regUMCCH0_3_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc3_umcch1_umcchdec // base address: 0x651000 #define regUMCCH1_3_BaseAddrCS0 … #define regUMCCH1_3_BaseAddrCS0_BASE_IDX … #define regUMCCH1_3_AddrMaskCS01 … #define regUMCCH1_3_AddrMaskCS01_BASE_IDX … #define regUMCCH1_3_AddrSelCS01 … #define regUMCCH1_3_AddrSelCS01_BASE_IDX … #define regUMCCH1_3_AddrHashBank0 … #define regUMCCH1_3_AddrHashBank0_BASE_IDX … #define regUMCCH1_3_AddrHashBank1 … #define regUMCCH1_3_AddrHashBank1_BASE_IDX … #define regUMCCH1_3_AddrHashBank2 … #define regUMCCH1_3_AddrHashBank2_BASE_IDX … #define regUMCCH1_3_AddrHashBank3 … #define regUMCCH1_3_AddrHashBank3_BASE_IDX … #define regUMCCH1_3_AddrHashBank4 … #define regUMCCH1_3_AddrHashBank4_BASE_IDX … #define regUMCCH1_3_AddrHashBank5 … #define regUMCCH1_3_AddrHashBank5_BASE_IDX … #define regUMCCH1_3_EccErrCntSel … #define regUMCCH1_3_EccErrCntSel_BASE_IDX … #define regUMCCH1_3_EccErrCnt … #define regUMCCH1_3_EccErrCnt_BASE_IDX … #define regUMCCH1_3_PerfMonCtlClk … #define regUMCCH1_3_PerfMonCtlClk_BASE_IDX … #define regUMCCH1_3_PerfMonCtrClk_Lo … #define regUMCCH1_3_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtrClk_Hi … #define regUMCCH1_3_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH1_3_PerfMonCtl1 … #define regUMCCH1_3_PerfMonCtl1_BASE_IDX … #define regUMCCH1_3_PerfMonCtr1_Lo … #define regUMCCH1_3_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtr1_Hi … #define regUMCCH1_3_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH1_3_PerfMonCtl2 … #define regUMCCH1_3_PerfMonCtl2_BASE_IDX … #define regUMCCH1_3_PerfMonCtr2_Lo … #define regUMCCH1_3_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtr2_Hi … #define regUMCCH1_3_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH1_3_PerfMonCtl3 … #define regUMCCH1_3_PerfMonCtl3_BASE_IDX … #define regUMCCH1_3_PerfMonCtr3_Lo … #define regUMCCH1_3_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtr3_Hi … #define regUMCCH1_3_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH1_3_PerfMonCtl4 … #define regUMCCH1_3_PerfMonCtl4_BASE_IDX … #define regUMCCH1_3_PerfMonCtr4_Lo … #define regUMCCH1_3_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtr4_Hi … #define regUMCCH1_3_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH1_3_PerfMonCtl5 … #define regUMCCH1_3_PerfMonCtl5_BASE_IDX … #define regUMCCH1_3_PerfMonCtr5_Lo … #define regUMCCH1_3_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtr5_Hi … #define regUMCCH1_3_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH1_3_PerfMonCtl6 … #define regUMCCH1_3_PerfMonCtl6_BASE_IDX … #define regUMCCH1_3_PerfMonCtr6_Lo … #define regUMCCH1_3_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtr6_Hi … #define regUMCCH1_3_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH1_3_PerfMonCtl7 … #define regUMCCH1_3_PerfMonCtl7_BASE_IDX … #define regUMCCH1_3_PerfMonCtr7_Lo … #define regUMCCH1_3_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtr7_Hi … #define regUMCCH1_3_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH1_3_PerfMonCtl8 … #define regUMCCH1_3_PerfMonCtl8_BASE_IDX … #define regUMCCH1_3_PerfMonCtr8_Lo … #define regUMCCH1_3_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH1_3_PerfMonCtr8_Hi … #define regUMCCH1_3_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc3_umcch2_umcchdec // base address: 0x652000 #define regUMCCH2_3_BaseAddrCS0 … #define regUMCCH2_3_BaseAddrCS0_BASE_IDX … #define regUMCCH2_3_AddrMaskCS01 … #define regUMCCH2_3_AddrMaskCS01_BASE_IDX … #define regUMCCH2_3_AddrSelCS01 … #define regUMCCH2_3_AddrSelCS01_BASE_IDX … #define regUMCCH2_3_AddrHashBank0 … #define regUMCCH2_3_AddrHashBank0_BASE_IDX … #define regUMCCH2_3_AddrHashBank1 … #define regUMCCH2_3_AddrHashBank1_BASE_IDX … #define regUMCCH2_3_AddrHashBank2 … #define regUMCCH2_3_AddrHashBank2_BASE_IDX … #define regUMCCH2_3_AddrHashBank3 … #define regUMCCH2_3_AddrHashBank3_BASE_IDX … #define regUMCCH2_3_AddrHashBank4 … #define regUMCCH2_3_AddrHashBank4_BASE_IDX … #define regUMCCH2_3_AddrHashBank5 … #define regUMCCH2_3_AddrHashBank5_BASE_IDX … #define regUMCCH2_3_EccErrCntSel … #define regUMCCH2_3_EccErrCntSel_BASE_IDX … #define regUMCCH2_3_EccErrCnt … #define regUMCCH2_3_EccErrCnt_BASE_IDX … #define regUMCCH2_3_PerfMonCtlClk … #define regUMCCH2_3_PerfMonCtlClk_BASE_IDX … #define regUMCCH2_3_PerfMonCtrClk_Lo … #define regUMCCH2_3_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtrClk_Hi … #define regUMCCH2_3_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH2_3_PerfMonCtl1 … #define regUMCCH2_3_PerfMonCtl1_BASE_IDX … #define regUMCCH2_3_PerfMonCtr1_Lo … #define regUMCCH2_3_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtr1_Hi … #define regUMCCH2_3_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH2_3_PerfMonCtl2 … #define regUMCCH2_3_PerfMonCtl2_BASE_IDX … #define regUMCCH2_3_PerfMonCtr2_Lo … #define regUMCCH2_3_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtr2_Hi … #define regUMCCH2_3_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH2_3_PerfMonCtl3 … #define regUMCCH2_3_PerfMonCtl3_BASE_IDX … #define regUMCCH2_3_PerfMonCtr3_Lo … #define regUMCCH2_3_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtr3_Hi … #define regUMCCH2_3_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH2_3_PerfMonCtl4 … #define regUMCCH2_3_PerfMonCtl4_BASE_IDX … #define regUMCCH2_3_PerfMonCtr4_Lo … #define regUMCCH2_3_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtr4_Hi … #define regUMCCH2_3_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH2_3_PerfMonCtl5 … #define regUMCCH2_3_PerfMonCtl5_BASE_IDX … #define regUMCCH2_3_PerfMonCtr5_Lo … #define regUMCCH2_3_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtr5_Hi … #define regUMCCH2_3_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH2_3_PerfMonCtl6 … #define regUMCCH2_3_PerfMonCtl6_BASE_IDX … #define regUMCCH2_3_PerfMonCtr6_Lo … #define regUMCCH2_3_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtr6_Hi … #define regUMCCH2_3_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH2_3_PerfMonCtl7 … #define regUMCCH2_3_PerfMonCtl7_BASE_IDX … #define regUMCCH2_3_PerfMonCtr7_Lo … #define regUMCCH2_3_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtr7_Hi … #define regUMCCH2_3_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH2_3_PerfMonCtl8 … #define regUMCCH2_3_PerfMonCtl8_BASE_IDX … #define regUMCCH2_3_PerfMonCtr8_Lo … #define regUMCCH2_3_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH2_3_PerfMonCtr8_Hi … #define regUMCCH2_3_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc3_umcch3_umcchdec // base address: 0x653000 #define regUMCCH3_3_BaseAddrCS0 … #define regUMCCH3_3_BaseAddrCS0_BASE_IDX … #define regUMCCH3_3_AddrMaskCS01 … #define regUMCCH3_3_AddrMaskCS01_BASE_IDX … #define regUMCCH3_3_AddrSelCS01 … #define regUMCCH3_3_AddrSelCS01_BASE_IDX … #define regUMCCH3_3_AddrHashBank0 … #define regUMCCH3_3_AddrHashBank0_BASE_IDX … #define regUMCCH3_3_AddrHashBank1 … #define regUMCCH3_3_AddrHashBank1_BASE_IDX … #define regUMCCH3_3_AddrHashBank2 … #define regUMCCH3_3_AddrHashBank2_BASE_IDX … #define regUMCCH3_3_AddrHashBank3 … #define regUMCCH3_3_AddrHashBank3_BASE_IDX … #define regUMCCH3_3_AddrHashBank4 … #define regUMCCH3_3_AddrHashBank4_BASE_IDX … #define regUMCCH3_3_AddrHashBank5 … #define regUMCCH3_3_AddrHashBank5_BASE_IDX … #define regUMCCH3_3_EccErrCntSel … #define regUMCCH3_3_EccErrCntSel_BASE_IDX … #define regUMCCH3_3_EccErrCnt … #define regUMCCH3_3_EccErrCnt_BASE_IDX … #define regUMCCH3_3_PerfMonCtlClk … #define regUMCCH3_3_PerfMonCtlClk_BASE_IDX … #define regUMCCH3_3_PerfMonCtrClk_Lo … #define regUMCCH3_3_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtrClk_Hi … #define regUMCCH3_3_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH3_3_PerfMonCtl1 … #define regUMCCH3_3_PerfMonCtl1_BASE_IDX … #define regUMCCH3_3_PerfMonCtr1_Lo … #define regUMCCH3_3_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtr1_Hi … #define regUMCCH3_3_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH3_3_PerfMonCtl2 … #define regUMCCH3_3_PerfMonCtl2_BASE_IDX … #define regUMCCH3_3_PerfMonCtr2_Lo … #define regUMCCH3_3_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtr2_Hi … #define regUMCCH3_3_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH3_3_PerfMonCtl3 … #define regUMCCH3_3_PerfMonCtl3_BASE_IDX … #define regUMCCH3_3_PerfMonCtr3_Lo … #define regUMCCH3_3_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtr3_Hi … #define regUMCCH3_3_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH3_3_PerfMonCtl4 … #define regUMCCH3_3_PerfMonCtl4_BASE_IDX … #define regUMCCH3_3_PerfMonCtr4_Lo … #define regUMCCH3_3_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtr4_Hi … #define regUMCCH3_3_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH3_3_PerfMonCtl5 … #define regUMCCH3_3_PerfMonCtl5_BASE_IDX … #define regUMCCH3_3_PerfMonCtr5_Lo … #define regUMCCH3_3_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtr5_Hi … #define regUMCCH3_3_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH3_3_PerfMonCtl6 … #define regUMCCH3_3_PerfMonCtl6_BASE_IDX … #define regUMCCH3_3_PerfMonCtr6_Lo … #define regUMCCH3_3_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtr6_Hi … #define regUMCCH3_3_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH3_3_PerfMonCtl7 … #define regUMCCH3_3_PerfMonCtl7_BASE_IDX … #define regUMCCH3_3_PerfMonCtr7_Lo … #define regUMCCH3_3_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtr7_Hi … #define regUMCCH3_3_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH3_3_PerfMonCtl8 … #define regUMCCH3_3_PerfMonCtl8_BASE_IDX … #define regUMCCH3_3_PerfMonCtr8_Lo … #define regUMCCH3_3_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH3_3_PerfMonCtr8_Hi … #define regUMCCH3_3_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc3_umcch4_umcchdec // base address: 0x750000 #define regUMCCH4_3_BaseAddrCS0 … #define regUMCCH4_3_BaseAddrCS0_BASE_IDX … #define regUMCCH4_3_AddrMaskCS01 … #define regUMCCH4_3_AddrMaskCS01_BASE_IDX … #define regUMCCH4_3_AddrSelCS01 … #define regUMCCH4_3_AddrSelCS01_BASE_IDX … #define regUMCCH4_3_AddrHashBank0 … #define regUMCCH4_3_AddrHashBank0_BASE_IDX … #define regUMCCH4_3_AddrHashBank1 … #define regUMCCH4_3_AddrHashBank1_BASE_IDX … #define regUMCCH4_3_AddrHashBank2 … #define regUMCCH4_3_AddrHashBank2_BASE_IDX … #define regUMCCH4_3_AddrHashBank3 … #define regUMCCH4_3_AddrHashBank3_BASE_IDX … #define regUMCCH4_3_AddrHashBank4 … #define regUMCCH4_3_AddrHashBank4_BASE_IDX … #define regUMCCH4_3_AddrHashBank5 … #define regUMCCH4_3_AddrHashBank5_BASE_IDX … #define regUMCCH4_3_EccErrCntSel … #define regUMCCH4_3_EccErrCntSel_BASE_IDX … #define regUMCCH4_3_EccErrCnt … #define regUMCCH4_3_EccErrCnt_BASE_IDX … #define regUMCCH4_3_PerfMonCtlClk … #define regUMCCH4_3_PerfMonCtlClk_BASE_IDX … #define regUMCCH4_3_PerfMonCtrClk_Lo … #define regUMCCH4_3_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtrClk_Hi … #define regUMCCH4_3_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH4_3_PerfMonCtl1 … #define regUMCCH4_3_PerfMonCtl1_BASE_IDX … #define regUMCCH4_3_PerfMonCtr1_Lo … #define regUMCCH4_3_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtr1_Hi … #define regUMCCH4_3_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH4_3_PerfMonCtl2 … #define regUMCCH4_3_PerfMonCtl2_BASE_IDX … #define regUMCCH4_3_PerfMonCtr2_Lo … #define regUMCCH4_3_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtr2_Hi … #define regUMCCH4_3_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH4_3_PerfMonCtl3 … #define regUMCCH4_3_PerfMonCtl3_BASE_IDX … #define regUMCCH4_3_PerfMonCtr3_Lo … #define regUMCCH4_3_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtr3_Hi … #define regUMCCH4_3_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH4_3_PerfMonCtl4 … #define regUMCCH4_3_PerfMonCtl4_BASE_IDX … #define regUMCCH4_3_PerfMonCtr4_Lo … #define regUMCCH4_3_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtr4_Hi … #define regUMCCH4_3_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH4_3_PerfMonCtl5 … #define regUMCCH4_3_PerfMonCtl5_BASE_IDX … #define regUMCCH4_3_PerfMonCtr5_Lo … #define regUMCCH4_3_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtr5_Hi … #define regUMCCH4_3_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH4_3_PerfMonCtl6 … #define regUMCCH4_3_PerfMonCtl6_BASE_IDX … #define regUMCCH4_3_PerfMonCtr6_Lo … #define regUMCCH4_3_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtr6_Hi … #define regUMCCH4_3_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH4_3_PerfMonCtl7 … #define regUMCCH4_3_PerfMonCtl7_BASE_IDX … #define regUMCCH4_3_PerfMonCtr7_Lo … #define regUMCCH4_3_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtr7_Hi … #define regUMCCH4_3_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH4_3_PerfMonCtl8 … #define regUMCCH4_3_PerfMonCtl8_BASE_IDX … #define regUMCCH4_3_PerfMonCtr8_Lo … #define regUMCCH4_3_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH4_3_PerfMonCtr8_Hi … #define regUMCCH4_3_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc3_umcch5_umcchdec // base address: 0x751000 #define regUMCCH5_3_BaseAddrCS0 … #define regUMCCH5_3_BaseAddrCS0_BASE_IDX … #define regUMCCH5_3_AddrMaskCS01 … #define regUMCCH5_3_AddrMaskCS01_BASE_IDX … #define regUMCCH5_3_AddrSelCS01 … #define regUMCCH5_3_AddrSelCS01_BASE_IDX … #define regUMCCH5_3_AddrHashBank0 … #define regUMCCH5_3_AddrHashBank0_BASE_IDX … #define regUMCCH5_3_AddrHashBank1 … #define regUMCCH5_3_AddrHashBank1_BASE_IDX … #define regUMCCH5_3_AddrHashBank2 … #define regUMCCH5_3_AddrHashBank2_BASE_IDX … #define regUMCCH5_3_AddrHashBank3 … #define regUMCCH5_3_AddrHashBank3_BASE_IDX … #define regUMCCH5_3_AddrHashBank4 … #define regUMCCH5_3_AddrHashBank4_BASE_IDX … #define regUMCCH5_3_AddrHashBank5 … #define regUMCCH5_3_AddrHashBank5_BASE_IDX … #define regUMCCH5_3_EccErrCntSel … #define regUMCCH5_3_EccErrCntSel_BASE_IDX … #define regUMCCH5_3_EccErrCnt … #define regUMCCH5_3_EccErrCnt_BASE_IDX … #define regUMCCH5_3_PerfMonCtlClk … #define regUMCCH5_3_PerfMonCtlClk_BASE_IDX … #define regUMCCH5_3_PerfMonCtrClk_Lo … #define regUMCCH5_3_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtrClk_Hi … #define regUMCCH5_3_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH5_3_PerfMonCtl1 … #define regUMCCH5_3_PerfMonCtl1_BASE_IDX … #define regUMCCH5_3_PerfMonCtr1_Lo … #define regUMCCH5_3_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtr1_Hi … #define regUMCCH5_3_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH5_3_PerfMonCtl2 … #define regUMCCH5_3_PerfMonCtl2_BASE_IDX … #define regUMCCH5_3_PerfMonCtr2_Lo … #define regUMCCH5_3_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtr2_Hi … #define regUMCCH5_3_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH5_3_PerfMonCtl3 … #define regUMCCH5_3_PerfMonCtl3_BASE_IDX … #define regUMCCH5_3_PerfMonCtr3_Lo … #define regUMCCH5_3_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtr3_Hi … #define regUMCCH5_3_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH5_3_PerfMonCtl4 … #define regUMCCH5_3_PerfMonCtl4_BASE_IDX … #define regUMCCH5_3_PerfMonCtr4_Lo … #define regUMCCH5_3_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtr4_Hi … #define regUMCCH5_3_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH5_3_PerfMonCtl5 … #define regUMCCH5_3_PerfMonCtl5_BASE_IDX … #define regUMCCH5_3_PerfMonCtr5_Lo … #define regUMCCH5_3_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtr5_Hi … #define regUMCCH5_3_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH5_3_PerfMonCtl6 … #define regUMCCH5_3_PerfMonCtl6_BASE_IDX … #define regUMCCH5_3_PerfMonCtr6_Lo … #define regUMCCH5_3_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtr6_Hi … #define regUMCCH5_3_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH5_3_PerfMonCtl7 … #define regUMCCH5_3_PerfMonCtl7_BASE_IDX … #define regUMCCH5_3_PerfMonCtr7_Lo … #define regUMCCH5_3_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtr7_Hi … #define regUMCCH5_3_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH5_3_PerfMonCtl8 … #define regUMCCH5_3_PerfMonCtl8_BASE_IDX … #define regUMCCH5_3_PerfMonCtr8_Lo … #define regUMCCH5_3_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH5_3_PerfMonCtr8_Hi … #define regUMCCH5_3_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc3_umcch6_umcchdec // base address: 0x752000 #define regUMCCH6_3_BaseAddrCS0 … #define regUMCCH6_3_BaseAddrCS0_BASE_IDX … #define regUMCCH6_3_AddrMaskCS01 … #define regUMCCH6_3_AddrMaskCS01_BASE_IDX … #define regUMCCH6_3_AddrSelCS01 … #define regUMCCH6_3_AddrSelCS01_BASE_IDX … #define regUMCCH6_3_AddrHashBank0 … #define regUMCCH6_3_AddrHashBank0_BASE_IDX … #define regUMCCH6_3_AddrHashBank1 … #define regUMCCH6_3_AddrHashBank1_BASE_IDX … #define regUMCCH6_3_AddrHashBank2 … #define regUMCCH6_3_AddrHashBank2_BASE_IDX … #define regUMCCH6_3_AddrHashBank3 … #define regUMCCH6_3_AddrHashBank3_BASE_IDX … #define regUMCCH6_3_AddrHashBank4 … #define regUMCCH6_3_AddrHashBank4_BASE_IDX … #define regUMCCH6_3_AddrHashBank5 … #define regUMCCH6_3_AddrHashBank5_BASE_IDX … #define regUMCCH6_3_EccErrCntSel … #define regUMCCH6_3_EccErrCntSel_BASE_IDX … #define regUMCCH6_3_EccErrCnt … #define regUMCCH6_3_EccErrCnt_BASE_IDX … #define regUMCCH6_3_PerfMonCtlClk … #define regUMCCH6_3_PerfMonCtlClk_BASE_IDX … #define regUMCCH6_3_PerfMonCtrClk_Lo … #define regUMCCH6_3_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtrClk_Hi … #define regUMCCH6_3_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH6_3_PerfMonCtl1 … #define regUMCCH6_3_PerfMonCtl1_BASE_IDX … #define regUMCCH6_3_PerfMonCtr1_Lo … #define regUMCCH6_3_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtr1_Hi … #define regUMCCH6_3_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH6_3_PerfMonCtl2 … #define regUMCCH6_3_PerfMonCtl2_BASE_IDX … #define regUMCCH6_3_PerfMonCtr2_Lo … #define regUMCCH6_3_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtr2_Hi … #define regUMCCH6_3_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH6_3_PerfMonCtl3 … #define regUMCCH6_3_PerfMonCtl3_BASE_IDX … #define regUMCCH6_3_PerfMonCtr3_Lo … #define regUMCCH6_3_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtr3_Hi … #define regUMCCH6_3_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH6_3_PerfMonCtl4 … #define regUMCCH6_3_PerfMonCtl4_BASE_IDX … #define regUMCCH6_3_PerfMonCtr4_Lo … #define regUMCCH6_3_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtr4_Hi … #define regUMCCH6_3_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH6_3_PerfMonCtl5 … #define regUMCCH6_3_PerfMonCtl5_BASE_IDX … #define regUMCCH6_3_PerfMonCtr5_Lo … #define regUMCCH6_3_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtr5_Hi … #define regUMCCH6_3_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH6_3_PerfMonCtl6 … #define regUMCCH6_3_PerfMonCtl6_BASE_IDX … #define regUMCCH6_3_PerfMonCtr6_Lo … #define regUMCCH6_3_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtr6_Hi … #define regUMCCH6_3_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH6_3_PerfMonCtl7 … #define regUMCCH6_3_PerfMonCtl7_BASE_IDX … #define regUMCCH6_3_PerfMonCtr7_Lo … #define regUMCCH6_3_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtr7_Hi … #define regUMCCH6_3_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH6_3_PerfMonCtl8 … #define regUMCCH6_3_PerfMonCtl8_BASE_IDX … #define regUMCCH6_3_PerfMonCtr8_Lo … #define regUMCCH6_3_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH6_3_PerfMonCtr8_Hi … #define regUMCCH6_3_PerfMonCtr8_Hi_BASE_IDX … // addressBlock: umc_w_phy_umc3_umcch7_umcchdec // base address: 0x753000 #define regUMCCH7_3_BaseAddrCS0 … #define regUMCCH7_3_BaseAddrCS0_BASE_IDX … #define regUMCCH7_3_AddrMaskCS01 … #define regUMCCH7_3_AddrMaskCS01_BASE_IDX … #define regUMCCH7_3_AddrSelCS01 … #define regUMCCH7_3_AddrSelCS01_BASE_IDX … #define regUMCCH7_3_AddrHashBank0 … #define regUMCCH7_3_AddrHashBank0_BASE_IDX … #define regUMCCH7_3_AddrHashBank1 … #define regUMCCH7_3_AddrHashBank1_BASE_IDX … #define regUMCCH7_3_AddrHashBank2 … #define regUMCCH7_3_AddrHashBank2_BASE_IDX … #define regUMCCH7_3_AddrHashBank3 … #define regUMCCH7_3_AddrHashBank3_BASE_IDX … #define regUMCCH7_3_AddrHashBank4 … #define regUMCCH7_3_AddrHashBank4_BASE_IDX … #define regUMCCH7_3_AddrHashBank5 … #define regUMCCH7_3_AddrHashBank5_BASE_IDX … #define regUMCCH7_3_EccErrCntSel … #define regUMCCH7_3_EccErrCntSel_BASE_IDX … #define regUMCCH7_3_EccErrCnt … #define regUMCCH7_3_EccErrCnt_BASE_IDX … #define regUMCCH7_3_PerfMonCtlClk … #define regUMCCH7_3_PerfMonCtlClk_BASE_IDX … #define regUMCCH7_3_PerfMonCtrClk_Lo … #define regUMCCH7_3_PerfMonCtrClk_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtrClk_Hi … #define regUMCCH7_3_PerfMonCtrClk_Hi_BASE_IDX … #define regUMCCH7_3_PerfMonCtl1 … #define regUMCCH7_3_PerfMonCtl1_BASE_IDX … #define regUMCCH7_3_PerfMonCtr1_Lo … #define regUMCCH7_3_PerfMonCtr1_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtr1_Hi … #define regUMCCH7_3_PerfMonCtr1_Hi_BASE_IDX … #define regUMCCH7_3_PerfMonCtl2 … #define regUMCCH7_3_PerfMonCtl2_BASE_IDX … #define regUMCCH7_3_PerfMonCtr2_Lo … #define regUMCCH7_3_PerfMonCtr2_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtr2_Hi … #define regUMCCH7_3_PerfMonCtr2_Hi_BASE_IDX … #define regUMCCH7_3_PerfMonCtl3 … #define regUMCCH7_3_PerfMonCtl3_BASE_IDX … #define regUMCCH7_3_PerfMonCtr3_Lo … #define regUMCCH7_3_PerfMonCtr3_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtr3_Hi … #define regUMCCH7_3_PerfMonCtr3_Hi_BASE_IDX … #define regUMCCH7_3_PerfMonCtl4 … #define regUMCCH7_3_PerfMonCtl4_BASE_IDX … #define regUMCCH7_3_PerfMonCtr4_Lo … #define regUMCCH7_3_PerfMonCtr4_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtr4_Hi … #define regUMCCH7_3_PerfMonCtr4_Hi_BASE_IDX … #define regUMCCH7_3_PerfMonCtl5 … #define regUMCCH7_3_PerfMonCtl5_BASE_IDX … #define regUMCCH7_3_PerfMonCtr5_Lo … #define regUMCCH7_3_PerfMonCtr5_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtr5_Hi … #define regUMCCH7_3_PerfMonCtr5_Hi_BASE_IDX … #define regUMCCH7_3_PerfMonCtl6 … #define regUMCCH7_3_PerfMonCtl6_BASE_IDX … #define regUMCCH7_3_PerfMonCtr6_Lo … #define regUMCCH7_3_PerfMonCtr6_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtr6_Hi … #define regUMCCH7_3_PerfMonCtr6_Hi_BASE_IDX … #define regUMCCH7_3_PerfMonCtl7 … #define regUMCCH7_3_PerfMonCtl7_BASE_IDX … #define regUMCCH7_3_PerfMonCtr7_Lo … #define regUMCCH7_3_PerfMonCtr7_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtr7_Hi … #define regUMCCH7_3_PerfMonCtr7_Hi_BASE_IDX … #define regUMCCH7_3_PerfMonCtl8 … #define regUMCCH7_3_PerfMonCtl8_BASE_IDX … #define regUMCCH7_3_PerfMonCtr8_Lo … #define regUMCCH7_3_PerfMonCtr8_Lo_BASE_IDX … #define regUMCCH7_3_PerfMonCtr8_Hi … #define regUMCCH7_3_PerfMonCtr8_Hi_BASE_IDX … #endif
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