/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef CIK_H #define CIK_H #define MC_SEQ_MISC0__MT__MASK … #define MC_SEQ_MISC0__MT__GDDR1 … #define MC_SEQ_MISC0__MT__DDR2 … #define MC_SEQ_MISC0__MT__GDDR3 … #define MC_SEQ_MISC0__MT__GDDR4 … #define MC_SEQ_MISC0__MT__GDDR5 … #define MC_SEQ_MISC0__MT__HBM … #define MC_SEQ_MISC0__MT__DDR3 … #define CP_ME_TABLE_SIZE … /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ #define CRTC0_REGISTER_OFFSET … #define CRTC1_REGISTER_OFFSET … #define CRTC2_REGISTER_OFFSET … #define CRTC3_REGISTER_OFFSET … #define CRTC4_REGISTER_OFFSET … #define CRTC5_REGISTER_OFFSET … /* hpd instance offsets */ #define HPD0_REGISTER_OFFSET … #define HPD1_REGISTER_OFFSET … #define HPD2_REGISTER_OFFSET … #define HPD3_REGISTER_OFFSET … #define HPD4_REGISTER_OFFSET … #define HPD5_REGISTER_OFFSET … #define BONAIRE_GB_ADDR_CONFIG_GOLDEN … #define HAWAII_GB_ADDR_CONFIG_GOLDEN … #define PIPEID(x) … #define MEID(x) … #define VMID(x) … #define QUEUEID(x) … #define mmCC_DRM_ID_STRAPS … #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK … #define mmCHUB_CONTROL … #define BYPASS_VM … #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU … #define mmGRPH_LUT_10BIT_BYPASS_CONTROL … #define LUT_10BIT_BYPASS_EN … #define CURSOR_MONO … #define CURSOR_24_1 … #define CURSOR_24_8_PRE_MULT … #define CURSOR_24_8_UNPRE_MULT … #define CURSOR_URGENT_ALWAYS … #define CURSOR_URGENT_1_8 … #define CURSOR_URGENT_1_4 … #define CURSOR_URGENT_3_8 … #define CURSOR_URGENT_1_2 … #define GRPH_DEPTH_8BPP … #define GRPH_DEPTH_16BPP … #define GRPH_DEPTH_32BPP … /* 8 BPP */ #define GRPH_FORMAT_INDEXED … /* 16 BPP */ #define GRPH_FORMAT_ARGB1555 … #define GRPH_FORMAT_ARGB565 … #define GRPH_FORMAT_ARGB4444 … #define GRPH_FORMAT_AI88 … #define GRPH_FORMAT_MONO16 … #define GRPH_FORMAT_BGRA5551 … /* 32 BPP */ #define GRPH_FORMAT_ARGB8888 … #define GRPH_FORMAT_ARGB2101010 … #define GRPH_FORMAT_32BPP_DIG … #define GRPH_FORMAT_8B_ARGB2101010 … #define GRPH_FORMAT_BGRA1010102 … #define GRPH_FORMAT_8B_BGRA1010102 … #define GRPH_FORMAT_RGB111110 … #define GRPH_FORMAT_BGR101111 … #define ADDR_SURF_MACRO_TILE_ASPECT_1 … #define ADDR_SURF_MACRO_TILE_ASPECT_2 … #define ADDR_SURF_MACRO_TILE_ASPECT_4 … #define ADDR_SURF_MACRO_TILE_ASPECT_8 … #define GRPH_ARRAY_LINEAR_GENERAL … #define GRPH_ARRAY_LINEAR_ALIGNED … #define GRPH_ARRAY_1D_TILED_THIN1 … #define GRPH_ARRAY_2D_TILED_THIN1 … #define DISPLAY_MICRO_TILING … #define THIN_MICRO_TILING … #define DEPTH_MICRO_TILING … #define ROTATED_MICRO_TILING … #define GRPH_ENDIAN_NONE … #define GRPH_ENDIAN_8IN16 … #define GRPH_ENDIAN_8IN32 … #define GRPH_ENDIAN_8IN64 … #define GRPH_RED_SEL_R … #define GRPH_RED_SEL_G … #define GRPH_RED_SEL_B … #define GRPH_RED_SEL_A … #define GRPH_GREEN_SEL_G … #define GRPH_GREEN_SEL_B … #define GRPH_GREEN_SEL_A … #define GRPH_GREEN_SEL_R … #define GRPH_BLUE_SEL_B … #define GRPH_BLUE_SEL_A … #define GRPH_BLUE_SEL_R … #define GRPH_BLUE_SEL_G … #define GRPH_ALPHA_SEL_A … #define GRPH_ALPHA_SEL_R … #define GRPH_ALPHA_SEL_G … #define GRPH_ALPHA_SEL_B … #define INPUT_GAMMA_USE_LUT … #define INPUT_GAMMA_BYPASS … #define INPUT_GAMMA_SRGB_24 … #define INPUT_GAMMA_XVYCC_222 … #define INPUT_CSC_BYPASS … #define INPUT_CSC_PROG_COEFF … #define INPUT_CSC_PROG_SHARED_MATRIXA … #define OUTPUT_CSC_BYPASS … #define OUTPUT_CSC_TV_RGB … #define OUTPUT_CSC_YCBCR_601 … #define OUTPUT_CSC_YCBCR_709 … #define OUTPUT_CSC_PROG_COEFF … #define OUTPUT_CSC_PROG_SHARED_MATRIXB … #define DEGAMMA_BYPASS … #define DEGAMMA_SRGB_24 … #define DEGAMMA_XVYCC_222 … #define GAMUT_REMAP_BYPASS … #define GAMUT_REMAP_PROG_COEFF … #define GAMUT_REMAP_PROG_SHARED_MATRIXA … #define GAMUT_REMAP_PROG_SHARED_MATRIXB … #define REGAMMA_BYPASS … #define REGAMMA_SRGB_24 … #define REGAMMA_XVYCC_222 … #define REGAMMA_PROG_A … #define REGAMMA_PROG_B … #define FMT_CLAMP_6BPC … #define FMT_CLAMP_8BPC … #define FMT_CLAMP_10BPC … #define HDMI_24BIT_DEEP_COLOR … #define HDMI_30BIT_DEEP_COLOR … #define HDMI_36BIT_DEEP_COLOR … #define HDMI_ACR_HW … #define HDMI_ACR_32 … #define HDMI_ACR_44 … #define HDMI_ACR_48 … #define HDMI_ACR_X1 … #define HDMI_ACR_X2 … #define HDMI_ACR_X4 … #define AFMT_AVI_INFO_Y_RGB … #define AFMT_AVI_INFO_Y_YCBCR422 … #define AFMT_AVI_INFO_Y_YCBCR444 … #define NO_AUTO … #define ES_AUTO … #define GS_AUTO … #define ES_AND_GS_AUTO … #define ARRAY_MODE(x) … #define PIPE_CONFIG(x) … #define TILE_SPLIT(x) … #define MICRO_TILE_MODE_NEW(x) … #define SAMPLE_SPLIT(x) … #define BANK_WIDTH(x) … #define BANK_HEIGHT(x) … #define MACRO_TILE_ASPECT(x) … #define NUM_BANKS(x) … #define MSG_ENTER_RLC_SAFE_MODE … #define MSG_EXIT_RLC_SAFE_MODE … /* * PM4 */ #define PACKET_TYPE0 … #define PACKET_TYPE1 … #define PACKET_TYPE2 … #define PACKET_TYPE3 … #define CP_PACKET_GET_TYPE(h) … #define CP_PACKET_GET_COUNT(h) … #define CP_PACKET0_GET_REG(h) … #define CP_PACKET3_GET_OPCODE(h) … #define PACKET0(reg, n) … #define CP_PACKET2 … #define PACKET2_PAD_SHIFT … #define PACKET2_PAD_MASK … #define PACKET2(v) … #define PACKET3(op, n) … #define PACKET3_COMPUTE(op, n) … /* Packet 3 types */ #define PACKET3_NOP … #define PACKET3_SET_BASE … #define PACKET3_BASE_INDEX(x) … #define CE_PARTITION_BASE … #define PACKET3_CLEAR_STATE … #define PACKET3_INDEX_BUFFER_SIZE … #define PACKET3_DISPATCH_DIRECT … #define PACKET3_DISPATCH_INDIRECT … #define PACKET3_ATOMIC_GDS … #define PACKET3_ATOMIC_MEM … #define PACKET3_OCCLUSION_QUERY … #define PACKET3_SET_PREDICATION … #define PACKET3_REG_RMW … #define PACKET3_COND_EXEC … #define PACKET3_PRED_EXEC … #define PACKET3_DRAW_INDIRECT … #define PACKET3_DRAW_INDEX_INDIRECT … #define PACKET3_INDEX_BASE … #define PACKET3_DRAW_INDEX_2 … #define PACKET3_CONTEXT_CONTROL … #define PACKET3_INDEX_TYPE … #define PACKET3_DRAW_INDIRECT_MULTI … #define PACKET3_DRAW_INDEX_AUTO … #define PACKET3_NUM_INSTANCES … #define PACKET3_DRAW_INDEX_MULTI_AUTO … #define PACKET3_INDIRECT_BUFFER_CONST … #define PACKET3_STRMOUT_BUFFER_UPDATE … #define PACKET3_DRAW_INDEX_OFFSET_2 … #define PACKET3_DRAW_PREAMBLE … #define PACKET3_WRITE_DATA … #define WRITE_DATA_DST_SEL(x) … /* 0 - register * 1 - memory (sync - via GRBM) * 2 - gl2 * 3 - gds * 4 - reserved * 5 - memory (async - direct) */ #define WR_ONE_ADDR … #define WR_CONFIRM … #define WRITE_DATA_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream */ #define WRITE_DATA_ENGINE_SEL(x) … /* 0 - me * 1 - pfp * 2 - ce */ #define PACKET3_DRAW_INDEX_INDIRECT_MULTI … #define PACKET3_MEM_SEMAPHORE … #define PACKET3_SEM_USE_MAILBOX … #define PACKET3_SEM_SEL_SIGNAL_TYPE … #define PACKET3_SEM_CLIENT_CODE … #define PACKET3_SEM_SEL_SIGNAL … #define PACKET3_SEM_SEL_WAIT … #define PACKET3_COPY_DW … #define PACKET3_WAIT_REG_MEM … #define WAIT_REG_MEM_FUNCTION(x) … /* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > */ #define WAIT_REG_MEM_MEM_SPACE(x) … /* 0 - reg * 1 - mem */ #define WAIT_REG_MEM_OPERATION(x) … /* 0 - wait_reg_mem * 1 - wr_wait_wr_reg */ #define WAIT_REG_MEM_ENGINE(x) … /* 0 - me * 1 - pfp */ #define PACKET3_INDIRECT_BUFFER … #define INDIRECT_BUFFER_TCL2_VOLATILE … #define INDIRECT_BUFFER_VALID … #define INDIRECT_BUFFER_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define PACKET3_COPY_DATA … #define PACKET3_PFP_SYNC_ME … #define PACKET3_SURFACE_SYNC … #define PACKET3_DEST_BASE_0_ENA … #define PACKET3_DEST_BASE_1_ENA … #define PACKET3_CB0_DEST_BASE_ENA … #define PACKET3_CB1_DEST_BASE_ENA … #define PACKET3_CB2_DEST_BASE_ENA … #define PACKET3_CB3_DEST_BASE_ENA … #define PACKET3_CB4_DEST_BASE_ENA … #define PACKET3_CB5_DEST_BASE_ENA … #define PACKET3_CB6_DEST_BASE_ENA … #define PACKET3_CB7_DEST_BASE_ENA … #define PACKET3_DB_DEST_BASE_ENA … #define PACKET3_TCL1_VOL_ACTION_ENA … #define PACKET3_TC_VOL_ACTION_ENA … #define PACKET3_TC_WB_ACTION_ENA … #define PACKET3_DEST_BASE_2_ENA … #define PACKET3_DEST_BASE_3_ENA … #define PACKET3_TCL1_ACTION_ENA … #define PACKET3_TC_ACTION_ENA … #define PACKET3_CB_ACTION_ENA … #define PACKET3_DB_ACTION_ENA … #define PACKET3_SH_KCACHE_ACTION_ENA … #define PACKET3_SH_KCACHE_VOL_ACTION_ENA … #define PACKET3_SH_ICACHE_ACTION_ENA … #define PACKET3_COND_WRITE … #define PACKET3_EVENT_WRITE … #define EVENT_TYPE(x) … #define EVENT_INDEX(x) … /* 0 - any non-TS event * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* * 2 - SAMPLE_PIPELINESTAT * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH * 5 - EOP events * 6 - EOS events */ #define PACKET3_EVENT_WRITE_EOP … #define EOP_TCL1_VOL_ACTION_EN … #define EOP_TC_VOL_ACTION_EN … #define EOP_TC_WB_ACTION_EN … #define EOP_TCL1_ACTION_EN … #define EOP_TC_ACTION_EN … #define EOP_TCL2_VOLATILE … #define EOP_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define DATA_SEL(x) … /* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit GPU counter value * 4 - send 64bit sys counter value */ #define INT_SEL(x) … /* 0 - none * 1 - interrupt only (DATA_SEL = 0) * 2 - interrupt when data write is confirmed */ #define DST_SEL(x) … /* 0 - MC * 1 - TC/L2 */ #define PACKET3_EVENT_WRITE_EOS … #define PACKET3_RELEASE_MEM … #define PACKET3_PREAMBLE_CNTL … #define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE … #define PACKET3_PREAMBLE_END_CLEAR_STATE … #define PACKET3_DMA_DATA … /* 1. header * 2. CONTROL * 3. SRC_ADDR_LO or DATA [31:0] * 4. SRC_ADDR_HI [31:0] * 5. DST_ADDR_LO [31:0] * 6. DST_ADDR_HI [7:0] * 7. COMMAND [30:21] | BYTE_COUNT [20:0] */ /* CONTROL */ #define PACKET3_DMA_DATA_ENGINE(x) … /* 0 - ME * 1 - PFP */ #define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define PACKET3_DMA_DATA_SRC_VOLATILE … #define PACKET3_DMA_DATA_DST_SEL(x) … /* 0 - DST_ADDR using DAS * 1 - GDS * 3 - DST_ADDR using L2 */ #define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define PACKET3_DMA_DATA_DST_VOLATILE … #define PACKET3_DMA_DATA_SRC_SEL(x) … /* 0 - SRC_ADDR using SAS * 1 - GDS * 2 - DATA * 3 - SRC_ADDR using L2 */ #define PACKET3_DMA_DATA_CP_SYNC … /* COMMAND */ #define PACKET3_DMA_DATA_DIS_WC … #define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) … /* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 */ #define PACKET3_DMA_DATA_CMD_DST_SWAP(x) … /* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 */ #define PACKET3_DMA_DATA_CMD_SAS … /* 0 - memory * 1 - register */ #define PACKET3_DMA_DATA_CMD_DAS … /* 0 - memory * 1 - register */ #define PACKET3_DMA_DATA_CMD_SAIC … #define PACKET3_DMA_DATA_CMD_DAIC … #define PACKET3_DMA_DATA_CMD_RAW_WAIT … #define PACKET3_ACQUIRE_MEM … #define PACKET3_REWIND … #define PACKET3_LOAD_UCONFIG_REG … #define PACKET3_LOAD_SH_REG … #define PACKET3_LOAD_CONFIG_REG … #define PACKET3_LOAD_CONTEXT_REG … #define PACKET3_SET_CONFIG_REG … #define PACKET3_SET_CONFIG_REG_START … #define PACKET3_SET_CONFIG_REG_END … #define PACKET3_SET_CONTEXT_REG … #define PACKET3_SET_CONTEXT_REG_START … #define PACKET3_SET_CONTEXT_REG_END … #define PACKET3_SET_CONTEXT_REG_INDIRECT … #define PACKET3_SET_SH_REG … #define PACKET3_SET_SH_REG_START … #define PACKET3_SET_SH_REG_END … #define PACKET3_SET_SH_REG_OFFSET … #define PACKET3_SET_QUEUE_REG … #define PACKET3_SET_UCONFIG_REG … #define PACKET3_SET_UCONFIG_REG_START … #define PACKET3_SET_UCONFIG_REG_END … #define PACKET3_SCRATCH_RAM_WRITE … #define PACKET3_SCRATCH_RAM_READ … #define PACKET3_LOAD_CONST_RAM … #define PACKET3_WRITE_CONST_RAM … #define PACKET3_DUMP_CONST_RAM … #define PACKET3_INCREMENT_CE_COUNTER … #define PACKET3_INCREMENT_DE_COUNTER … #define PACKET3_WAIT_ON_CE_COUNTER … #define PACKET3_WAIT_ON_DE_COUNTER_DIFF … #define PACKET3_SWITCH_BUFFER … /* SDMA - first instance at 0xd000, second at 0xd800 */ #define SDMA0_REGISTER_OFFSET … #define SDMA1_REGISTER_OFFSET … #define SDMA_MAX_INSTANCE … #define SDMA_PACKET(op, sub_op, e) … /* sDMA opcodes */ #define SDMA_OPCODE_NOP … #define SDMA_NOP_COUNT(x) … #define SDMA_OPCODE_COPY … #define SDMA_COPY_SUB_OPCODE_LINEAR … #define SDMA_COPY_SUB_OPCODE_TILED … #define SDMA_COPY_SUB_OPCODE_SOA … #define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW … #define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW … #define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW … #define SDMA_OPCODE_WRITE … #define SDMA_WRITE_SUB_OPCODE_LINEAR … #define SDMA_WRITE_SUB_OPCODE_TILED … #define SDMA_OPCODE_INDIRECT_BUFFER … #define SDMA_OPCODE_FENCE … #define SDMA_OPCODE_TRAP … #define SDMA_OPCODE_SEMAPHORE … #define SDMA_SEMAPHORE_EXTRA_O … /* 0 - increment * 1 - write 1 */ #define SDMA_SEMAPHORE_EXTRA_S … /* 0 - wait * 1 - signal */ #define SDMA_SEMAPHORE_EXTRA_M … /* mailbox */ #define SDMA_OPCODE_POLL_REG_MEM … #define SDMA_POLL_REG_MEM_EXTRA_OP(x) … /* 0 - wait_reg_mem * 1 - wr_wait_wr_reg */ #define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) … /* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > */ #define SDMA_POLL_REG_MEM_EXTRA_M … /* 0 = register * 1 = memory */ #define SDMA_OPCODE_COND_EXEC … #define SDMA_OPCODE_CONSTANT_FILL … #define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) … /* 0 = byte fill * 2 = DW fill */ #define SDMA_OPCODE_GENERATE_PTE_PDE … #define SDMA_OPCODE_TIMESTAMP … #define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL … #define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL … #define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL … #define SDMA_OPCODE_SRBM_WRITE … #define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) … /* byte mask */ #define VCE_CMD_NO_OP … #define VCE_CMD_END … #define VCE_CMD_IB … #define VCE_CMD_FENCE … #define VCE_CMD_TRAP … #define VCE_CMD_IB_AUTO … #define VCE_CMD_SEMAPHORE … /* if PTR32, these are the bases for scratch and lds */ #define PRIVATE_BASE(x) … #define SHARED_BASE(x) … #define KFD_CIK_SDMA_QUEUE_OFFSET … /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ enum { … }; /* mmPA_SC_RASTER_CONFIG mask */ #define RB_MAP_PKR0(x) … #define RB_MAP_PKR0_MASK … #define RB_MAP_PKR1(x) … #define RB_MAP_PKR1_MASK … #define RB_XSEL2(x) … #define RB_XSEL2_MASK … #define RB_XSEL … #define RB_YSEL … #define PKR_MAP(x) … #define PKR_MAP_MASK … #define PKR_XSEL(x) … #define PKR_XSEL_MASK … #define PKR_YSEL(x) … #define PKR_YSEL_MASK … #define SC_MAP(x) … #define SC_MAP_MASK … #define SC_XSEL(x) … #define SC_XSEL_MASK … #define SC_YSEL(x) … #define SC_YSEL_MASK … #define SE_MAP(x) … #define SE_MAP_MASK … #define SE_XSEL(x) … #define SE_XSEL_MASK … #define SE_YSEL(x) … #define SE_YSEL_MASK … /* mmPA_SC_RASTER_CONFIG_1 mask */ #define SE_PAIR_MAP(x) … #define SE_PAIR_MAP_MASK … #define SE_PAIR_XSEL(x) … #define SE_PAIR_XSEL_MASK … #define SE_PAIR_YSEL(x) … #define SE_PAIR_YSEL_MASK … #endif
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