/* * Copyright 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef PP_SMC_H #define PP_SMC_H #pragma pack(push, 1) #define PPSMC_SWSTATE_FLAG_DC … #define PPSMC_SWSTATE_FLAG_UVD … #define PPSMC_SWSTATE_FLAG_VCE … #define PPSMC_SWSTATE_FLAG_PCIE_X1 … #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL … #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL … #define PPSMC_THERMAL_PROTECT_TYPE_NONE … #define PPSMC_SYSTEMFLAG_GPIO_DC … #define PPSMC_SYSTEMFLAG_STEPVDDC … #define PPSMC_SYSTEMFLAG_GDDR5 … #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP … #define PPSMC_SYSTEMFLAG_REGULATOR_HOT … #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG … #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO … #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK … #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK … #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE … #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE … #define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH … #define PPSMC_DISPLAY_WATERMARK_LOW … #define PPSMC_DISPLAY_WATERMARK_HIGH … #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP … #define PPSMC_STATEFLAG_POWERBOOST … #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE … #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS … #define FDO_MODE_HARDWARE … #define FDO_MODE_PIECE_WISE_LINEAR … enum FAN_CONTROL { … }; #define PPSMC_Result_OK … #define PPSMC_Result_Failed … PPSMC_Result; #define PPSMC_MSG_Halt … #define PPSMC_MSG_Resume … #define PPSMC_MSG_ZeroLevelsDisabled … #define PPSMC_MSG_OneLevelsDisabled … #define PPSMC_MSG_TwoLevelsDisabled … #define PPSMC_MSG_EnableThermalInterrupt … #define PPSMC_MSG_RunningOnAC … #define PPSMC_MSG_SwitchToSwState … #define PPSMC_MSG_SwitchToInitialState … #define PPSMC_MSG_NoForcedLevel … #define PPSMC_MSG_ForceHigh … #define PPSMC_MSG_ForceMediumOrHigh … #define PPSMC_MSG_SwitchToMinimumPower … #define PPSMC_MSG_ResumeFromMinimumPower … #define PPSMC_MSG_EnableCac … #define PPSMC_MSG_DisableCac … #define PPSMC_TDPClampingActive … #define PPSMC_TDPClampingInactive … #define PPSMC_StartFanControl … #define PPSMC_StopFanControl … #define PPSMC_MSG_NoDisplay … #define PPSMC_NoDisplay … #define PPSMC_MSG_HasDisplay … #define PPSMC_HasDisplay … #define PPSMC_MSG_UVDPowerOFF … #define PPSMC_MSG_UVDPowerON … #define PPSMC_MSG_EnableULV … #define PPSMC_MSG_DisableULV … #define PPSMC_MSG_EnterULV … #define PPSMC_MSG_ExitULV … #define PPSMC_CACLongTermAvgEnable … #define PPSMC_CACLongTermAvgDisable … #define PPSMC_MSG_CollectCAC_PowerCorreln … #define PPSMC_FlushDataCache … #define PPSMC_MSG_SetEnabledLevels … #define PPSMC_MSG_SetForcedLevels … #define PPSMC_MSG_ResetToDefaults … #define PPSMC_MSG_EnableDTE … #define PPSMC_MSG_DisableDTE … #define PPSMC_MSG_ThrottleOVRDSCLKDS … #define PPSMC_MSG_CancelThrottleOVRDSCLKDS … #define PPSMC_MSG_EnableACDCGPIOInterrupt … /* CI/KV/KB */ #define PPSMC_MSG_UVDDPM_SetEnabledMask … #define PPSMC_MSG_VCEDPM_SetEnabledMask … #define PPSMC_MSG_ACPDPM_SetEnabledMask … #define PPSMC_MSG_SAMUDPM_SetEnabledMask … #define PPSMC_MSG_MCLKDPM_ForceState … #define PPSMC_MSG_MCLKDPM_NoForcedLevel … #define PPSMC_MSG_Thermal_Cntl_Disable … #define PPSMC_MSG_Voltage_Cntl_Disable … #define PPSMC_MSG_PCIeDPM_Enable … #define PPSMC_MSG_PCIeDPM_Disable … #define PPSMC_MSG_ACPPowerOFF … #define PPSMC_MSG_ACPPowerON … #define PPSMC_MSG_SAMPowerOFF … #define PPSMC_MSG_SAMPowerON … #define PPSMC_MSG_PCIeDPM_Disable … #define PPSMC_MSG_NBDPM_Enable … #define PPSMC_MSG_NBDPM_Disable … #define PPSMC_MSG_SCLKDPM_SetEnabledMask … #define PPSMC_MSG_MCLKDPM_SetEnabledMask … #define PPSMC_MSG_PCIeDPM_ForceLevel … #define PPSMC_MSG_PCIeDPM_UnForceLevel … #define PPSMC_MSG_EnableVRHotGPIOInterrupt … #define PPSMC_MSG_DPM_Enable … #define PPSMC_MSG_DPM_Disable … #define PPSMC_MSG_MCLKDPM_Enable … #define PPSMC_MSG_MCLKDPM_Disable … #define PPSMC_MSG_UVDDPM_Enable … #define PPSMC_MSG_UVDDPM_Disable … #define PPSMC_MSG_SAMUDPM_Enable … #define PPSMC_MSG_SAMUDPM_Disable … #define PPSMC_MSG_ACPDPM_Enable … #define PPSMC_MSG_ACPDPM_Disable … #define PPSMC_MSG_VCEDPM_Enable … #define PPSMC_MSG_VCEDPM_Disable … #define PPSMC_MSG_VddC_Request … #define PPSMC_MSG_SCLKDPM_GetEnabledMask … #define PPSMC_MSG_PCIeDPM_SetEnabledMask … #define PPSMC_MSG_TDCLimitEnable … #define PPSMC_MSG_TDCLimitDisable … #define PPSMC_MSG_PkgPwrLimitEnable … #define PPSMC_MSG_PkgPwrLimitDisable … #define PPSMC_MSG_PkgPwrSetLimit … #define PPSMC_MSG_OverDriveSetTargetTdp … #define PPSMC_MSG_SCLKDPM_FreezeLevel … #define PPSMC_MSG_SCLKDPM_UnfreezeLevel … #define PPSMC_MSG_MCLKDPM_FreezeLevel … #define PPSMC_MSG_MCLKDPM_UnfreezeLevel … #define PPSMC_MSG_MASTER_DeepSleep_ON … #define PPSMC_MSG_MASTER_DeepSleep_OFF … #define PPSMC_MSG_Remove_DC_Clamp … #define PPSMC_MSG_SetFanPwmMax … #define PPSMC_MSG_SetFanRpmMax … #define PPSMC_MSG_ENABLE_THERMAL_DPM … #define PPSMC_MSG_DISABLE_THERMAL_DPM … #define PPSMC_MSG_API_GetSclkFrequency … #define PPSMC_MSG_API_GetMclkFrequency … /* TN */ #define PPSMC_MSG_DPM_Config … #define PPSMC_MSG_DPM_ForceState … #define PPSMC_MSG_PG_SIMD_Config … #define PPSMC_MSG_Voltage_Cntl_Enable … #define PPSMC_MSG_Thermal_Cntl_Enable … #define PPSMC_MSG_VCEPowerOFF … #define PPSMC_MSG_VCEPowerON … #define PPSMC_MSG_DPM_N_LevelsDisabled … #define PPSMC_MSG_DCE_RemoveVoltageAdjustment … #define PPSMC_MSG_DCE_AllowVoltageAdjustment … #define PPSMC_MSG_EnableBAPM … #define PPSMC_MSG_DisableBAPM … #define PPSMC_MSG_UVD_DPM_Config … #define PPSMC_MSG_DRV_DRAM_ADDR_HI … #define PPSMC_MSG_DRV_DRAM_ADDR_LO … #define PPSMC_MSG_SMU_DRAM_ADDR_HI … #define PPSMC_MSG_SMU_DRAM_ADDR_LO … #define PPSMC_MSG_LoadUcodes … PPSMC_Msg; #pragma pack(pop) #endif
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