/* * Copyright 2013 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef PP_SISLANDS_SMC_H #define PP_SISLANDS_SMC_H #include "ppsmc.h" #pragma pack(push, 1) #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE … struct PP_SIslands_Dpm2PerfLevel { … }; PP_SIslands_Dpm2PerfLevel; struct PP_SIslands_DPM2Status { … }; PP_SIslands_DPM2Status; struct PP_SIslands_DPM2Parameters { … }; PP_SIslands_DPM2Parameters; struct PP_SIslands_PAPMStatus { … }; PP_SIslands_PAPMStatus; struct PP_SIslands_PAPMParameters { … }; PP_SIslands_PAPMParameters; struct SISLANDS_SMC_SCLK_VALUE { … }; SISLANDS_SMC_SCLK_VALUE; struct SISLANDS_SMC_MCLK_VALUE { … }; SISLANDS_SMC_MCLK_VALUE; struct SISLANDS_SMC_VOLTAGE_VALUE { … }; SISLANDS_SMC_VOLTAGE_VALUE; struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL { … }; #define SISLANDS_SMC_STROBE_RATIO … #define SISLANDS_SMC_STROBE_ENABLE … #define SISLANDS_SMC_MC_EDC_RD_FLAG … #define SISLANDS_SMC_MC_EDC_WR_FLAG … #define SISLANDS_SMC_MC_RTT_ENABLE … #define SISLANDS_SMC_MC_STUTTER_EN … #define SISLANDS_SMC_MC_PG_EN … SISLANDS_SMC_HW_PERFORMANCE_LEVEL; struct SISLANDS_SMC_SWSTATE { … }; SISLANDS_SMC_SWSTATE; struct SISLANDS_SMC_SWSTATE_SINGLE { … }; #define SISLANDS_SMC_VOLTAGEMASK_VDDC … #define SISLANDS_SMC_VOLTAGEMASK_MVDD … #define SISLANDS_SMC_VOLTAGEMASK_VDDCI … #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING … #define SISLANDS_SMC_VOLTAGEMASK_MAX … struct SISLANDS_SMC_VOLTAGEMASKTABLE { … }; SISLANDS_SMC_VOLTAGEMASKTABLE; #define SISLANDS_MAX_NO_VREG_STEPS … struct SISLANDS_SMC_STATETABLE { … }; SISLANDS_SMC_STATETABLE; #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout … #define SI_SMC_SOFT_REGISTER_delay_vreg … #define SI_SMC_SOFT_REGISTER_delay_acpi … #define SI_SMC_SOFT_REGISTER_seq_index … #define SI_SMC_SOFT_REGISTER_mvdd_chg_time … #define SI_SMC_SOFT_REGISTER_mclk_switch_lim … #define SI_SMC_SOFT_REGISTER_watermark_threshold … #define SI_SMC_SOFT_REGISTER_phase_shedding_delay … #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay … #define SI_SMC_SOFT_REGISTER_mc_block_delay … #define SI_SMC_SOFT_REGISTER_ticks_per_us … #define SI_SMC_SOFT_REGISTER_crtc_index … #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min … #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max … #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width … #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen … #define SI_SMC_SOFT_REGISTER_vr_hot_gpio … #define SI_SMC_SOFT_REGISTER_svi_rework_plat_type … #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd … #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc … struct PP_SIslands_FanTable { … }; PP_SIslands_FanTable; #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES … #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES … #define SMC_SISLANDS_SCALE_I … #define SMC_SISLANDS_SCALE_R … struct PP_SIslands_CacConfig { … }; PP_SIslands_CacConfig; #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE … #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT … struct SMC_SIslands_MCRegisterAddress { … }; SMC_SIslands_MCRegisterAddress; struct SMC_SIslands_MCRegisterSet { … }; SMC_SIslands_MCRegisterSet; struct SMC_SIslands_MCRegisters { … }; SMC_SIslands_MCRegisters; struct SMC_SIslands_MCArbDramTimingRegisterSet { … }; SMC_SIslands_MCArbDramTimingRegisterSet; struct SMC_SIslands_MCArbDramTimingRegisters { … }; SMC_SIslands_MCArbDramTimingRegisters; struct SMC_SISLANDS_SPLL_DIV_TABLE { … }; #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK … #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT … #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK … #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT … #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK … #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT … #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK … #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT … SMC_SISLANDS_SPLL_DIV_TABLE; #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES … #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE … struct Smc_SIslands_DTE_Configuration { … }; Smc_SIslands_DTE_Configuration; #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON … #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION … #define SISLANDS_SMC_FIRMWARE_HEADER_version … #define SISLANDS_SMC_FIRMWARE_HEADER_flags … #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters … #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable … #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable … #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable … #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable … #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable … #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable … #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration … #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters … #pragma pack(pop) int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, u32 smc_start_address, const u8 *src, u32 byte_count, u32 limit); void amdgpu_si_start_smc(struct amdgpu_device *adev); void amdgpu_si_reset_smc(struct amdgpu_device *adev); int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev); void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable); bool amdgpu_si_is_smc_running(struct amdgpu_device *adev); PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg); PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev); int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit); int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, u32 *value, u32 limit); int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, u32 value, u32 limit); #endif
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