linux/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h

/*
 * DCE_8_0 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef DCE_8_0_D_H
#define DCE_8_0_D_H

#define mmPIPE0_PG_CONFIG …
#define mmPIPE0_PG_ENABLE …
#define mmPIPE0_PG_STATUS …
#define mmPIPE1_PG_CONFIG …
#define mmPIPE1_PG_ENABLE …
#define mmPIPE1_PG_STATUS …
#define mmPIPE2_PG_CONFIG …
#define mmPIPE2_PG_ENABLE …
#define mmPIPE2_PG_STATUS …
#define mmPIPE3_PG_CONFIG …
#define mmPIPE3_PG_ENABLE …
#define mmPIPE3_PG_STATUS …
#define mmPIPE4_PG_CONFIG …
#define mmPIPE4_PG_ENABLE …
#define mmPIPE4_PG_STATUS …
#define mmPIPE5_PG_CONFIG …
#define mmPIPE5_PG_ENABLE …
#define mmPIPE5_PG_STATUS …
#define mmDC_IP_REQUEST_CNTL …
#define mmDC_PGFSM_CONFIG_REG …
#define mmDC_PGFSM_WRITE_REG …
#define mmDC_PGCNTL_STATUS_REG …
#define mmDCPG_TEST_DEBUG_INDEX …
#define mmDCPG_TEST_DEBUG_DATA …
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL …
#define mmBL1_PWM_USER_LEVEL …
#define mmBL1_PWM_TARGET_ABM_LEVEL …
#define mmBL1_PWM_CURRENT_ABM_LEVEL …
#define mmBL1_PWM_FINAL_DUTY_CYCLE …
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE …
#define mmBL1_PWM_ABM_CNTL …
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE …
#define mmBL1_PWM_GRP2_REG_LOCK …
#define mmDC_ABM1_CNTL …
#define mmDC_ABM1_IPCSC_COEFF_SEL …
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 …
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 …
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 …
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 …
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 …
#define mmDC_ABM1_ACE_THRES_12 …
#define mmDC_ABM1_ACE_THRES_34 …
#define mmDC_ABM1_ACE_CNTL_MISC …
#define mmDC_ABM1_DEBUG_MISC …
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS …
#define mmDC_ABM1_HG_MISC_CTRL …
#define mmDC_ABM1_LS_SUM_OF_LUMA …
#define mmDC_ABM1_LS_MIN_MAX_LUMA …
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA …
#define mmDC_ABM1_LS_PIXEL_COUNT …
#define mmDC_ABM1_LS_OVR_SCAN_BIN …
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES …
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT …
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT …
#define mmDC_ABM1_HG_SAMPLE_RATE …
#define mmDC_ABM1_LS_SAMPLE_RATE …
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG …
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX …
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX …
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX …
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX …
#define mmDC_ABM1_HG_RESULT_1 …
#define mmDC_ABM1_HG_RESULT_2 …
#define mmDC_ABM1_HG_RESULT_3 …
#define mmDC_ABM1_HG_RESULT_4 …
#define mmDC_ABM1_HG_RESULT_5 …
#define mmDC_ABM1_HG_RESULT_6 …
#define mmDC_ABM1_HG_RESULT_7 …
#define mmDC_ABM1_HG_RESULT_8 …
#define mmDC_ABM1_HG_RESULT_9 …
#define mmDC_ABM1_HG_RESULT_10 …
#define mmDC_ABM1_HG_RESULT_11 …
#define mmDC_ABM1_HG_RESULT_12 …
#define mmDC_ABM1_HG_RESULT_13 …
#define mmDC_ABM1_HG_RESULT_14 …
#define mmDC_ABM1_HG_RESULT_15 …
#define mmDC_ABM1_HG_RESULT_16 …
#define mmDC_ABM1_HG_RESULT_17 …
#define mmDC_ABM1_HG_RESULT_18 …
#define mmDC_ABM1_HG_RESULT_19 …
#define mmDC_ABM1_HG_RESULT_20 …
#define mmDC_ABM1_HG_RESULT_21 …
#define mmDC_ABM1_HG_RESULT_22 …
#define mmDC_ABM1_HG_RESULT_23 …
#define mmDC_ABM1_HG_RESULT_24 …
#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE …
#define mmDC_ABM1_BL_MASTER_LOCK …
#define mmABM_TEST_DEBUG_INDEX …
#define mmABM_TEST_DEBUG_DATA …
#define mmCRTC_DCFE_CLOCK_CONTROL …
#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL …
#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL …
#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL …
#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL …
#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL …
#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL …
#define mmCRTC_H_BLANK_EARLY_NUM …
#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM …
#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM …
#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM …
#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM …
#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM …
#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM …
#define mmDCFE_DBG_SEL …
#define mmCRTC0_DCFE_DBG_SEL …
#define mmCRTC1_DCFE_DBG_SEL …
#define mmCRTC2_DCFE_DBG_SEL …
#define mmCRTC3_DCFE_DBG_SEL …
#define mmCRTC4_DCFE_DBG_SEL …
#define mmCRTC5_DCFE_DBG_SEL …
#define mmDCFE_MEM_LIGHT_SLEEP_CNTL …
#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL …
#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL …
#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL …
#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL …
#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL …
#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL …
#define mmCRTC_H_TOTAL …
#define mmCRTC0_CRTC_H_TOTAL …
#define mmCRTC1_CRTC_H_TOTAL …
#define mmCRTC2_CRTC_H_TOTAL …
#define mmCRTC3_CRTC_H_TOTAL …
#define mmCRTC4_CRTC_H_TOTAL …
#define mmCRTC5_CRTC_H_TOTAL …
#define mmCRTC_H_BLANK_START_END …
#define mmCRTC0_CRTC_H_BLANK_START_END …
#define mmCRTC1_CRTC_H_BLANK_START_END …
#define mmCRTC2_CRTC_H_BLANK_START_END …
#define mmCRTC3_CRTC_H_BLANK_START_END …
#define mmCRTC4_CRTC_H_BLANK_START_END …
#define mmCRTC5_CRTC_H_BLANK_START_END …
#define mmCRTC_H_SYNC_A …
#define mmCRTC0_CRTC_H_SYNC_A …
#define mmCRTC1_CRTC_H_SYNC_A …
#define mmCRTC2_CRTC_H_SYNC_A …
#define mmCRTC3_CRTC_H_SYNC_A …
#define mmCRTC4_CRTC_H_SYNC_A …
#define mmCRTC5_CRTC_H_SYNC_A …
#define mmCRTC_H_SYNC_A_CNTL …
#define mmCRTC0_CRTC_H_SYNC_A_CNTL …
#define mmCRTC1_CRTC_H_SYNC_A_CNTL …
#define mmCRTC2_CRTC_H_SYNC_A_CNTL …
#define mmCRTC3_CRTC_H_SYNC_A_CNTL …
#define mmCRTC4_CRTC_H_SYNC_A_CNTL …
#define mmCRTC5_CRTC_H_SYNC_A_CNTL …
#define mmCRTC_H_SYNC_B …
#define mmCRTC0_CRTC_H_SYNC_B …
#define mmCRTC1_CRTC_H_SYNC_B …
#define mmCRTC2_CRTC_H_SYNC_B …
#define mmCRTC3_CRTC_H_SYNC_B …
#define mmCRTC4_CRTC_H_SYNC_B …
#define mmCRTC5_CRTC_H_SYNC_B …
#define mmCRTC_H_SYNC_B_CNTL …
#define mmCRTC0_CRTC_H_SYNC_B_CNTL …
#define mmCRTC1_CRTC_H_SYNC_B_CNTL …
#define mmCRTC2_CRTC_H_SYNC_B_CNTL …
#define mmCRTC3_CRTC_H_SYNC_B_CNTL …
#define mmCRTC4_CRTC_H_SYNC_B_CNTL …
#define mmCRTC5_CRTC_H_SYNC_B_CNTL …
#define mmCRTC_VBI_END …
#define mmCRTC0_CRTC_VBI_END …
#define mmCRTC1_CRTC_VBI_END …
#define mmCRTC2_CRTC_VBI_END …
#define mmCRTC3_CRTC_VBI_END …
#define mmCRTC4_CRTC_VBI_END …
#define mmCRTC5_CRTC_VBI_END …
#define mmCRTC_V_TOTAL …
#define mmCRTC0_CRTC_V_TOTAL …
#define mmCRTC1_CRTC_V_TOTAL …
#define mmCRTC2_CRTC_V_TOTAL …
#define mmCRTC3_CRTC_V_TOTAL …
#define mmCRTC4_CRTC_V_TOTAL …
#define mmCRTC5_CRTC_V_TOTAL …
#define mmCRTC_V_TOTAL_MIN …
#define mmCRTC0_CRTC_V_TOTAL_MIN …
#define mmCRTC1_CRTC_V_TOTAL_MIN …
#define mmCRTC2_CRTC_V_TOTAL_MIN …
#define mmCRTC3_CRTC_V_TOTAL_MIN …
#define mmCRTC4_CRTC_V_TOTAL_MIN …
#define mmCRTC5_CRTC_V_TOTAL_MIN …
#define mmCRTC_V_TOTAL_MAX …
#define mmCRTC0_CRTC_V_TOTAL_MAX …
#define mmCRTC1_CRTC_V_TOTAL_MAX …
#define mmCRTC2_CRTC_V_TOTAL_MAX …
#define mmCRTC3_CRTC_V_TOTAL_MAX …
#define mmCRTC4_CRTC_V_TOTAL_MAX …
#define mmCRTC5_CRTC_V_TOTAL_MAX …
#define mmCRTC_V_TOTAL_CONTROL …
#define mmCRTC0_CRTC_V_TOTAL_CONTROL …
#define mmCRTC1_CRTC_V_TOTAL_CONTROL …
#define mmCRTC2_CRTC_V_TOTAL_CONTROL …
#define mmCRTC3_CRTC_V_TOTAL_CONTROL …
#define mmCRTC4_CRTC_V_TOTAL_CONTROL …
#define mmCRTC5_CRTC_V_TOTAL_CONTROL …
#define mmCRTC_V_TOTAL_INT_STATUS …
#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS …
#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS …
#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS …
#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS …
#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS …
#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS …
#define mmCRTC_VSYNC_NOM_INT_STATUS …
#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS …
#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS …
#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS …
#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS …
#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS …
#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS …
#define mmCRTC_V_BLANK_START_END …
#define mmCRTC0_CRTC_V_BLANK_START_END …
#define mmCRTC1_CRTC_V_BLANK_START_END …
#define mmCRTC2_CRTC_V_BLANK_START_END …
#define mmCRTC3_CRTC_V_BLANK_START_END …
#define mmCRTC4_CRTC_V_BLANK_START_END …
#define mmCRTC5_CRTC_V_BLANK_START_END …
#define mmCRTC_V_SYNC_A …
#define mmCRTC0_CRTC_V_SYNC_A …
#define mmCRTC1_CRTC_V_SYNC_A …
#define mmCRTC2_CRTC_V_SYNC_A …
#define mmCRTC3_CRTC_V_SYNC_A …
#define mmCRTC4_CRTC_V_SYNC_A …
#define mmCRTC5_CRTC_V_SYNC_A …
#define mmCRTC_V_SYNC_A_CNTL …
#define mmCRTC0_CRTC_V_SYNC_A_CNTL …
#define mmCRTC1_CRTC_V_SYNC_A_CNTL …
#define mmCRTC2_CRTC_V_SYNC_A_CNTL …
#define mmCRTC3_CRTC_V_SYNC_A_CNTL …
#define mmCRTC4_CRTC_V_SYNC_A_CNTL …
#define mmCRTC5_CRTC_V_SYNC_A_CNTL …
#define mmCRTC_V_SYNC_B …
#define mmCRTC0_CRTC_V_SYNC_B …
#define mmCRTC1_CRTC_V_SYNC_B …
#define mmCRTC2_CRTC_V_SYNC_B …
#define mmCRTC3_CRTC_V_SYNC_B …
#define mmCRTC4_CRTC_V_SYNC_B …
#define mmCRTC5_CRTC_V_SYNC_B …
#define mmCRTC_V_SYNC_B_CNTL …
#define mmCRTC0_CRTC_V_SYNC_B_CNTL …
#define mmCRTC1_CRTC_V_SYNC_B_CNTL …
#define mmCRTC2_CRTC_V_SYNC_B_CNTL …
#define mmCRTC3_CRTC_V_SYNC_B_CNTL …
#define mmCRTC4_CRTC_V_SYNC_B_CNTL …
#define mmCRTC5_CRTC_V_SYNC_B_CNTL …
#define mmCRTC_DTMTEST_CNTL …
#define mmCRTC0_CRTC_DTMTEST_CNTL …
#define mmCRTC1_CRTC_DTMTEST_CNTL …
#define mmCRTC2_CRTC_DTMTEST_CNTL …
#define mmCRTC3_CRTC_DTMTEST_CNTL …
#define mmCRTC4_CRTC_DTMTEST_CNTL …
#define mmCRTC5_CRTC_DTMTEST_CNTL …
#define mmCRTC_DTMTEST_STATUS_POSITION …
#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION …
#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION …
#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION …
#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION …
#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION …
#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION …
#define mmCRTC_TRIGA_CNTL …
#define mmCRTC0_CRTC_TRIGA_CNTL …
#define mmCRTC1_CRTC_TRIGA_CNTL …
#define mmCRTC2_CRTC_TRIGA_CNTL …
#define mmCRTC3_CRTC_TRIGA_CNTL …
#define mmCRTC4_CRTC_TRIGA_CNTL …
#define mmCRTC5_CRTC_TRIGA_CNTL …
#define mmCRTC_TRIGA_MANUAL_TRIG …
#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG …
#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG …
#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG …
#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG …
#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG …
#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG …
#define mmCRTC_TRIGB_CNTL …
#define mmCRTC0_CRTC_TRIGB_CNTL …
#define mmCRTC1_CRTC_TRIGB_CNTL …
#define mmCRTC2_CRTC_TRIGB_CNTL …
#define mmCRTC3_CRTC_TRIGB_CNTL …
#define mmCRTC4_CRTC_TRIGB_CNTL …
#define mmCRTC5_CRTC_TRIGB_CNTL …
#define mmCRTC_TRIGB_MANUAL_TRIG …
#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG …
#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG …
#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG …
#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG …
#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG …
#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG …
#define mmCRTC_FORCE_COUNT_NOW_CNTL …
#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL …
#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL …
#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL …
#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL …
#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL …
#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL …
#define mmCRTC_FLOW_CONTROL …
#define mmCRTC0_CRTC_FLOW_CONTROL …
#define mmCRTC1_CRTC_FLOW_CONTROL …
#define mmCRTC2_CRTC_FLOW_CONTROL …
#define mmCRTC3_CRTC_FLOW_CONTROL …
#define mmCRTC4_CRTC_FLOW_CONTROL …
#define mmCRTC5_CRTC_FLOW_CONTROL …
#define mmCRTC_STEREO_FORCE_NEXT_EYE …
#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE …
#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE …
#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE …
#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE …
#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE …
#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE …
#define mmCRTC_CONTROL …
#define mmCRTC0_CRTC_CONTROL …
#define mmCRTC1_CRTC_CONTROL …
#define mmCRTC2_CRTC_CONTROL …
#define mmCRTC3_CRTC_CONTROL …
#define mmCRTC4_CRTC_CONTROL …
#define mmCRTC5_CRTC_CONTROL …
#define mmCRTC_BLANK_CONTROL …
#define mmCRTC0_CRTC_BLANK_CONTROL …
#define mmCRTC1_CRTC_BLANK_CONTROL …
#define mmCRTC2_CRTC_BLANK_CONTROL …
#define mmCRTC3_CRTC_BLANK_CONTROL …
#define mmCRTC4_CRTC_BLANK_CONTROL …
#define mmCRTC5_CRTC_BLANK_CONTROL …
#define mmCRTC_INTERLACE_CONTROL …
#define mmCRTC0_CRTC_INTERLACE_CONTROL …
#define mmCRTC1_CRTC_INTERLACE_CONTROL …
#define mmCRTC2_CRTC_INTERLACE_CONTROL …
#define mmCRTC3_CRTC_INTERLACE_CONTROL …
#define mmCRTC4_CRTC_INTERLACE_CONTROL …
#define mmCRTC5_CRTC_INTERLACE_CONTROL …
#define mmCRTC_INTERLACE_STATUS …
#define mmCRTC0_CRTC_INTERLACE_STATUS …
#define mmCRTC1_CRTC_INTERLACE_STATUS …
#define mmCRTC2_CRTC_INTERLACE_STATUS …
#define mmCRTC3_CRTC_INTERLACE_STATUS …
#define mmCRTC4_CRTC_INTERLACE_STATUS …
#define mmCRTC5_CRTC_INTERLACE_STATUS …
#define mmCRTC_FIELD_INDICATION_CONTROL …
#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL …
#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL …
#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL …
#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL …
#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL …
#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL …
#define mmCRTC_PIXEL_DATA_READBACK0 …
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 …
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 …
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 …
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 …
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 …
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 …
#define mmCRTC_PIXEL_DATA_READBACK1 …
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 …
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 …
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 …
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 …
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 …
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 …
#define mmCRTC_STATUS …
#define mmCRTC0_CRTC_STATUS …
#define mmCRTC1_CRTC_STATUS …
#define mmCRTC2_CRTC_STATUS …
#define mmCRTC3_CRTC_STATUS …
#define mmCRTC4_CRTC_STATUS …
#define mmCRTC5_CRTC_STATUS …
#define mmCRTC_STATUS_POSITION …
#define mmCRTC0_CRTC_STATUS_POSITION …
#define mmCRTC1_CRTC_STATUS_POSITION …
#define mmCRTC2_CRTC_STATUS_POSITION …
#define mmCRTC3_CRTC_STATUS_POSITION …
#define mmCRTC4_CRTC_STATUS_POSITION …
#define mmCRTC5_CRTC_STATUS_POSITION …
#define mmCRTC_NOM_VERT_POSITION …
#define mmCRTC0_CRTC_NOM_VERT_POSITION …
#define mmCRTC1_CRTC_NOM_VERT_POSITION …
#define mmCRTC2_CRTC_NOM_VERT_POSITION …
#define mmCRTC3_CRTC_NOM_VERT_POSITION …
#define mmCRTC4_CRTC_NOM_VERT_POSITION …
#define mmCRTC5_CRTC_NOM_VERT_POSITION …
#define mmCRTC_STATUS_FRAME_COUNT …
#define mmCRTC0_CRTC_STATUS_FRAME_COUNT …
#define mmCRTC1_CRTC_STATUS_FRAME_COUNT …
#define mmCRTC2_CRTC_STATUS_FRAME_COUNT …
#define mmCRTC3_CRTC_STATUS_FRAME_COUNT …
#define mmCRTC4_CRTC_STATUS_FRAME_COUNT …
#define mmCRTC5_CRTC_STATUS_FRAME_COUNT …
#define mmCRTC_STATUS_VF_COUNT …
#define mmCRTC0_CRTC_STATUS_VF_COUNT …
#define mmCRTC1_CRTC_STATUS_VF_COUNT …
#define mmCRTC2_CRTC_STATUS_VF_COUNT …
#define mmCRTC3_CRTC_STATUS_VF_COUNT …
#define mmCRTC4_CRTC_STATUS_VF_COUNT …
#define mmCRTC5_CRTC_STATUS_VF_COUNT …
#define mmCRTC_STATUS_HV_COUNT …
#define mmCRTC0_CRTC_STATUS_HV_COUNT …
#define mmCRTC1_CRTC_STATUS_HV_COUNT …
#define mmCRTC2_CRTC_STATUS_HV_COUNT …
#define mmCRTC3_CRTC_STATUS_HV_COUNT …
#define mmCRTC4_CRTC_STATUS_HV_COUNT …
#define mmCRTC5_CRTC_STATUS_HV_COUNT …
#define mmCRTC_COUNT_CONTROL …
#define mmCRTC0_CRTC_COUNT_CONTROL …
#define mmCRTC1_CRTC_COUNT_CONTROL …
#define mmCRTC2_CRTC_COUNT_CONTROL …
#define mmCRTC3_CRTC_COUNT_CONTROL …
#define mmCRTC4_CRTC_COUNT_CONTROL …
#define mmCRTC5_CRTC_COUNT_CONTROL …
#define mmCRTC_COUNT_RESET …
#define mmCRTC0_CRTC_COUNT_RESET …
#define mmCRTC1_CRTC_COUNT_RESET …
#define mmCRTC2_CRTC_COUNT_RESET …
#define mmCRTC3_CRTC_COUNT_RESET …
#define mmCRTC4_CRTC_COUNT_RESET …
#define mmCRTC5_CRTC_COUNT_RESET …
#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE …
#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE …
#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE …
#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE …
#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE …
#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE …
#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE …
#define mmCRTC_VERT_SYNC_CONTROL …
#define mmCRTC0_CRTC_VERT_SYNC_CONTROL …
#define mmCRTC1_CRTC_VERT_SYNC_CONTROL …
#define mmCRTC2_CRTC_VERT_SYNC_CONTROL …
#define mmCRTC3_CRTC_VERT_SYNC_CONTROL …
#define mmCRTC4_CRTC_VERT_SYNC_CONTROL …
#define mmCRTC5_CRTC_VERT_SYNC_CONTROL …
#define mmCRTC_STEREO_STATUS …
#define mmCRTC0_CRTC_STEREO_STATUS …
#define mmCRTC1_CRTC_STEREO_STATUS …
#define mmCRTC2_CRTC_STEREO_STATUS …
#define mmCRTC3_CRTC_STEREO_STATUS …
#define mmCRTC4_CRTC_STEREO_STATUS …
#define mmCRTC5_CRTC_STEREO_STATUS …
#define mmCRTC_STEREO_CONTROL …
#define mmCRTC0_CRTC_STEREO_CONTROL …
#define mmCRTC1_CRTC_STEREO_CONTROL …
#define mmCRTC2_CRTC_STEREO_CONTROL …
#define mmCRTC3_CRTC_STEREO_CONTROL …
#define mmCRTC4_CRTC_STEREO_CONTROL …
#define mmCRTC5_CRTC_STEREO_CONTROL …
#define mmCRTC_SNAPSHOT_STATUS …
#define mmCRTC0_CRTC_SNAPSHOT_STATUS …
#define mmCRTC1_CRTC_SNAPSHOT_STATUS …
#define mmCRTC2_CRTC_SNAPSHOT_STATUS …
#define mmCRTC3_CRTC_SNAPSHOT_STATUS …
#define mmCRTC4_CRTC_SNAPSHOT_STATUS …
#define mmCRTC5_CRTC_SNAPSHOT_STATUS …
#define mmCRTC_SNAPSHOT_CONTROL …
#define mmCRTC0_CRTC_SNAPSHOT_CONTROL …
#define mmCRTC1_CRTC_SNAPSHOT_CONTROL …
#define mmCRTC2_CRTC_SNAPSHOT_CONTROL …
#define mmCRTC3_CRTC_SNAPSHOT_CONTROL …
#define mmCRTC4_CRTC_SNAPSHOT_CONTROL …
#define mmCRTC5_CRTC_SNAPSHOT_CONTROL …
#define mmCRTC_SNAPSHOT_POSITION …
#define mmCRTC0_CRTC_SNAPSHOT_POSITION …
#define mmCRTC1_CRTC_SNAPSHOT_POSITION …
#define mmCRTC2_CRTC_SNAPSHOT_POSITION …
#define mmCRTC3_CRTC_SNAPSHOT_POSITION …
#define mmCRTC4_CRTC_SNAPSHOT_POSITION …
#define mmCRTC5_CRTC_SNAPSHOT_POSITION …
#define mmCRTC_SNAPSHOT_FRAME …
#define mmCRTC0_CRTC_SNAPSHOT_FRAME …
#define mmCRTC1_CRTC_SNAPSHOT_FRAME …
#define mmCRTC2_CRTC_SNAPSHOT_FRAME …
#define mmCRTC3_CRTC_SNAPSHOT_FRAME …
#define mmCRTC4_CRTC_SNAPSHOT_FRAME …
#define mmCRTC5_CRTC_SNAPSHOT_FRAME …
#define mmCRTC_START_LINE_CONTROL …
#define mmCRTC0_CRTC_START_LINE_CONTROL …
#define mmCRTC1_CRTC_START_LINE_CONTROL …
#define mmCRTC2_CRTC_START_LINE_CONTROL …
#define mmCRTC3_CRTC_START_LINE_CONTROL …
#define mmCRTC4_CRTC_START_LINE_CONTROL …
#define mmCRTC5_CRTC_START_LINE_CONTROL …
#define mmCRTC_INTERRUPT_CONTROL …
#define mmCRTC0_CRTC_INTERRUPT_CONTROL …
#define mmCRTC1_CRTC_INTERRUPT_CONTROL …
#define mmCRTC2_CRTC_INTERRUPT_CONTROL …
#define mmCRTC3_CRTC_INTERRUPT_CONTROL …
#define mmCRTC4_CRTC_INTERRUPT_CONTROL …
#define mmCRTC5_CRTC_INTERRUPT_CONTROL …
#define mmCRTC_UPDATE_LOCK …
#define mmCRTC0_CRTC_UPDATE_LOCK …
#define mmCRTC1_CRTC_UPDATE_LOCK …
#define mmCRTC2_CRTC_UPDATE_LOCK …
#define mmCRTC3_CRTC_UPDATE_LOCK …
#define mmCRTC4_CRTC_UPDATE_LOCK …
#define mmCRTC5_CRTC_UPDATE_LOCK …
#define mmCRTC_DOUBLE_BUFFER_CONTROL …
#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL …
#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL …
#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL …
#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL …
#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL …
#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL …
#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE …
#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE …
#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE …
#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE …
#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE …
#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE …
#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE …
#define mmCRTC_TEST_PATTERN_CONTROL …
#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL …
#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL …
#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL …
#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL …
#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL …
#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL …
#define mmCRTC_TEST_PATTERN_PARAMETERS …
#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS …
#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS …
#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS …
#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS …
#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS …
#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS …
#define mmCRTC_TEST_PATTERN_COLOR …
#define mmCRTC0_CRTC_TEST_PATTERN_COLOR …
#define mmCRTC1_CRTC_TEST_PATTERN_COLOR …
#define mmCRTC2_CRTC_TEST_PATTERN_COLOR …
#define mmCRTC3_CRTC_TEST_PATTERN_COLOR …
#define mmCRTC4_CRTC_TEST_PATTERN_COLOR …
#define mmCRTC5_CRTC_TEST_PATTERN_COLOR …
#define mmMASTER_UPDATE_LOCK …
#define mmCRTC0_MASTER_UPDATE_LOCK …
#define mmCRTC1_MASTER_UPDATE_LOCK …
#define mmCRTC2_MASTER_UPDATE_LOCK …
#define mmCRTC3_MASTER_UPDATE_LOCK …
#define mmCRTC4_MASTER_UPDATE_LOCK …
#define mmCRTC5_MASTER_UPDATE_LOCK …
#define mmMASTER_UPDATE_MODE …
#define mmCRTC0_MASTER_UPDATE_MODE …
#define mmCRTC1_MASTER_UPDATE_MODE …
#define mmCRTC2_MASTER_UPDATE_MODE …
#define mmCRTC3_MASTER_UPDATE_MODE …
#define mmCRTC4_MASTER_UPDATE_MODE …
#define mmCRTC5_MASTER_UPDATE_MODE …
#define mmCRTC_MVP_INBAND_CNTL_INSERT …
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT …
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT …
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT …
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT …
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT …
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT …
#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER …
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER …
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER …
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER …
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER …
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER …
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER …
#define mmCRTC_MVP_STATUS …
#define mmCRTC0_CRTC_MVP_STATUS …
#define mmCRTC1_CRTC_MVP_STATUS …
#define mmCRTC2_CRTC_MVP_STATUS …
#define mmCRTC3_CRTC_MVP_STATUS …
#define mmCRTC4_CRTC_MVP_STATUS …
#define mmCRTC5_CRTC_MVP_STATUS …
#define mmCRTC_MASTER_EN …
#define mmCRTC0_CRTC_MASTER_EN …
#define mmCRTC1_CRTC_MASTER_EN …
#define mmCRTC2_CRTC_MASTER_EN …
#define mmCRTC3_CRTC_MASTER_EN …
#define mmCRTC4_CRTC_MASTER_EN …
#define mmCRTC5_CRTC_MASTER_EN …
#define mmCRTC_ALLOW_STOP_OFF_V_CNT …
#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT …
#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT …
#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT …
#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT …
#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT …
#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT …
#define mmCRTC_V_UPDATE_INT_STATUS …
#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS …
#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS …
#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS …
#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS …
#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS …
#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS …
#define mmCRTC_OVERSCAN_COLOR …
#define mmCRTC0_CRTC_OVERSCAN_COLOR …
#define mmCRTC1_CRTC_OVERSCAN_COLOR …
#define mmCRTC2_CRTC_OVERSCAN_COLOR …
#define mmCRTC3_CRTC_OVERSCAN_COLOR …
#define mmCRTC4_CRTC_OVERSCAN_COLOR …
#define mmCRTC5_CRTC_OVERSCAN_COLOR …
#define mmCRTC_OVERSCAN_COLOR_EXT …
#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT …
#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT …
#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT …
#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT …
#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT …
#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT …
#define mmCRTC_BLANK_DATA_COLOR …
#define mmCRTC0_CRTC_BLANK_DATA_COLOR …
#define mmCRTC1_CRTC_BLANK_DATA_COLOR …
#define mmCRTC2_CRTC_BLANK_DATA_COLOR …
#define mmCRTC3_CRTC_BLANK_DATA_COLOR …
#define mmCRTC4_CRTC_BLANK_DATA_COLOR …
#define mmCRTC5_CRTC_BLANK_DATA_COLOR …
#define mmCRTC_BLANK_DATA_COLOR_EXT …
#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT …
#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT …
#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT …
#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT …
#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT …
#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT …
#define mmCRTC_BLACK_COLOR …
#define mmCRTC0_CRTC_BLACK_COLOR …
#define mmCRTC1_CRTC_BLACK_COLOR …
#define mmCRTC2_CRTC_BLACK_COLOR …
#define mmCRTC3_CRTC_BLACK_COLOR …
#define mmCRTC4_CRTC_BLACK_COLOR …
#define mmCRTC5_CRTC_BLACK_COLOR …
#define mmCRTC_BLACK_COLOR_EXT …
#define mmCRTC0_CRTC_BLACK_COLOR_EXT …
#define mmCRTC1_CRTC_BLACK_COLOR_EXT …
#define mmCRTC2_CRTC_BLACK_COLOR_EXT …
#define mmCRTC3_CRTC_BLACK_COLOR_EXT …
#define mmCRTC4_CRTC_BLACK_COLOR_EXT …
#define mmCRTC5_CRTC_BLACK_COLOR_EXT …
#define mmCRTC_VERTICAL_INTERRUPT0_POSITION …
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION …
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION …
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION …
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION …
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION …
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION …
#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL …
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL …
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL …
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL …
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL …
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL …
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL …
#define mmCRTC_VERTICAL_INTERRUPT1_POSITION …
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION …
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION …
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION …
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION …
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION …
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION …
#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL …
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL …
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL …
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL …
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL …
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL …
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL …
#define mmCRTC_VERTICAL_INTERRUPT2_POSITION …
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION …
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION …
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION …
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION …
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION …
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION …
#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL …
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL …
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL …
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL …
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL …
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL …
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL …
#define mmCRTC_CRC_CNTL …
#define mmCRTC0_CRTC_CRC_CNTL …
#define mmCRTC1_CRTC_CRC_CNTL …
#define mmCRTC2_CRTC_CRC_CNTL …
#define mmCRTC3_CRTC_CRC_CNTL …
#define mmCRTC4_CRTC_CRC_CNTL …
#define mmCRTC5_CRTC_CRC_CNTL …
#define mmCRTC_CRC0_WINDOWA_X_CONTROL …
#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL …
#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL …
#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL …
#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL …
#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL …
#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL …
#define mmCRTC_CRC0_WINDOWA_Y_CONTROL …
#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL …
#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL …
#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL …
#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL …
#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL …
#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL …
#define mmCRTC_CRC0_WINDOWB_X_CONTROL …
#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL …
#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL …
#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL …
#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL …
#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL …
#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL …
#define mmCRTC_CRC0_WINDOWB_Y_CONTROL …
#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL …
#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL …
#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL …
#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL …
#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL …
#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL …
#define mmCRTC_CRC0_DATA_RG …
#define mmCRTC0_CRTC_CRC0_DATA_RG …
#define mmCRTC1_CRTC_CRC0_DATA_RG …
#define mmCRTC2_CRTC_CRC0_DATA_RG …
#define mmCRTC3_CRTC_CRC0_DATA_RG …
#define mmCRTC4_CRTC_CRC0_DATA_RG …
#define mmCRTC5_CRTC_CRC0_DATA_RG …
#define mmCRTC_CRC0_DATA_B …
#define mmCRTC0_CRTC_CRC0_DATA_B …
#define mmCRTC1_CRTC_CRC0_DATA_B …
#define mmCRTC2_CRTC_CRC0_DATA_B …
#define mmCRTC3_CRTC_CRC0_DATA_B …
#define mmCRTC4_CRTC_CRC0_DATA_B …
#define mmCRTC5_CRTC_CRC0_DATA_B …
#define mmCRTC_CRC1_WINDOWA_X_CONTROL …
#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL …
#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL …
#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL …
#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL …
#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL …
#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL …
#define mmCRTC_CRC1_WINDOWA_Y_CONTROL …
#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL …
#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL …
#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL …
#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL …
#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL …
#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL …
#define mmCRTC_CRC1_WINDOWB_X_CONTROL …
#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL …
#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL …
#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL …
#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL …
#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL …
#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL …
#define mmCRTC_CRC1_WINDOWB_Y_CONTROL …
#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL …
#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL …
#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL …
#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL …
#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL …
#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL …
#define mmCRTC_CRC1_DATA_RG …
#define mmCRTC0_CRTC_CRC1_DATA_RG …
#define mmCRTC1_CRTC_CRC1_DATA_RG …
#define mmCRTC2_CRTC_CRC1_DATA_RG …
#define mmCRTC3_CRTC_CRC1_DATA_RG …
#define mmCRTC4_CRTC_CRC1_DATA_RG …
#define mmCRTC5_CRTC_CRC1_DATA_RG …
#define mmCRTC_CRC1_DATA_B …
#define mmCRTC0_CRTC_CRC1_DATA_B …
#define mmCRTC1_CRTC_CRC1_DATA_B …
#define mmCRTC2_CRTC_CRC1_DATA_B …
#define mmCRTC3_CRTC_CRC1_DATA_B …
#define mmCRTC4_CRTC_CRC1_DATA_B …
#define mmCRTC5_CRTC_CRC1_DATA_B …
#define mmCRTC_EXT_TIMING_SYNC_CONTROL …
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL …
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL …
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL …
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL …
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL …
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL …
#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START …
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START …
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START …
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START …
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START …
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START …
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START …
#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END …
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END …
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END …
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END …
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END …
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END …
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END …
#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL …
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL …
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL …
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL …
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL …
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL …
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL …
#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL …
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL …
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL …
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL …
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL …
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL …
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL …
#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL …
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL …
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL …
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL …
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL …
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL …
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL …
#define mmCRTC_STATIC_SCREEN_CONTROL …
#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL …
#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL …
#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL …
#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL …
#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL …
#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL …
#define mmCRTC_3D_STRUCTURE_CONTROL …
#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL …
#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL …
#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL …
#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL …
#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL …
#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL …
#define mmCRTC_GSL_VSYNC_GAP …
#define mmCRTC0_CRTC_GSL_VSYNC_GAP …
#define mmCRTC1_CRTC_GSL_VSYNC_GAP …
#define mmCRTC2_CRTC_GSL_VSYNC_GAP …
#define mmCRTC3_CRTC_GSL_VSYNC_GAP …
#define mmCRTC4_CRTC_GSL_VSYNC_GAP …
#define mmCRTC5_CRTC_GSL_VSYNC_GAP …
#define mmCRTC_GSL_WINDOW …
#define mmCRTC0_CRTC_GSL_WINDOW …
#define mmCRTC1_CRTC_GSL_WINDOW …
#define mmCRTC2_CRTC_GSL_WINDOW …
#define mmCRTC3_CRTC_GSL_WINDOW …
#define mmCRTC4_CRTC_GSL_WINDOW …
#define mmCRTC5_CRTC_GSL_WINDOW …
#define mmCRTC_GSL_CONTROL …
#define mmCRTC0_CRTC_GSL_CONTROL …
#define mmCRTC1_CRTC_GSL_CONTROL …
#define mmCRTC2_CRTC_GSL_CONTROL …
#define mmCRTC3_CRTC_GSL_CONTROL …
#define mmCRTC4_CRTC_GSL_CONTROL …
#define mmCRTC5_CRTC_GSL_CONTROL …
#define mmCRTC_TEST_DEBUG_INDEX …
#define mmCRTC0_CRTC_TEST_DEBUG_INDEX …
#define mmCRTC1_CRTC_TEST_DEBUG_INDEX …
#define mmCRTC2_CRTC_TEST_DEBUG_INDEX …
#define mmCRTC3_CRTC_TEST_DEBUG_INDEX …
#define mmCRTC4_CRTC_TEST_DEBUG_INDEX …
#define mmCRTC5_CRTC_TEST_DEBUG_INDEX …
#define mmCRTC_TEST_DEBUG_DATA …
#define mmCRTC0_CRTC_TEST_DEBUG_DATA …
#define mmCRTC1_CRTC_TEST_DEBUG_DATA …
#define mmCRTC2_CRTC_TEST_DEBUG_DATA …
#define mmCRTC3_CRTC_TEST_DEBUG_DATA …
#define mmCRTC4_CRTC_TEST_DEBUG_DATA …
#define mmCRTC5_CRTC_TEST_DEBUG_DATA …
#define mmDAC_ENABLE …
#define mmDAC_SOURCE_SELECT …
#define mmDAC_CRC_EN …
#define mmDAC_CRC_CONTROL …
#define mmDAC_CRC_SIG_RGB_MASK …
#define mmDAC_CRC_SIG_CONTROL_MASK …
#define mmDAC_CRC_SIG_RGB …
#define mmDAC_CRC_SIG_CONTROL …
#define mmDAC_SYNC_TRISTATE_CONTROL …
#define mmDAC_STEREOSYNC_SELECT …
#define mmDAC_AUTODETECT_CONTROL …
#define mmDAC_AUTODETECT_CONTROL2 …
#define mmDAC_AUTODETECT_CONTROL3 …
#define mmDAC_AUTODETECT_STATUS …
#define mmDAC_AUTODETECT_INT_CONTROL …
#define mmDAC_FORCE_OUTPUT_CNTL …
#define mmDAC_FORCE_DATA …
#define mmDAC_POWERDOWN …
#define mmDAC_CONTROL …
#define mmDAC_COMPARATOR_ENABLE …
#define mmDAC_COMPARATOR_OUTPUT …
#define mmDAC_PWR_CNTL …
#define mmDAC_DFT_CONFIG …
#define mmDAC_FIFO_STATUS …
#define mmPERFCOUNTER_CNTL …
#define mmDC_PERFMON0_PERFCOUNTER_CNTL …
#define mmDC_PERFMON1_PERFCOUNTER_CNTL …
#define mmDC_PERFMON2_PERFCOUNTER_CNTL …
#define mmDC_PERFMON3_PERFCOUNTER_CNTL …
#define mmDC_PERFMON4_PERFCOUNTER_CNTL …
#define mmDC_PERFMON5_PERFCOUNTER_CNTL …
#define mmDC_PERFMON6_PERFCOUNTER_CNTL …
#define mmDC_PERFMON7_PERFCOUNTER_CNTL …
#define mmDC_PERFMON8_PERFCOUNTER_CNTL …
#define mmDC_PERFMON9_PERFCOUNTER_CNTL …
#define mmPERFCOUNTER_STATE …
#define mmDC_PERFMON0_PERFCOUNTER_STATE …
#define mmDC_PERFMON1_PERFCOUNTER_STATE …
#define mmDC_PERFMON2_PERFCOUNTER_STATE …
#define mmDC_PERFMON3_PERFCOUNTER_STATE …
#define mmDC_PERFMON4_PERFCOUNTER_STATE …
#define mmDC_PERFMON5_PERFCOUNTER_STATE …
#define mmDC_PERFMON6_PERFCOUNTER_STATE …
#define mmDC_PERFMON7_PERFCOUNTER_STATE …
#define mmDC_PERFMON8_PERFCOUNTER_STATE …
#define mmDC_PERFMON9_PERFCOUNTER_STATE …
#define mmPERFMON_CNTL …
#define mmDC_PERFMON0_PERFMON_CNTL …
#define mmDC_PERFMON1_PERFMON_CNTL …
#define mmDC_PERFMON2_PERFMON_CNTL …
#define mmDC_PERFMON3_PERFMON_CNTL …
#define mmDC_PERFMON4_PERFMON_CNTL …
#define mmDC_PERFMON5_PERFMON_CNTL …
#define mmDC_PERFMON6_PERFMON_CNTL …
#define mmDC_PERFMON7_PERFMON_CNTL …
#define mmDC_PERFMON8_PERFMON_CNTL …
#define mmDC_PERFMON9_PERFMON_CNTL …
#define mmPERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC …
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC …
#define mmPERFMON_CVALUE_LOW …
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW …
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW …
#define mmPERFMON_HI …
#define mmDC_PERFMON0_PERFMON_HI …
#define mmDC_PERFMON1_PERFMON_HI …
#define mmDC_PERFMON2_PERFMON_HI …
#define mmDC_PERFMON3_PERFMON_HI …
#define mmDC_PERFMON4_PERFMON_HI …
#define mmDC_PERFMON5_PERFMON_HI …
#define mmDC_PERFMON6_PERFMON_HI …
#define mmDC_PERFMON7_PERFMON_HI …
#define mmDC_PERFMON8_PERFMON_HI …
#define mmDC_PERFMON9_PERFMON_HI …
#define mmPERFMON_LOW …
#define mmDC_PERFMON0_PERFMON_LOW …
#define mmDC_PERFMON1_PERFMON_LOW …
#define mmDC_PERFMON2_PERFMON_LOW …
#define mmDC_PERFMON3_PERFMON_LOW …
#define mmDC_PERFMON4_PERFMON_LOW …
#define mmDC_PERFMON5_PERFMON_LOW …
#define mmDC_PERFMON6_PERFMON_LOW …
#define mmDC_PERFMON7_PERFMON_LOW …
#define mmDC_PERFMON8_PERFMON_LOW …
#define mmDC_PERFMON9_PERFMON_LOW …
#define mmPERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX …
#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX …
#define mmPERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA …
#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA …
#define mmVGA25_PPLL_REF_DIV …
#define mmVGA28_PPLL_REF_DIV …
#define mmVGA41_PPLL_REF_DIV …
#define mmVGA25_PPLL_FB_DIV …
#define mmVGA28_PPLL_FB_DIV …
#define mmVGA41_PPLL_FB_DIV …
#define mmVGA25_PPLL_POST_DIV …
#define mmVGA28_PPLL_POST_DIV …
#define mmVGA41_PPLL_POST_DIV …
#define mmVGA25_PPLL_ANALOG …
#define mmVGA28_PPLL_ANALOG …
#define mmVGA41_PPLL_ANALOG …
#define mmDPREFCLK_CNTL …
#define mmSCANIN_SOFT_RESET …
#define mmDCCG_GTC_CNTL …
#define mmDCCG_GTC_DTO_INCR …
#define mmDCCG_GTC_DTO_MODULO …
#define mmDCCG_GTC_CURRENT …
#define mmDCCG_DS_DTO_INCR …
#define mmDCCG_DS_DTO_MODULO …
#define mmDCCG_DS_CNTL …
#define mmDCCG_DS_HW_CAL_INTERVAL …
#define mmDCCG_DS_DEBUG_CNTL …
#define mmDMCU_SMU_INTERRUPT_CNTL …
#define mmSMU_CONTROL …
#define mmSMU_INTERRUPT_CONTROL …
#define mmDAC_CLK_ENABLE …
#define mmDVO_CLK_ENABLE …
#define mmDCCG_GATE_DISABLE_CNTL …
#define mmDISPCLK_CGTT_BLK_CTRL_REG …
#define mmSCLK_CGTT_BLK_CTRL_REG …
#define mmDCCG_CAC_STATUS …
#define mmPIXCLK1_RESYNC_CNTL …
#define mmPIXCLK2_RESYNC_CNTL …
#define mmPIXCLK0_RESYNC_CNTL …
#define mmMICROSECOND_TIME_BASE_DIV …
#define mmDCCG_DISP_CNTL_REG …
#define mmDISPPLL_BG_CNTL …
#define mmDIG_SOFT_RESET …
#define mmMILLISECOND_TIME_BASE_DIV …
#define mmDISPCLK_FREQ_CHANGE_CNTL …
#define mmLIGHT_SLEEP_CNTL …
#define mmDCCG_PERFMON_CNTL …
#define mmCRTC0_PIXEL_RATE_CNTL …
#define mmDP_DTO0_PHASE …
#define mmDP_DTO0_MODULO …
#define mmCRTC1_PIXEL_RATE_CNTL …
#define mmDP_DTO1_PHASE …
#define mmDP_DTO1_MODULO …
#define mmCRTC2_PIXEL_RATE_CNTL …
#define mmDP_DTO2_PHASE …
#define mmDP_DTO2_MODULO …
#define mmCRTC3_PIXEL_RATE_CNTL …
#define mmDP_DTO3_PHASE …
#define mmDP_DTO3_MODULO …
#define mmCRTC4_PIXEL_RATE_CNTL …
#define mmDP_DTO4_PHASE …
#define mmDP_DTO4_MODULO …
#define mmCRTC5_PIXEL_RATE_CNTL …
#define mmDP_DTO5_PHASE …
#define mmDP_DTO5_MODULO …
#define mmDCFE0_SOFT_RESET …
#define mmDCFE1_SOFT_RESET …
#define mmDCFE2_SOFT_RESET …
#define mmDCFE3_SOFT_RESET …
#define mmDCFE4_SOFT_RESET …
#define mmDCFE5_SOFT_RESET …
#define mmDCI_SOFT_RESET …
#define mmDCCG_SOFT_RESET …
#define mmSYMCLKA_CLOCK_ENABLE …
#define mmSYMCLKB_CLOCK_ENABLE …
#define mmSYMCLKC_CLOCK_ENABLE …
#define mmSYMCLKD_CLOCK_ENABLE …
#define mmSYMCLKE_CLOCK_ENABLE …
#define mmSYMCLKF_CLOCK_ENABLE …
#define mmSYMCLKG_CLOCK_ENABLE …
#define mmUNIPHY_SOFT_RESET …
#define mmDCO_SOFT_RESET …
#define mmDVOACLKD_CNTL …
#define mmDVOACLKC_MVP_CNTL …
#define mmDVOACLKC_CNTL …
#define mmDCCG_AUDIO_DTO_SOURCE …
#define mmDCCG_AUDIO_DTO0_PHASE …
#define mmDCCG_AUDIO_DTO0_MODULE …
#define mmDCCG_AUDIO_DTO1_PHASE …
#define mmDCCG_AUDIO_DTO1_MODULE …
#define mmDCCG_TEST_DEBUG_INDEX …
#define mmDCCG_TEST_DEBUG_DATA …
#define mmDCCG_TEST_CLK_SEL …
#define mmPLL_REF_DIV …
#define mmDCCG_PLL0_PLL_REF_DIV …
#define mmDCCG_PLL1_PLL_REF_DIV …
#define mmDCCG_PLL2_PLL_REF_DIV …
#define mmDCCG_PLL3_PLL_REF_DIV …
#define mmPLL_FB_DIV …
#define mmDCCG_PLL0_PLL_FB_DIV …
#define mmDCCG_PLL1_PLL_FB_DIV …
#define mmDCCG_PLL2_PLL_FB_DIV …
#define mmDCCG_PLL3_PLL_FB_DIV …
#define mmPLL_POST_DIV …
#define mmDCCG_PLL0_PLL_POST_DIV …
#define mmDCCG_PLL1_PLL_POST_DIV …
#define mmDCCG_PLL2_PLL_POST_DIV …
#define mmDCCG_PLL3_PLL_POST_DIV …
#define mmPLL_SS_AMOUNT_DSFRAC …
#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC …
#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC …
#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC …
#define mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC …
#define mmPLL_SS_CNTL …
#define mmDCCG_PLL0_PLL_SS_CNTL …
#define mmDCCG_PLL1_PLL_SS_CNTL …
#define mmDCCG_PLL2_PLL_SS_CNTL …
#define mmDCCG_PLL3_PLL_SS_CNTL …
#define mmPLL_DS_CNTL …
#define mmDCCG_PLL0_PLL_DS_CNTL …
#define mmDCCG_PLL1_PLL_DS_CNTL …
#define mmDCCG_PLL2_PLL_DS_CNTL …
#define mmDCCG_PLL3_PLL_DS_CNTL …
#define mmPLL_IDCLK_CNTL …
#define mmDCCG_PLL0_PLL_IDCLK_CNTL …
#define mmDCCG_PLL1_PLL_IDCLK_CNTL …
#define mmDCCG_PLL2_PLL_IDCLK_CNTL …
#define mmDCCG_PLL3_PLL_IDCLK_CNTL …
#define mmPLL_CNTL …
#define mmDCCG_PLL0_PLL_CNTL …
#define mmDCCG_PLL1_PLL_CNTL …
#define mmDCCG_PLL2_PLL_CNTL …
#define mmDCCG_PLL3_PLL_CNTL …
#define mmPLL_ANALOG …
#define mmDCCG_PLL0_PLL_ANALOG …
#define mmDCCG_PLL1_PLL_ANALOG …
#define mmDCCG_PLL2_PLL_ANALOG …
#define mmDCCG_PLL3_PLL_ANALOG …
#define mmPLL_ANALOG_CNTL …
#define mmDCCG_PLL0_PLL_ANALOG_CNTL …
#define mmDCCG_PLL1_PLL_ANALOG_CNTL …
#define mmDCCG_PLL2_PLL_ANALOG_CNTL …
#define mmDCCG_PLL3_PLL_ANALOG_CNTL …
#define mmPLL_VREG_CNTL …
#define mmDCCG_PLL0_PLL_VREG_CNTL …
#define mmDCCG_PLL1_PLL_VREG_CNTL …
#define mmDCCG_PLL2_PLL_VREG_CNTL …
#define mmDCCG_PLL3_PLL_VREG_CNTL …
#define mmPLL_XOR_LOCK …
#define mmDCCG_PLL0_PLL_XOR_LOCK …
#define mmDCCG_PLL1_PLL_XOR_LOCK …
#define mmDCCG_PLL2_PLL_XOR_LOCK …
#define mmDCCG_PLL3_PLL_XOR_LOCK …
#define mmPLL_UNLOCK_DETECT_CNTL …
#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL …
#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL …
#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL …
#define mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL …
#define mmPLL_DEBUG_CNTL …
#define mmDCCG_PLL0_PLL_DEBUG_CNTL …
#define mmDCCG_PLL1_PLL_DEBUG_CNTL …
#define mmDCCG_PLL2_PLL_DEBUG_CNTL …
#define mmDCCG_PLL3_PLL_DEBUG_CNTL …
#define mmPLL_UPDATE_LOCK …
#define mmDCCG_PLL0_PLL_UPDATE_LOCK …
#define mmDCCG_PLL1_PLL_UPDATE_LOCK …
#define mmDCCG_PLL2_PLL_UPDATE_LOCK …
#define mmDCCG_PLL3_PLL_UPDATE_LOCK …
#define mmPLL_UPDATE_CNTL …
#define mmDCCG_PLL0_PLL_UPDATE_CNTL …
#define mmDCCG_PLL1_PLL_UPDATE_CNTL …
#define mmDCCG_PLL2_PLL_UPDATE_CNTL …
#define mmDCCG_PLL3_PLL_UPDATE_CNTL …
#define mmPLL_DISPCLK_DTO_CNTL …
#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL …
#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL …
#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL …
#define mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL …
#define mmPLL_DISPCLK_CURRENT_DTO_PHASE …
#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE …
#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE …
#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE …
#define mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE …
#define mmDENTIST_DISPCLK_CNTL …
#define mmDCDEBUG_BUS_CLK1_SEL …
#define mmDCDEBUG_BUS_CLK2_SEL …
#define mmDCDEBUG_BUS_CLK3_SEL …
#define mmDCDEBUG_BUS_CLK4_SEL …
#define mmDCDEBUG_OUT_PIN_OVERRIDE …
#define mmDCDEBUG_OUT_CNTL …
#define mmDCDEBUG_OUT_DATA …
#define mmDMIF_ADDR_CONFIG …
#define mmDMIF_CONTROL …
#define mmDMIF_STATUS …
#define mmDMIF_HW_DEBUG …
#define mmDMIF_ARBITRATION_CONTROL …
#define mmPIPE0_ARBITRATION_CONTROL3 …
#define mmPIPE1_ARBITRATION_CONTROL3 …
#define mmPIPE2_ARBITRATION_CONTROL3 …
#define mmPIPE3_ARBITRATION_CONTROL3 …
#define mmPIPE4_ARBITRATION_CONTROL3 …
#define mmPIPE5_ARBITRATION_CONTROL3 …
#define mmDMIF_TEST_DEBUG_INDEX …
#define mmDMIF_TEST_DEBUG_DATA …
#define ixDMIF_DEBUG02_CORE0 …
#define ixDMIF_DEBUG02_CORE1 …
#define mmDMIF_ADDR_CALC …
#define mmDMIF_STATUS2 …
#define mmPIPE0_MAX_REQUESTS …
#define mmPIPE1_MAX_REQUESTS …
#define mmPIPE2_MAX_REQUESTS …
#define mmPIPE3_MAX_REQUESTS …
#define mmPIPE4_MAX_REQUESTS …
#define mmPIPE5_MAX_REQUESTS …
#define mmLOW_POWER_TILING_CONTROL …
#define mmMCIF_CONTROL …
#define mmMCIF_WRITE_COMBINE_CONTROL …
#define mmMCIF_TEST_DEBUG_INDEX …
#define mmMCIF_TEST_DEBUG_DATA …
#define ixIDDCCIF02_DBG_DCCIF_C …
#define ixIDDCCIF04_DBG_DCCIF_E …
#define ixIDDCCIF05_DBG_DCCIF_F …
#define mmMCIF_VMID …
#define mmMCIF_MEM_CONTROL …
#define mmCC_DC_PIPE_DIS …
#define mmMC_DC_INTERFACE_NACK_STATUS …
#define mmDC_RBBMIF_RDWR_CNTL1 …
#define mmDC_RBBMIF_RDWR_CNTL2 …
#define mmDC_RBBMIF_RDWR_CNTL3 …
#define mmDCI_MEM_PWR_STATE …
#define mmDCI_MEM_PWR_STATE2 …
#define mmDCI_CLK_CNTL …
#define mmDCCG_VPCLK_CNTL …
#define mmDCI_MEM_PWR_CNTL …
#define mmDC_XDMA_INTERFACE_CNTL …
#define mmDCI_TEST_DEBUG_INDEX …
#define mmDCI_TEST_DEBUG_DATA …
#define mmDCI_DEBUG_CONFIG …
#define mmPIPE0_DMIF_BUFFER_CONTROL …
#define mmPIPE1_DMIF_BUFFER_CONTROL …
#define mmPIPE2_DMIF_BUFFER_CONTROL …
#define mmPIPE3_DMIF_BUFFER_CONTROL …
#define mmPIPE4_DMIF_BUFFER_CONTROL …
#define mmPIPE5_DMIF_BUFFER_CONTROL …
#define mmMCIF_BUFMGR_SW_CONTROL …
#define mmMCIF_BUFMGR_STATUS …
#define mmMCIF_BUF_PITCH …
#define mmMCIF_BUF_1_ADDR_Y_LOW …
#define mmMCIF_BUF_2_ADDR_Y_LOW …
#define mmMCIF_BUF_3_ADDR_Y_LOW …
#define mmMCIF_BUF_4_ADDR_Y_LOW …
#define mmMCIF_BUF_1_ADDR_UP …
#define mmMCIF_BUF_2_ADDR_UP …
#define mmMCIF_BUF_3_ADDR_UP …
#define mmMCIF_BUF_4_ADDR_UP …
#define mmMCIF_BUF_1_ADDR_C_LOW …
#define mmMCIF_BUF_2_ADDR_C_LOW …
#define mmMCIF_BUF_3_ADDR_C_LOW …
#define mmMCIF_BUF_4_ADDR_C_LOW …
#define mmMCIF_BUF_1_STATUS …
#define mmMCIF_BUF_2_STATUS …
#define mmMCIF_BUF_3_STATUS …
#define mmMCIF_BUF_4_STATUS …
#define mmMCIF_SI_ARBITRATION_CONTROL …
#define mmMCIF_URGENCY_WATERMARK …
#define mmDC_GENERICA …
#define mmDC_GENERICB …
#define mmDC_PAD_EXTERN_SIG …
#define mmDC_REF_CLK_CNTL …
#define mmDC_GPIO_DEBUG …
#define mmDCO_MEM_POWER_STATE …
#define mmDCO_MEM_POWER_STATE_2 …
#define mmDCO_LIGHT_SLEEP_DIS …
#define mmUNIPHY_IMPCAL_LINKA …
#define mmUNIPHY_IMPCAL_LINKB …
#define mmUNIPHY_IMPCAL_PERIOD …
#define mmAUXP_IMPCAL …
#define mmAUXN_IMPCAL …
#define mmDCIO_IMPCAL_CNTL_AB …
#define mmUNIPHY_IMPCAL_PSW_AB …
#define mmUNIPHY_IMPCAL_LINKC …
#define mmUNIPHY_IMPCAL_LINKD …
#define mmDCIO_IMPCAL_CNTL_CD …
#define mmUNIPHY_IMPCAL_PSW_CD …
#define mmUNIPHY_IMPCAL_LINKE …
#define mmUNIPHY_IMPCAL_LINKF …
#define mmDCIO_IMPCAL_CNTL_EF …
#define mmUNIPHY_IMPCAL_PSW_EF …
#define mmDC_PINSTRAPS …
#define mmDC_DVODATA_CONFIG …
#define mmLVTMA_PWRSEQ_CNTL …
#define mmLVTMA_PWRSEQ_STATE …
#define mmLVTMA_PWRSEQ_REF_DIV …
#define mmLVTMA_PWRSEQ_DELAY1 …
#define mmLVTMA_PWRSEQ_DELAY2 …
#define mmBL_PWM_CNTL …
#define mmBL_PWM_CNTL2 …
#define mmBL_PWM_PERIOD_CNTL …
#define mmBL_PWM_GRP1_REG_LOCK …
#define mmDCIO_GSL_GENLK_PAD_CNTL …
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL …
#define mmDCIO_GSL0_CNTL …
#define mmDCIO_GSL1_CNTL …
#define mmDCIO_GSL2_CNTL …
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE …
#define mmDC_GPU_TIMER_START_POSITION_P_FLIP …
#define mmDC_GPU_TIMER_READ …
#define mmDC_GPU_TIMER_READ_CNTL …
#define mmDCO_CLK_CNTL …
#define mmDCO_CLK_RAMP_CNTL …
#define mmDCIO_DEBUG …
#define mmDCO_DCFE_EXT_VSYNC_CNTL …
#define mmDCIO_TEST_DEBUG_INDEX …
#define mmDCIO_TEST_DEBUG_DATA …
#define ixDCIO_DEBUG1 …
#define ixDCIO_DEBUG2 …
#define ixDCIO_DEBUG3 …
#define ixDCIO_DEBUG4 …
#define ixDCIO_DEBUG5 …
#define ixDCIO_DEBUG6 …
#define ixDCIO_DEBUG7 …
#define ixDCIO_DEBUG8 …
#define ixDCIO_DEBUG9 …
#define ixDCIO_DEBUGA …
#define ixDCIO_DEBUGB …
#define ixDCIO_DEBUGC …
#define ixDCIO_DEBUGD …
#define ixDCIO_DEBUGE …
#define ixDCIO_DEBUGF …
#define ixDCIO_DEBUG10 …
#define ixDCIO_DEBUG11 …
#define ixDCIO_DEBUG12 …
#define ixDCIO_DEBUG13 …
#define ixDCIO_DEBUG14 …
#define ixDCIO_DEBUG15 …
#define ixDCIO_DEBUG_ID …
#define mmDC_GPIO_GENERIC_MASK …
#define mmDC_GPIO_GENERIC_A …
#define mmDC_GPIO_GENERIC_EN …
#define mmDC_GPIO_GENERIC_Y …
#define mmDC_GPIO_DVODATA_MASK …
#define mmDC_GPIO_DVODATA_A …
#define mmDC_GPIO_DVODATA_EN …
#define mmDC_GPIO_DVODATA_Y …
#define mmDC_GPIO_DDC1_MASK …
#define mmDC_GPIO_DDC1_A …
#define mmDC_GPIO_DDC1_EN …
#define mmDC_GPIO_DDC1_Y …
#define mmDC_GPIO_DDC2_MASK …
#define mmDC_GPIO_DDC2_A …
#define mmDC_GPIO_DDC2_EN …
#define mmDC_GPIO_DDC2_Y …
#define mmDC_GPIO_DDC3_MASK …
#define mmDC_GPIO_DDC3_A …
#define mmDC_GPIO_DDC3_EN …
#define mmDC_GPIO_DDC3_Y …
#define mmDC_GPIO_DDC4_MASK …
#define mmDC_GPIO_DDC4_A …
#define mmDC_GPIO_DDC4_EN …
#define mmDC_GPIO_DDC4_Y …
#define mmDC_GPIO_DDC5_MASK …
#define mmDC_GPIO_DDC5_A …
#define mmDC_GPIO_DDC5_EN …
#define mmDC_GPIO_DDC5_Y …
#define mmDC_GPIO_DDC6_MASK …
#define mmDC_GPIO_DDC6_A …
#define mmDC_GPIO_DDC6_EN …
#define mmDC_GPIO_DDC6_Y …
#define mmDC_GPIO_DDCVGA_MASK …
#define mmDC_GPIO_DDCVGA_A …
#define mmDC_GPIO_DDCVGA_EN …
#define mmDC_GPIO_DDCVGA_Y …
#define mmDC_GPIO_SYNCA_MASK …
#define mmDC_GPIO_SYNCA_A …
#define mmDC_GPIO_SYNCA_EN …
#define mmDC_GPIO_SYNCA_Y …
#define mmDC_GPIO_GENLK_MASK …
#define mmDC_GPIO_GENLK_A …
#define mmDC_GPIO_GENLK_EN …
#define mmDC_GPIO_GENLK_Y …
#define mmDC_GPIO_HPD_MASK …
#define mmDC_GPIO_HPD_A …
#define mmDC_GPIO_HPD_EN …
#define mmDC_GPIO_HPD_Y …
#define mmDC_GPIO_PWRSEQ_MASK …
#define mmDC_GPIO_PWRSEQ_A …
#define mmDC_GPIO_PWRSEQ_EN …
#define mmDC_GPIO_PWRSEQ_Y …
#define mmDC_GPIO_PAD_STRENGTH_1 …
#define mmDC_GPIO_PAD_STRENGTH_2 …
#define mmPHY_AUX_CNTL …
#define mmDC_GPIO_I2CPAD_MASK …
#define mmDC_GPIO_I2CPAD_A …
#define mmDC_GPIO_I2CPAD_EN …
#define mmDC_GPIO_I2CPAD_Y …
#define mmDC_GPIO_I2CPAD_STRENGTH …
#define mmDVO_STRENGTH_CONTROL …
#define mmDVO_VREF_CONTROL …
#define mmDVO_SKEW_ADJUST …
#define mmUNIPHYAB_TPG_CONTROL …
#define mmUNIPHYAB_TPG_SEED …
#define mmUNIPHYCD_TPG_CONTROL …
#define mmUNIPHYCD_TPG_SEED …
#define mmUNIPHYEF_TPG_CONTROL …
#define mmUNIPHYEF_TPG_SEED …
#define mmUNIPHYGH_TPG_CONTROL …
#define mmUNIPHYGH_TPG_SEED …
#define mmDC_GPIO_I2S_SPDIF_MASK …
#define mmDC_GPIO_I2S_SPDIF_A …
#define mmDC_GPIO_I2S_SPDIF_EN …
#define mmDC_GPIO_I2S_SPDIF_Y …
#define mmDC_GPIO_I2S_SPDIF_STRENGTH …
#define mmDAC_MACRO_CNTL_RESERVED0 …
#define mmDAC_MACRO_CNTL_RESERVED1 …
#define mmDAC_MACRO_CNTL_RESERVED2 …
#define mmDAC_MACRO_CNTL_RESERVED3 …
#define mmUNIPHY_TX_CONTROL1 …
#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 …
#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 …
#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 …
#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 …
#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 …
#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 …
#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 …
#define mmUNIPHY_TX_CONTROL2 …
#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 …
#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 …
#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 …
#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 …
#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 …
#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 …
#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 …
#define mmUNIPHY_TX_CONTROL3 …
#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 …
#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 …
#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 …
#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 …
#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 …
#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 …
#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 …
#define mmUNIPHY_TX_CONTROL4 …
#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 …
#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 …
#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 …
#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 …
#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 …
#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 …
#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 …
#define mmUNIPHY_POWER_CONTROL …
#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL …
#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL …
#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL …
#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL …
#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL …
#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL …
#define mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL …
#define mmUNIPHY_PLL_FBDIV …
#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV …
#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV …
#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV …
#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV …
#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV …
#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV …
#define mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV …
#define mmUNIPHY_PLL_CONTROL1 …
#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 …
#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 …
#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 …
#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 …
#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 …
#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 …
#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 …
#define mmUNIPHY_PLL_CONTROL2 …
#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 …
#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 …
#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 …
#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 …
#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 …
#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 …
#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 …
#define mmUNIPHY_PLL_SS_STEP_SIZE …
#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE …
#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE …
#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE …
#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE …
#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE …
#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE …
#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE …
#define mmUNIPHY_PLL_SS_CNTL …
#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL …
#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL …
#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL …
#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL …
#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL …
#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL …
#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL …
#define mmUNIPHY_DATA_SYNCHRONIZATION …
#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION …
#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION …
#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION …
#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION …
#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION …
#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION …
#define mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION …
#define mmUNIPHY_REG_TEST_OUTPUT …
#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT …
#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT …
#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT …
#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT …
#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT …
#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT …
#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT …
#define mmUNIPHY_ANG_BIST_CNTL …
#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL …
#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL …
#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL …
#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL …
#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL …
#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL …
#define mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL …
#define mmUNIPHY_LINK_CNTL …
#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL …
#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL …
#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL …
#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL …
#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL …
#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL …
#define mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL …
#define mmUNIPHY_CHANNEL_XBAR_CNTL …
#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL …
#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL …
#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL …
#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL …
#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL …
#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL …
#define mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL …
#define mmUNIPHY_REG_TEST_OUTPUT2 …
#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 …
#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 …
#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 …
#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 …
#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 …
#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 …
#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 …
#define mmGRPH_ENABLE …
#define mmDCP0_GRPH_ENABLE …
#define mmDCP1_GRPH_ENABLE …
#define mmDCP2_GRPH_ENABLE …
#define mmDCP3_GRPH_ENABLE …
#define mmDCP4_GRPH_ENABLE …
#define mmDCP5_GRPH_ENABLE …
#define mmGRPH_CONTROL …
#define mmDCP0_GRPH_CONTROL …
#define mmDCP1_GRPH_CONTROL …
#define mmDCP2_GRPH_CONTROL …
#define mmDCP3_GRPH_CONTROL …
#define mmDCP4_GRPH_CONTROL …
#define mmDCP5_GRPH_CONTROL …
#define mmGRPH_LUT_10BIT_BYPASS …
#define mmDCP0_GRPH_LUT_10BIT_BYPASS …
#define mmDCP1_GRPH_LUT_10BIT_BYPASS …
#define mmDCP2_GRPH_LUT_10BIT_BYPASS …
#define mmDCP3_GRPH_LUT_10BIT_BYPASS …
#define mmDCP4_GRPH_LUT_10BIT_BYPASS …
#define mmDCP5_GRPH_LUT_10BIT_BYPASS …
#define mmGRPH_SWAP_CNTL …
#define mmDCP0_GRPH_SWAP_CNTL …
#define mmDCP1_GRPH_SWAP_CNTL …
#define mmDCP2_GRPH_SWAP_CNTL …
#define mmDCP3_GRPH_SWAP_CNTL …
#define mmDCP4_GRPH_SWAP_CNTL …
#define mmDCP5_GRPH_SWAP_CNTL …
#define mmGRPH_PRIMARY_SURFACE_ADDRESS …
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS …
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS …
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS …
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS …
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS …
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS …
#define mmGRPH_SECONDARY_SURFACE_ADDRESS …
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS …
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS …
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS …
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS …
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS …
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS …
#define mmGRPH_PITCH …
#define mmDCP0_GRPH_PITCH …
#define mmDCP1_GRPH_PITCH …
#define mmDCP2_GRPH_PITCH …
#define mmDCP3_GRPH_PITCH …
#define mmDCP4_GRPH_PITCH …
#define mmDCP5_GRPH_PITCH …
#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH …
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH …
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH …
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH …
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH …
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH …
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH …
#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmGRPH_SURFACE_OFFSET_X …
#define mmDCP0_GRPH_SURFACE_OFFSET_X …
#define mmDCP1_GRPH_SURFACE_OFFSET_X …
#define mmDCP2_GRPH_SURFACE_OFFSET_X …
#define mmDCP3_GRPH_SURFACE_OFFSET_X …
#define mmDCP4_GRPH_SURFACE_OFFSET_X …
#define mmDCP5_GRPH_SURFACE_OFFSET_X …
#define mmGRPH_SURFACE_OFFSET_Y …
#define mmDCP0_GRPH_SURFACE_OFFSET_Y …
#define mmDCP1_GRPH_SURFACE_OFFSET_Y …
#define mmDCP2_GRPH_SURFACE_OFFSET_Y …
#define mmDCP3_GRPH_SURFACE_OFFSET_Y …
#define mmDCP4_GRPH_SURFACE_OFFSET_Y …
#define mmDCP5_GRPH_SURFACE_OFFSET_Y …
#define mmGRPH_X_START …
#define mmDCP0_GRPH_X_START …
#define mmDCP1_GRPH_X_START …
#define mmDCP2_GRPH_X_START …
#define mmDCP3_GRPH_X_START …
#define mmDCP4_GRPH_X_START …
#define mmDCP5_GRPH_X_START …
#define mmGRPH_Y_START …
#define mmDCP0_GRPH_Y_START …
#define mmDCP1_GRPH_Y_START …
#define mmDCP2_GRPH_Y_START …
#define mmDCP3_GRPH_Y_START …
#define mmDCP4_GRPH_Y_START …
#define mmDCP5_GRPH_Y_START …
#define mmGRPH_X_END …
#define mmDCP0_GRPH_X_END …
#define mmDCP1_GRPH_X_END …
#define mmDCP2_GRPH_X_END …
#define mmDCP3_GRPH_X_END …
#define mmDCP4_GRPH_X_END …
#define mmDCP5_GRPH_X_END …
#define mmGRPH_Y_END …
#define mmDCP0_GRPH_Y_END …
#define mmDCP1_GRPH_Y_END …
#define mmDCP2_GRPH_Y_END …
#define mmDCP3_GRPH_Y_END …
#define mmDCP4_GRPH_Y_END …
#define mmDCP5_GRPH_Y_END …
#define mmINPUT_GAMMA_CONTROL …
#define mmDCP0_INPUT_GAMMA_CONTROL …
#define mmDCP1_INPUT_GAMMA_CONTROL …
#define mmDCP2_INPUT_GAMMA_CONTROL …
#define mmDCP3_INPUT_GAMMA_CONTROL …
#define mmDCP4_INPUT_GAMMA_CONTROL …
#define mmDCP5_INPUT_GAMMA_CONTROL …
#define mmGRPH_UPDATE …
#define mmDCP0_GRPH_UPDATE …
#define mmDCP1_GRPH_UPDATE …
#define mmDCP2_GRPH_UPDATE …
#define mmDCP3_GRPH_UPDATE …
#define mmDCP4_GRPH_UPDATE …
#define mmDCP5_GRPH_UPDATE …
#define mmGRPH_FLIP_CONTROL …
#define mmDCP0_GRPH_FLIP_CONTROL …
#define mmDCP1_GRPH_FLIP_CONTROL …
#define mmDCP2_GRPH_FLIP_CONTROL …
#define mmDCP3_GRPH_FLIP_CONTROL …
#define mmDCP4_GRPH_FLIP_CONTROL …
#define mmDCP5_GRPH_FLIP_CONTROL …
#define mmGRPH_SURFACE_ADDRESS_INUSE …
#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE …
#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE …
#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE …
#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE …
#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE …
#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE …
#define mmGRPH_DFQ_CONTROL …
#define mmDCP0_GRPH_DFQ_CONTROL …
#define mmDCP1_GRPH_DFQ_CONTROL …
#define mmDCP2_GRPH_DFQ_CONTROL …
#define mmDCP3_GRPH_DFQ_CONTROL …
#define mmDCP4_GRPH_DFQ_CONTROL …
#define mmDCP5_GRPH_DFQ_CONTROL …
#define mmGRPH_DFQ_STATUS …
#define mmDCP0_GRPH_DFQ_STATUS …
#define mmDCP1_GRPH_DFQ_STATUS …
#define mmDCP2_GRPH_DFQ_STATUS …
#define mmDCP3_GRPH_DFQ_STATUS …
#define mmDCP4_GRPH_DFQ_STATUS …
#define mmDCP5_GRPH_DFQ_STATUS …
#define mmGRPH_INTERRUPT_STATUS …
#define mmDCP0_GRPH_INTERRUPT_STATUS …
#define mmDCP1_GRPH_INTERRUPT_STATUS …
#define mmDCP2_GRPH_INTERRUPT_STATUS …
#define mmDCP3_GRPH_INTERRUPT_STATUS …
#define mmDCP4_GRPH_INTERRUPT_STATUS …
#define mmDCP5_GRPH_INTERRUPT_STATUS …
#define mmGRPH_INTERRUPT_CONTROL …
#define mmDCP0_GRPH_INTERRUPT_CONTROL …
#define mmDCP1_GRPH_INTERRUPT_CONTROL …
#define mmDCP2_GRPH_INTERRUPT_CONTROL …
#define mmDCP3_GRPH_INTERRUPT_CONTROL …
#define mmDCP4_GRPH_INTERRUPT_CONTROL …
#define mmDCP5_GRPH_INTERRUPT_CONTROL …
#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE …
#define mmGRPH_COMPRESS_SURFACE_ADDRESS …
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS …
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS …
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS …
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS …
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS …
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS …
#define mmGRPH_COMPRESS_PITCH …
#define mmDCP0_GRPH_COMPRESS_PITCH …
#define mmDCP1_GRPH_COMPRESS_PITCH …
#define mmDCP2_GRPH_COMPRESS_PITCH …
#define mmDCP3_GRPH_COMPRESS_PITCH …
#define mmDCP4_GRPH_COMPRESS_PITCH …
#define mmDCP5_GRPH_COMPRESS_PITCH …
#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH …
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH …
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH …
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH …
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH …
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH …
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH …
#define mmOVL_ENABLE …
#define mmDCP0_OVL_ENABLE …
#define mmDCP1_OVL_ENABLE …
#define mmDCP2_OVL_ENABLE …
#define mmDCP3_OVL_ENABLE …
#define mmDCP4_OVL_ENABLE …
#define mmDCP5_OVL_ENABLE …
#define mmOVL_CONTROL1 …
#define mmDCP0_OVL_CONTROL1 …
#define mmDCP1_OVL_CONTROL1 …
#define mmDCP2_OVL_CONTROL1 …
#define mmDCP3_OVL_CONTROL1 …
#define mmDCP4_OVL_CONTROL1 …
#define mmDCP5_OVL_CONTROL1 …
#define mmOVL_CONTROL2 …
#define mmDCP0_OVL_CONTROL2 …
#define mmDCP1_OVL_CONTROL2 …
#define mmDCP2_OVL_CONTROL2 …
#define mmDCP3_OVL_CONTROL2 …
#define mmDCP4_OVL_CONTROL2 …
#define mmDCP5_OVL_CONTROL2 …
#define mmOVL_SWAP_CNTL …
#define mmDCP0_OVL_SWAP_CNTL …
#define mmDCP1_OVL_SWAP_CNTL …
#define mmDCP2_OVL_SWAP_CNTL …
#define mmDCP3_OVL_SWAP_CNTL …
#define mmDCP4_OVL_SWAP_CNTL …
#define mmDCP5_OVL_SWAP_CNTL …
#define mmOVL_SURFACE_ADDRESS …
#define mmDCP0_OVL_SURFACE_ADDRESS …
#define mmDCP1_OVL_SURFACE_ADDRESS …
#define mmDCP2_OVL_SURFACE_ADDRESS …
#define mmDCP3_OVL_SURFACE_ADDRESS …
#define mmDCP4_OVL_SURFACE_ADDRESS …
#define mmDCP5_OVL_SURFACE_ADDRESS …
#define mmOVL_PITCH …
#define mmDCP0_OVL_PITCH …
#define mmDCP1_OVL_PITCH …
#define mmDCP2_OVL_PITCH …
#define mmDCP3_OVL_PITCH …
#define mmDCP4_OVL_PITCH …
#define mmDCP5_OVL_PITCH …
#define mmOVL_SURFACE_ADDRESS_HIGH …
#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH …
#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH …
#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH …
#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH …
#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH …
#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH …
#define mmOVL_SURFACE_OFFSET_X …
#define mmDCP0_OVL_SURFACE_OFFSET_X …
#define mmDCP1_OVL_SURFACE_OFFSET_X …
#define mmDCP2_OVL_SURFACE_OFFSET_X …
#define mmDCP3_OVL_SURFACE_OFFSET_X …
#define mmDCP4_OVL_SURFACE_OFFSET_X …
#define mmDCP5_OVL_SURFACE_OFFSET_X …
#define mmOVL_SURFACE_OFFSET_Y …
#define mmDCP0_OVL_SURFACE_OFFSET_Y …
#define mmDCP1_OVL_SURFACE_OFFSET_Y …
#define mmDCP2_OVL_SURFACE_OFFSET_Y …
#define mmDCP3_OVL_SURFACE_OFFSET_Y …
#define mmDCP4_OVL_SURFACE_OFFSET_Y …
#define mmDCP5_OVL_SURFACE_OFFSET_Y …
#define mmOVL_START …
#define mmDCP0_OVL_START …
#define mmDCP1_OVL_START …
#define mmDCP2_OVL_START …
#define mmDCP3_OVL_START …
#define mmDCP4_OVL_START …
#define mmDCP5_OVL_START …
#define mmOVL_END …
#define mmDCP0_OVL_END …
#define mmDCP1_OVL_END …
#define mmDCP2_OVL_END …
#define mmDCP3_OVL_END …
#define mmDCP4_OVL_END …
#define mmDCP5_OVL_END …
#define mmOVL_UPDATE …
#define mmDCP0_OVL_UPDATE …
#define mmDCP1_OVL_UPDATE …
#define mmDCP2_OVL_UPDATE …
#define mmDCP3_OVL_UPDATE …
#define mmDCP4_OVL_UPDATE …
#define mmDCP5_OVL_UPDATE …
#define mmOVL_SURFACE_ADDRESS_INUSE …
#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE …
#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE …
#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE …
#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE …
#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE …
#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE …
#define mmOVL_DFQ_CONTROL …
#define mmDCP0_OVL_DFQ_CONTROL …
#define mmDCP1_OVL_DFQ_CONTROL …
#define mmDCP2_OVL_DFQ_CONTROL …
#define mmDCP3_OVL_DFQ_CONTROL …
#define mmDCP4_OVL_DFQ_CONTROL …
#define mmDCP5_OVL_DFQ_CONTROL …
#define mmOVL_DFQ_STATUS …
#define mmDCP0_OVL_DFQ_STATUS …
#define mmDCP1_OVL_DFQ_STATUS …
#define mmDCP2_OVL_DFQ_STATUS …
#define mmDCP3_OVL_DFQ_STATUS …
#define mmDCP4_OVL_DFQ_STATUS …
#define mmDCP5_OVL_DFQ_STATUS …
#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE …
#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE …
#define mmOVLSCL_EDGE_PIXEL_CNTL …
#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL …
#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL …
#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL …
#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL …
#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL …
#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL …
#define mmPRESCALE_GRPH_CONTROL …
#define mmDCP0_PRESCALE_GRPH_CONTROL …
#define mmDCP1_PRESCALE_GRPH_CONTROL …
#define mmDCP2_PRESCALE_GRPH_CONTROL …
#define mmDCP3_PRESCALE_GRPH_CONTROL …
#define mmDCP4_PRESCALE_GRPH_CONTROL …
#define mmDCP5_PRESCALE_GRPH_CONTROL …
#define mmPRESCALE_VALUES_GRPH_R …
#define mmDCP0_PRESCALE_VALUES_GRPH_R …
#define mmDCP1_PRESCALE_VALUES_GRPH_R …
#define mmDCP2_PRESCALE_VALUES_GRPH_R …
#define mmDCP3_PRESCALE_VALUES_GRPH_R …
#define mmDCP4_PRESCALE_VALUES_GRPH_R …
#define mmDCP5_PRESCALE_VALUES_GRPH_R …
#define mmPRESCALE_VALUES_GRPH_G …
#define mmDCP0_PRESCALE_VALUES_GRPH_G …
#define mmDCP1_PRESCALE_VALUES_GRPH_G …
#define mmDCP2_PRESCALE_VALUES_GRPH_G …
#define mmDCP3_PRESCALE_VALUES_GRPH_G …
#define mmDCP4_PRESCALE_VALUES_GRPH_G …
#define mmDCP5_PRESCALE_VALUES_GRPH_G …
#define mmPRESCALE_VALUES_GRPH_B …
#define mmDCP0_PRESCALE_VALUES_GRPH_B …
#define mmDCP1_PRESCALE_VALUES_GRPH_B …
#define mmDCP2_PRESCALE_VALUES_GRPH_B …
#define mmDCP3_PRESCALE_VALUES_GRPH_B …
#define mmDCP4_PRESCALE_VALUES_GRPH_B …
#define mmDCP5_PRESCALE_VALUES_GRPH_B …
#define mmPRESCALE_OVL_CONTROL …
#define mmDCP0_PRESCALE_OVL_CONTROL …
#define mmDCP1_PRESCALE_OVL_CONTROL …
#define mmDCP2_PRESCALE_OVL_CONTROL …
#define mmDCP3_PRESCALE_OVL_CONTROL …
#define mmDCP4_PRESCALE_OVL_CONTROL …
#define mmDCP5_PRESCALE_OVL_CONTROL …
#define mmPRESCALE_VALUES_OVL_CB …
#define mmDCP0_PRESCALE_VALUES_OVL_CB …
#define mmDCP1_PRESCALE_VALUES_OVL_CB …
#define mmDCP2_PRESCALE_VALUES_OVL_CB …
#define mmDCP3_PRESCALE_VALUES_OVL_CB …
#define mmDCP4_PRESCALE_VALUES_OVL_CB …
#define mmDCP5_PRESCALE_VALUES_OVL_CB …
#define mmPRESCALE_VALUES_OVL_Y …
#define mmDCP0_PRESCALE_VALUES_OVL_Y …
#define mmDCP1_PRESCALE_VALUES_OVL_Y …
#define mmDCP2_PRESCALE_VALUES_OVL_Y …
#define mmDCP3_PRESCALE_VALUES_OVL_Y …
#define mmDCP4_PRESCALE_VALUES_OVL_Y …
#define mmDCP5_PRESCALE_VALUES_OVL_Y …
#define mmPRESCALE_VALUES_OVL_CR …
#define mmDCP0_PRESCALE_VALUES_OVL_CR …
#define mmDCP1_PRESCALE_VALUES_OVL_CR …
#define mmDCP2_PRESCALE_VALUES_OVL_CR …
#define mmDCP3_PRESCALE_VALUES_OVL_CR …
#define mmDCP4_PRESCALE_VALUES_OVL_CR …
#define mmDCP5_PRESCALE_VALUES_OVL_CR …
#define mmINPUT_CSC_CONTROL …
#define mmDCP0_INPUT_CSC_CONTROL …
#define mmDCP1_INPUT_CSC_CONTROL …
#define mmDCP2_INPUT_CSC_CONTROL …
#define mmDCP3_INPUT_CSC_CONTROL …
#define mmDCP4_INPUT_CSC_CONTROL …
#define mmDCP5_INPUT_CSC_CONTROL …
#define mmINPUT_CSC_C11_C12 …
#define mmDCP0_INPUT_CSC_C11_C12 …
#define mmDCP1_INPUT_CSC_C11_C12 …
#define mmDCP2_INPUT_CSC_C11_C12 …
#define mmDCP3_INPUT_CSC_C11_C12 …
#define mmDCP4_INPUT_CSC_C11_C12 …
#define mmDCP5_INPUT_CSC_C11_C12 …
#define mmINPUT_CSC_C13_C14 …
#define mmDCP0_INPUT_CSC_C13_C14 …
#define mmDCP1_INPUT_CSC_C13_C14 …
#define mmDCP2_INPUT_CSC_C13_C14 …
#define mmDCP3_INPUT_CSC_C13_C14 …
#define mmDCP4_INPUT_CSC_C13_C14 …
#define mmDCP5_INPUT_CSC_C13_C14 …
#define mmINPUT_CSC_C21_C22 …
#define mmDCP0_INPUT_CSC_C21_C22 …
#define mmDCP1_INPUT_CSC_C21_C22 …
#define mmDCP2_INPUT_CSC_C21_C22 …
#define mmDCP3_INPUT_CSC_C21_C22 …
#define mmDCP4_INPUT_CSC_C21_C22 …
#define mmDCP5_INPUT_CSC_C21_C22 …
#define mmINPUT_CSC_C23_C24 …
#define mmDCP0_INPUT_CSC_C23_C24 …
#define mmDCP1_INPUT_CSC_C23_C24 …
#define mmDCP2_INPUT_CSC_C23_C24 …
#define mmDCP3_INPUT_CSC_C23_C24 …
#define mmDCP4_INPUT_CSC_C23_C24 …
#define mmDCP5_INPUT_CSC_C23_C24 …
#define mmINPUT_CSC_C31_C32 …
#define mmDCP0_INPUT_CSC_C31_C32 …
#define mmDCP1_INPUT_CSC_C31_C32 …
#define mmDCP2_INPUT_CSC_C31_C32 …
#define mmDCP3_INPUT_CSC_C31_C32 …
#define mmDCP4_INPUT_CSC_C31_C32 …
#define mmDCP5_INPUT_CSC_C31_C32 …
#define mmINPUT_CSC_C33_C34 …
#define mmDCP0_INPUT_CSC_C33_C34 …
#define mmDCP1_INPUT_CSC_C33_C34 …
#define mmDCP2_INPUT_CSC_C33_C34 …
#define mmDCP3_INPUT_CSC_C33_C34 …
#define mmDCP4_INPUT_CSC_C33_C34 …
#define mmDCP5_INPUT_CSC_C33_C34 …
#define mmOUTPUT_CSC_CONTROL …
#define mmDCP0_OUTPUT_CSC_CONTROL …
#define mmDCP1_OUTPUT_CSC_CONTROL …
#define mmDCP2_OUTPUT_CSC_CONTROL …
#define mmDCP3_OUTPUT_CSC_CONTROL …
#define mmDCP4_OUTPUT_CSC_CONTROL …
#define mmDCP5_OUTPUT_CSC_CONTROL …
#define mmOUTPUT_CSC_C11_C12 …
#define mmDCP0_OUTPUT_CSC_C11_C12 …
#define mmDCP1_OUTPUT_CSC_C11_C12 …
#define mmDCP2_OUTPUT_CSC_C11_C12 …
#define mmDCP3_OUTPUT_CSC_C11_C12 …
#define mmDCP4_OUTPUT_CSC_C11_C12 …
#define mmDCP5_OUTPUT_CSC_C11_C12 …
#define mmOUTPUT_CSC_C13_C14 …
#define mmDCP0_OUTPUT_CSC_C13_C14 …
#define mmDCP1_OUTPUT_CSC_C13_C14 …
#define mmDCP2_OUTPUT_CSC_C13_C14 …
#define mmDCP3_OUTPUT_CSC_C13_C14 …
#define mmDCP4_OUTPUT_CSC_C13_C14 …
#define mmDCP5_OUTPUT_CSC_C13_C14 …
#define mmOUTPUT_CSC_C21_C22 …
#define mmDCP0_OUTPUT_CSC_C21_C22 …
#define mmDCP1_OUTPUT_CSC_C21_C22 …
#define mmDCP2_OUTPUT_CSC_C21_C22 …
#define mmDCP3_OUTPUT_CSC_C21_C22 …
#define mmDCP4_OUTPUT_CSC_C21_C22 …
#define mmDCP5_OUTPUT_CSC_C21_C22 …
#define mmOUTPUT_CSC_C23_C24 …
#define mmDCP0_OUTPUT_CSC_C23_C24 …
#define mmDCP1_OUTPUT_CSC_C23_C24 …
#define mmDCP2_OUTPUT_CSC_C23_C24 …
#define mmDCP3_OUTPUT_CSC_C23_C24 …
#define mmDCP4_OUTPUT_CSC_C23_C24 …
#define mmDCP5_OUTPUT_CSC_C23_C24 …
#define mmOUTPUT_CSC_C31_C32 …
#define mmDCP0_OUTPUT_CSC_C31_C32 …
#define mmDCP1_OUTPUT_CSC_C31_C32 …
#define mmDCP2_OUTPUT_CSC_C31_C32 …
#define mmDCP3_OUTPUT_CSC_C31_C32 …
#define mmDCP4_OUTPUT_CSC_C31_C32 …
#define mmDCP5_OUTPUT_CSC_C31_C32 …
#define mmOUTPUT_CSC_C33_C34 …
#define mmDCP0_OUTPUT_CSC_C33_C34 …
#define mmDCP1_OUTPUT_CSC_C33_C34 …
#define mmDCP2_OUTPUT_CSC_C33_C34 …
#define mmDCP3_OUTPUT_CSC_C33_C34 …
#define mmDCP4_OUTPUT_CSC_C33_C34 …
#define mmDCP5_OUTPUT_CSC_C33_C34 …
#define mmCOMM_MATRIXA_TRANS_C11_C12 …
#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 …
#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 …
#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 …
#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 …
#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 …
#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 …
#define mmCOMM_MATRIXA_TRANS_C13_C14 …
#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 …
#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 …
#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 …
#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 …
#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 …
#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 …
#define mmCOMM_MATRIXA_TRANS_C21_C22 …
#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 …
#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 …
#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 …
#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 …
#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 …
#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 …
#define mmCOMM_MATRIXA_TRANS_C23_C24 …
#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 …
#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 …
#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 …
#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 …
#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 …
#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 …
#define mmCOMM_MATRIXA_TRANS_C31_C32 …
#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 …
#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 …
#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 …
#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 …
#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 …
#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 …
#define mmCOMM_MATRIXA_TRANS_C33_C34 …
#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 …
#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 …
#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 …
#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 …
#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 …
#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 …
#define mmCOMM_MATRIXB_TRANS_C11_C12 …
#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 …
#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 …
#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 …
#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 …
#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 …
#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 …
#define mmCOMM_MATRIXB_TRANS_C13_C14 …
#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 …
#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 …
#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 …
#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 …
#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 …
#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 …
#define mmCOMM_MATRIXB_TRANS_C21_C22 …
#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 …
#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 …
#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 …
#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 …
#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 …
#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 …
#define mmCOMM_MATRIXB_TRANS_C23_C24 …
#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 …
#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 …
#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 …
#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 …
#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 …
#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 …
#define mmCOMM_MATRIXB_TRANS_C31_C32 …
#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 …
#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 …
#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 …
#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 …
#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 …
#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 …
#define mmCOMM_MATRIXB_TRANS_C33_C34 …
#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 …
#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 …
#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 …
#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 …
#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 …
#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 …
#define mmDENORM_CONTROL …
#define mmDCP0_DENORM_CONTROL …
#define mmDCP1_DENORM_CONTROL …
#define mmDCP2_DENORM_CONTROL …
#define mmDCP3_DENORM_CONTROL …
#define mmDCP4_DENORM_CONTROL …
#define mmDCP5_DENORM_CONTROL …
#define mmOUT_ROUND_CONTROL …
#define mmDCP0_OUT_ROUND_CONTROL …
#define mmDCP1_OUT_ROUND_CONTROL …
#define mmDCP2_OUT_ROUND_CONTROL …
#define mmDCP3_OUT_ROUND_CONTROL …
#define mmDCP4_OUT_ROUND_CONTROL …
#define mmDCP5_OUT_ROUND_CONTROL …
#define mmOUT_CLAMP_CONTROL_R_CR …
#define mmDCP0_OUT_CLAMP_CONTROL_R_CR …
#define mmDCP1_OUT_CLAMP_CONTROL_R_CR …
#define mmDCP2_OUT_CLAMP_CONTROL_R_CR …
#define mmDCP3_OUT_CLAMP_CONTROL_R_CR …
#define mmDCP4_OUT_CLAMP_CONTROL_R_CR …
#define mmDCP5_OUT_CLAMP_CONTROL_R_CR …
#define mmOUT_CLAMP_CONTROL_G_Y …
#define mmDCP0_OUT_CLAMP_CONTROL_G_Y …
#define mmDCP1_OUT_CLAMP_CONTROL_G_Y …
#define mmDCP2_OUT_CLAMP_CONTROL_G_Y …
#define mmDCP3_OUT_CLAMP_CONTROL_G_Y …
#define mmDCP4_OUT_CLAMP_CONTROL_G_Y …
#define mmDCP5_OUT_CLAMP_CONTROL_G_Y …
#define mmOUT_CLAMP_CONTROL_B_CB …
#define mmDCP0_OUT_CLAMP_CONTROL_B_CB …
#define mmDCP1_OUT_CLAMP_CONTROL_B_CB …
#define mmDCP2_OUT_CLAMP_CONTROL_B_CB …
#define mmDCP3_OUT_CLAMP_CONTROL_B_CB …
#define mmDCP4_OUT_CLAMP_CONTROL_B_CB …
#define mmDCP5_OUT_CLAMP_CONTROL_B_CB …
#define mmKEY_CONTROL …
#define mmDCP0_KEY_CONTROL …
#define mmDCP1_KEY_CONTROL …
#define mmDCP2_KEY_CONTROL …
#define mmDCP3_KEY_CONTROL …
#define mmDCP4_KEY_CONTROL …
#define mmDCP5_KEY_CONTROL …
#define mmKEY_RANGE_ALPHA …
#define mmDCP0_KEY_RANGE_ALPHA …
#define mmDCP1_KEY_RANGE_ALPHA …
#define mmDCP2_KEY_RANGE_ALPHA …
#define mmDCP3_KEY_RANGE_ALPHA …
#define mmDCP4_KEY_RANGE_ALPHA …
#define mmDCP5_KEY_RANGE_ALPHA …
#define mmKEY_RANGE_RED …
#define mmDCP0_KEY_RANGE_RED …
#define mmDCP1_KEY_RANGE_RED …
#define mmDCP2_KEY_RANGE_RED …
#define mmDCP3_KEY_RANGE_RED …
#define mmDCP4_KEY_RANGE_RED …
#define mmDCP5_KEY_RANGE_RED …
#define mmKEY_RANGE_GREEN …
#define mmDCP0_KEY_RANGE_GREEN …
#define mmDCP1_KEY_RANGE_GREEN …
#define mmDCP2_KEY_RANGE_GREEN …
#define mmDCP3_KEY_RANGE_GREEN …
#define mmDCP4_KEY_RANGE_GREEN …
#define mmDCP5_KEY_RANGE_GREEN …
#define mmKEY_RANGE_BLUE …
#define mmDCP0_KEY_RANGE_BLUE …
#define mmDCP1_KEY_RANGE_BLUE …
#define mmDCP2_KEY_RANGE_BLUE …
#define mmDCP3_KEY_RANGE_BLUE …
#define mmDCP4_KEY_RANGE_BLUE …
#define mmDCP5_KEY_RANGE_BLUE …
#define mmDEGAMMA_CONTROL …
#define mmDCP0_DEGAMMA_CONTROL …
#define mmDCP1_DEGAMMA_CONTROL …
#define mmDCP2_DEGAMMA_CONTROL …
#define mmDCP3_DEGAMMA_CONTROL …
#define mmDCP4_DEGAMMA_CONTROL …
#define mmDCP5_DEGAMMA_CONTROL …
#define mmGAMUT_REMAP_CONTROL …
#define mmDCP0_GAMUT_REMAP_CONTROL …
#define mmDCP1_GAMUT_REMAP_CONTROL …
#define mmDCP2_GAMUT_REMAP_CONTROL …
#define mmDCP3_GAMUT_REMAP_CONTROL …
#define mmDCP4_GAMUT_REMAP_CONTROL …
#define mmDCP5_GAMUT_REMAP_CONTROL …
#define mmGAMUT_REMAP_C11_C12 …
#define mmDCP0_GAMUT_REMAP_C11_C12 …
#define mmDCP1_GAMUT_REMAP_C11_C12 …
#define mmDCP2_GAMUT_REMAP_C11_C12 …
#define mmDCP3_GAMUT_REMAP_C11_C12 …
#define mmDCP4_GAMUT_REMAP_C11_C12 …
#define mmDCP5_GAMUT_REMAP_C11_C12 …
#define mmGAMUT_REMAP_C13_C14 …
#define mmDCP0_GAMUT_REMAP_C13_C14 …
#define mmDCP1_GAMUT_REMAP_C13_C14 …
#define mmDCP2_GAMUT_REMAP_C13_C14 …
#define mmDCP3_GAMUT_REMAP_C13_C14 …
#define mmDCP4_GAMUT_REMAP_C13_C14 …
#define mmDCP5_GAMUT_REMAP_C13_C14 …
#define mmGAMUT_REMAP_C21_C22 …
#define mmDCP0_GAMUT_REMAP_C21_C22 …
#define mmDCP1_GAMUT_REMAP_C21_C22 …
#define mmDCP2_GAMUT_REMAP_C21_C22 …
#define mmDCP3_GAMUT_REMAP_C21_C22 …
#define mmDCP4_GAMUT_REMAP_C21_C22 …
#define mmDCP5_GAMUT_REMAP_C21_C22 …
#define mmGAMUT_REMAP_C23_C24 …
#define mmDCP0_GAMUT_REMAP_C23_C24 …
#define mmDCP1_GAMUT_REMAP_C23_C24 …
#define mmDCP2_GAMUT_REMAP_C23_C24 …
#define mmDCP3_GAMUT_REMAP_C23_C24 …
#define mmDCP4_GAMUT_REMAP_C23_C24 …
#define mmDCP5_GAMUT_REMAP_C23_C24 …
#define mmGAMUT_REMAP_C31_C32 …
#define mmDCP0_GAMUT_REMAP_C31_C32 …
#define mmDCP1_GAMUT_REMAP_C31_C32 …
#define mmDCP2_GAMUT_REMAP_C31_C32 …
#define mmDCP3_GAMUT_REMAP_C31_C32 …
#define mmDCP4_GAMUT_REMAP_C31_C32 …
#define mmDCP5_GAMUT_REMAP_C31_C32 …
#define mmGAMUT_REMAP_C33_C34 …
#define mmDCP0_GAMUT_REMAP_C33_C34 …
#define mmDCP1_GAMUT_REMAP_C33_C34 …
#define mmDCP2_GAMUT_REMAP_C33_C34 …
#define mmDCP3_GAMUT_REMAP_C33_C34 …
#define mmDCP4_GAMUT_REMAP_C33_C34 …
#define mmDCP5_GAMUT_REMAP_C33_C34 …
#define mmDCP_SPATIAL_DITHER_CNTL …
#define mmDCP0_DCP_SPATIAL_DITHER_CNTL …
#define mmDCP1_DCP_SPATIAL_DITHER_CNTL …
#define mmDCP2_DCP_SPATIAL_DITHER_CNTL …
#define mmDCP3_DCP_SPATIAL_DITHER_CNTL …
#define mmDCP4_DCP_SPATIAL_DITHER_CNTL …
#define mmDCP5_DCP_SPATIAL_DITHER_CNTL …
#define mmDCP_RANDOM_SEEDS …
#define mmDCP0_DCP_RANDOM_SEEDS …
#define mmDCP1_DCP_RANDOM_SEEDS …
#define mmDCP2_DCP_RANDOM_SEEDS …
#define mmDCP3_DCP_RANDOM_SEEDS …
#define mmDCP4_DCP_RANDOM_SEEDS …
#define mmDCP5_DCP_RANDOM_SEEDS …
#define mmDCP_FP_CONVERTED_FIELD …
#define mmDCP0_DCP_FP_CONVERTED_FIELD …
#define mmDCP1_DCP_FP_CONVERTED_FIELD …
#define mmDCP2_DCP_FP_CONVERTED_FIELD …
#define mmDCP3_DCP_FP_CONVERTED_FIELD …
#define mmDCP4_DCP_FP_CONVERTED_FIELD …
#define mmDCP5_DCP_FP_CONVERTED_FIELD …
#define mmCUR_CONTROL …
#define mmDCP0_CUR_CONTROL …
#define mmDCP1_CUR_CONTROL …
#define mmDCP2_CUR_CONTROL …
#define mmDCP3_CUR_CONTROL …
#define mmDCP4_CUR_CONTROL …
#define mmDCP5_CUR_CONTROL …
#define mmCUR_SURFACE_ADDRESS …
#define mmDCP0_CUR_SURFACE_ADDRESS …
#define mmDCP1_CUR_SURFACE_ADDRESS …
#define mmDCP2_CUR_SURFACE_ADDRESS …
#define mmDCP3_CUR_SURFACE_ADDRESS …
#define mmDCP4_CUR_SURFACE_ADDRESS …
#define mmDCP5_CUR_SURFACE_ADDRESS …
#define mmCUR_SIZE …
#define mmDCP0_CUR_SIZE …
#define mmDCP1_CUR_SIZE …
#define mmDCP2_CUR_SIZE …
#define mmDCP3_CUR_SIZE …
#define mmDCP4_CUR_SIZE …
#define mmDCP5_CUR_SIZE …
#define mmCUR_SURFACE_ADDRESS_HIGH …
#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH …
#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH …
#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH …
#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH …
#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH …
#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH …
#define mmCUR_POSITION …
#define mmDCP0_CUR_POSITION …
#define mmDCP1_CUR_POSITION …
#define mmDCP2_CUR_POSITION …
#define mmDCP3_CUR_POSITION …
#define mmDCP4_CUR_POSITION …
#define mmDCP5_CUR_POSITION …
#define mmCUR_HOT_SPOT …
#define mmDCP0_CUR_HOT_SPOT …
#define mmDCP1_CUR_HOT_SPOT …
#define mmDCP2_CUR_HOT_SPOT …
#define mmDCP3_CUR_HOT_SPOT …
#define mmDCP4_CUR_HOT_SPOT …
#define mmDCP5_CUR_HOT_SPOT …
#define mmCUR_COLOR1 …
#define mmDCP0_CUR_COLOR1 …
#define mmDCP1_CUR_COLOR1 …
#define mmDCP2_CUR_COLOR1 …
#define mmDCP3_CUR_COLOR1 …
#define mmDCP4_CUR_COLOR1 …
#define mmDCP5_CUR_COLOR1 …
#define mmCUR_COLOR2 …
#define mmDCP0_CUR_COLOR2 …
#define mmDCP1_CUR_COLOR2 …
#define mmDCP2_CUR_COLOR2 …
#define mmDCP3_CUR_COLOR2 …
#define mmDCP4_CUR_COLOR2 …
#define mmDCP5_CUR_COLOR2 …
#define mmCUR_UPDATE …
#define mmDCP0_CUR_UPDATE …
#define mmDCP1_CUR_UPDATE …
#define mmDCP2_CUR_UPDATE …
#define mmDCP3_CUR_UPDATE …
#define mmDCP4_CUR_UPDATE …
#define mmDCP5_CUR_UPDATE …
#define mmCUR2_CONTROL …
#define mmDCP0_CUR2_CONTROL …
#define mmDCP1_CUR2_CONTROL …
#define mmDCP2_CUR2_CONTROL …
#define mmDCP3_CUR2_CONTROL …
#define mmDCP4_CUR2_CONTROL …
#define mmDCP5_CUR2_CONTROL …
#define mmCUR2_SURFACE_ADDRESS …
#define mmDCP0_CUR2_SURFACE_ADDRESS …
#define mmDCP1_CUR2_SURFACE_ADDRESS …
#define mmDCP2_CUR2_SURFACE_ADDRESS …
#define mmDCP3_CUR2_SURFACE_ADDRESS …
#define mmDCP4_CUR2_SURFACE_ADDRESS …
#define mmDCP5_CUR2_SURFACE_ADDRESS …
#define mmCUR2_SIZE …
#define mmDCP0_CUR2_SIZE …
#define mmDCP1_CUR2_SIZE …
#define mmDCP2_CUR2_SIZE …
#define mmDCP3_CUR2_SIZE …
#define mmDCP4_CUR2_SIZE …
#define mmDCP5_CUR2_SIZE …
#define mmCUR2_SURFACE_ADDRESS_HIGH …
#define mmDCP0_CUR2_SURFACE_ADDRESS_HIGH …
#define mmDCP1_CUR2_SURFACE_ADDRESS_HIGH …
#define mmDCP2_CUR2_SURFACE_ADDRESS_HIGH …
#define mmDCP3_CUR2_SURFACE_ADDRESS_HIGH …
#define mmDCP4_CUR2_SURFACE_ADDRESS_HIGH …
#define mmDCP5_CUR2_SURFACE_ADDRESS_HIGH …
#define mmCUR2_POSITION …
#define mmDCP0_CUR2_POSITION …
#define mmDCP1_CUR2_POSITION …
#define mmDCP2_CUR2_POSITION …
#define mmDCP3_CUR2_POSITION …
#define mmDCP4_CUR2_POSITION …
#define mmDCP5_CUR2_POSITION …
#define mmCUR2_HOT_SPOT …
#define mmDCP0_CUR2_HOT_SPOT …
#define mmDCP1_CUR2_HOT_SPOT …
#define mmDCP2_CUR2_HOT_SPOT …
#define mmDCP3_CUR2_HOT_SPOT …
#define mmDCP4_CUR2_HOT_SPOT …
#define mmDCP5_CUR2_HOT_SPOT …
#define mmCUR2_COLOR1 …
#define mmDCP0_CUR2_COLOR1 …
#define mmDCP1_CUR2_COLOR1 …
#define mmDCP2_CUR2_COLOR1 …
#define mmDCP3_CUR2_COLOR1 …
#define mmDCP4_CUR2_COLOR1 …
#define mmDCP5_CUR2_COLOR1 …
#define mmCUR2_COLOR2 …
#define mmDCP0_CUR2_COLOR2 …
#define mmDCP1_CUR2_COLOR2 …
#define mmDCP2_CUR2_COLOR2 …
#define mmDCP3_CUR2_COLOR2 …
#define mmDCP4_CUR2_COLOR2 …
#define mmDCP5_CUR2_COLOR2 …
#define mmCUR2_UPDATE …
#define mmDCP0_CUR2_UPDATE …
#define mmDCP1_CUR2_UPDATE …
#define mmDCP2_CUR2_UPDATE …
#define mmDCP3_CUR2_UPDATE …
#define mmDCP4_CUR2_UPDATE …
#define mmDCP5_CUR2_UPDATE …
#define mmCUR_REQUEST_FILTER_CNTL …
#define mmDCP0_CUR_REQUEST_FILTER_CNTL …
#define mmDCP1_CUR_REQUEST_FILTER_CNTL …
#define mmDCP2_CUR_REQUEST_FILTER_CNTL …
#define mmDCP3_CUR_REQUEST_FILTER_CNTL …
#define mmDCP4_CUR_REQUEST_FILTER_CNTL …
#define mmDCP5_CUR_REQUEST_FILTER_CNTL …
#define mmCUR_STEREO_CONTROL …
#define mmDCP0_CUR_STEREO_CONTROL …
#define mmDCP1_CUR_STEREO_CONTROL …
#define mmDCP2_CUR_STEREO_CONTROL …
#define mmDCP3_CUR_STEREO_CONTROL …
#define mmDCP4_CUR_STEREO_CONTROL …
#define mmDCP5_CUR_STEREO_CONTROL …
#define mmCUR2_STEREO_CONTROL …
#define mmDCP0_CUR2_STEREO_CONTROL …
#define mmDCP1_CUR2_STEREO_CONTROL …
#define mmDCP2_CUR2_STEREO_CONTROL …
#define mmDCP3_CUR2_STEREO_CONTROL …
#define mmDCP4_CUR2_STEREO_CONTROL …
#define mmDCP5_CUR2_STEREO_CONTROL …
#define mmDC_LUT_RW_MODE …
#define mmDCP0_DC_LUT_RW_MODE …
#define mmDCP1_DC_LUT_RW_MODE …
#define mmDCP2_DC_LUT_RW_MODE …
#define mmDCP3_DC_LUT_RW_MODE …
#define mmDCP4_DC_LUT_RW_MODE …
#define mmDCP5_DC_LUT_RW_MODE …
#define mmDC_LUT_RW_INDEX …
#define mmDCP0_DC_LUT_RW_INDEX …
#define mmDCP1_DC_LUT_RW_INDEX …
#define mmDCP2_DC_LUT_RW_INDEX …
#define mmDCP3_DC_LUT_RW_INDEX …
#define mmDCP4_DC_LUT_RW_INDEX …
#define mmDCP5_DC_LUT_RW_INDEX …
#define mmDC_LUT_SEQ_COLOR …
#define mmDCP0_DC_LUT_SEQ_COLOR …
#define mmDCP1_DC_LUT_SEQ_COLOR …
#define mmDCP2_DC_LUT_SEQ_COLOR …
#define mmDCP3_DC_LUT_SEQ_COLOR …
#define mmDCP4_DC_LUT_SEQ_COLOR …
#define mmDCP5_DC_LUT_SEQ_COLOR …
#define mmDC_LUT_PWL_DATA …
#define mmDCP0_DC_LUT_PWL_DATA …
#define mmDCP1_DC_LUT_PWL_DATA …
#define mmDCP2_DC_LUT_PWL_DATA …
#define mmDCP3_DC_LUT_PWL_DATA …
#define mmDCP4_DC_LUT_PWL_DATA …
#define mmDCP5_DC_LUT_PWL_DATA …
#define mmDC_LUT_30_COLOR …
#define mmDCP0_DC_LUT_30_COLOR …
#define mmDCP1_DC_LUT_30_COLOR …
#define mmDCP2_DC_LUT_30_COLOR …
#define mmDCP3_DC_LUT_30_COLOR …
#define mmDCP4_DC_LUT_30_COLOR …
#define mmDCP5_DC_LUT_30_COLOR …
#define mmDC_LUT_VGA_ACCESS_ENABLE …
#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE …
#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE …
#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE …
#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE …
#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE …
#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE …
#define mmDC_LUT_WRITE_EN_MASK …
#define mmDCP0_DC_LUT_WRITE_EN_MASK …
#define mmDCP1_DC_LUT_WRITE_EN_MASK …
#define mmDCP2_DC_LUT_WRITE_EN_MASK …
#define mmDCP3_DC_LUT_WRITE_EN_MASK …
#define mmDCP4_DC_LUT_WRITE_EN_MASK …
#define mmDCP5_DC_LUT_WRITE_EN_MASK …
#define mmDC_LUT_AUTOFILL …
#define mmDCP0_DC_LUT_AUTOFILL …
#define mmDCP1_DC_LUT_AUTOFILL …
#define mmDCP2_DC_LUT_AUTOFILL …
#define mmDCP3_DC_LUT_AUTOFILL …
#define mmDCP4_DC_LUT_AUTOFILL …
#define mmDCP5_DC_LUT_AUTOFILL …
#define mmDC_LUT_CONTROL …
#define mmDCP0_DC_LUT_CONTROL …
#define mmDCP1_DC_LUT_CONTROL …
#define mmDCP2_DC_LUT_CONTROL …
#define mmDCP3_DC_LUT_CONTROL …
#define mmDCP4_DC_LUT_CONTROL …
#define mmDCP5_DC_LUT_CONTROL …
#define mmDC_LUT_BLACK_OFFSET_BLUE …
#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE …
#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE …
#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE …
#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE …
#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE …
#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE …
#define mmDC_LUT_BLACK_OFFSET_GREEN …
#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN …
#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN …
#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN …
#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN …
#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN …
#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN …
#define mmDC_LUT_BLACK_OFFSET_RED …
#define mmDCP0_DC_LUT_BLACK_OFFSET_RED …
#define mmDCP1_DC_LUT_BLACK_OFFSET_RED …
#define mmDCP2_DC_LUT_BLACK_OFFSET_RED …
#define mmDCP3_DC_LUT_BLACK_OFFSET_RED …
#define mmDCP4_DC_LUT_BLACK_OFFSET_RED …
#define mmDCP5_DC_LUT_BLACK_OFFSET_RED …
#define mmDC_LUT_WHITE_OFFSET_BLUE …
#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE …
#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE …
#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE …
#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE …
#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE …
#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE …
#define mmDC_LUT_WHITE_OFFSET_GREEN …
#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN …
#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN …
#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN …
#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN …
#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN …
#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN …
#define mmDC_LUT_WHITE_OFFSET_RED …
#define mmDCP0_DC_LUT_WHITE_OFFSET_RED …
#define mmDCP1_DC_LUT_WHITE_OFFSET_RED …
#define mmDCP2_DC_LUT_WHITE_OFFSET_RED …
#define mmDCP3_DC_LUT_WHITE_OFFSET_RED …
#define mmDCP4_DC_LUT_WHITE_OFFSET_RED …
#define mmDCP5_DC_LUT_WHITE_OFFSET_RED …
#define mmDCP_CRC_CONTROL …
#define mmDCP0_DCP_CRC_CONTROL …
#define mmDCP1_DCP_CRC_CONTROL …
#define mmDCP2_DCP_CRC_CONTROL …
#define mmDCP3_DCP_CRC_CONTROL …
#define mmDCP4_DCP_CRC_CONTROL …
#define mmDCP5_DCP_CRC_CONTROL …
#define mmDCP_CRC_MASK …
#define mmDCP0_DCP_CRC_MASK …
#define mmDCP1_DCP_CRC_MASK …
#define mmDCP2_DCP_CRC_MASK …
#define mmDCP3_DCP_CRC_MASK …
#define mmDCP4_DCP_CRC_MASK …
#define mmDCP5_DCP_CRC_MASK …
#define mmDCP_CRC_CURRENT …
#define mmDCP0_DCP_CRC_CURRENT …
#define mmDCP1_DCP_CRC_CURRENT …
#define mmDCP2_DCP_CRC_CURRENT …
#define mmDCP3_DCP_CRC_CURRENT …
#define mmDCP4_DCP_CRC_CURRENT …
#define mmDCP5_DCP_CRC_CURRENT …
#define mmDCP_CRC_LAST …
#define mmDCP0_DCP_CRC_LAST …
#define mmDCP1_DCP_CRC_LAST …
#define mmDCP2_DCP_CRC_LAST …
#define mmDCP3_DCP_CRC_LAST …
#define mmDCP4_DCP_CRC_LAST …
#define mmDCP5_DCP_CRC_LAST …
#define mmDCP_DEBUG …
#define mmDCP0_DCP_DEBUG …
#define mmDCP1_DCP_DEBUG …
#define mmDCP2_DCP_DEBUG …
#define mmDCP3_DCP_DEBUG …
#define mmDCP4_DCP_DEBUG …
#define mmDCP5_DCP_DEBUG …
#define mmGRPH_FLIP_RATE_CNTL …
#define mmDCP0_GRPH_FLIP_RATE_CNTL …
#define mmDCP1_GRPH_FLIP_RATE_CNTL …
#define mmDCP2_GRPH_FLIP_RATE_CNTL …
#define mmDCP3_GRPH_FLIP_RATE_CNTL …
#define mmDCP4_GRPH_FLIP_RATE_CNTL …
#define mmDCP5_GRPH_FLIP_RATE_CNTL …
#define mmDCP_GSL_CONTROL …
#define mmDCP0_DCP_GSL_CONTROL …
#define mmDCP1_DCP_GSL_CONTROL …
#define mmDCP2_DCP_GSL_CONTROL …
#define mmDCP3_DCP_GSL_CONTROL …
#define mmDCP4_DCP_GSL_CONTROL …
#define mmDCP5_DCP_GSL_CONTROL …
#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK …
#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK …
#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK …
#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK …
#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK …
#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK …
#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK …
#define mmOVL_SECONDARY_SURFACE_ADDRESS …
#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS …
#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS …
#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS …
#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS …
#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS …
#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS …
#define mmOVL_STEREOSYNC_FLIP …
#define mmDCP0_OVL_STEREOSYNC_FLIP …
#define mmDCP1_OVL_STEREOSYNC_FLIP …
#define mmDCP2_OVL_STEREOSYNC_FLIP …
#define mmDCP3_OVL_STEREOSYNC_FLIP …
#define mmDCP4_OVL_STEREOSYNC_FLIP …
#define mmDCP5_OVL_STEREOSYNC_FLIP …
#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH …
#define mmDCP_TEST_DEBUG_INDEX …
#define mmDCP0_DCP_TEST_DEBUG_INDEX …
#define mmDCP1_DCP_TEST_DEBUG_INDEX …
#define mmDCP2_DCP_TEST_DEBUG_INDEX …
#define mmDCP3_DCP_TEST_DEBUG_INDEX …
#define mmDCP4_DCP_TEST_DEBUG_INDEX …
#define mmDCP5_DCP_TEST_DEBUG_INDEX …
#define mmDCP_TEST_DEBUG_DATA …
#define mmDCP0_DCP_TEST_DEBUG_DATA …
#define mmDCP1_DCP_TEST_DEBUG_DATA …
#define mmDCP2_DCP_TEST_DEBUG_DATA …
#define mmDCP3_DCP_TEST_DEBUG_DATA …
#define mmDCP4_DCP_TEST_DEBUG_DATA …
#define mmDCP5_DCP_TEST_DEBUG_DATA …
#define mmGRPH_STEREOSYNC_FLIP …
#define mmDCP0_GRPH_STEREOSYNC_FLIP …
#define mmDCP1_GRPH_STEREOSYNC_FLIP …
#define mmDCP2_GRPH_STEREOSYNC_FLIP …
#define mmDCP3_GRPH_STEREOSYNC_FLIP …
#define mmDCP4_GRPH_STEREOSYNC_FLIP …
#define mmDCP5_GRPH_STEREOSYNC_FLIP …
#define mmDCP_DEBUG2 …
#define mmDCP0_DCP_DEBUG2 …
#define mmDCP1_DCP_DEBUG2 …
#define mmDCP2_DCP_DEBUG2 …
#define mmDCP3_DCP_DEBUG2 …
#define mmDCP4_DCP_DEBUG2 …
#define mmDCP5_DCP_DEBUG2 …
#define mmHW_ROTATION …
#define mmDCP0_HW_ROTATION …
#define mmDCP1_HW_ROTATION …
#define mmDCP2_HW_ROTATION …
#define mmDCP3_HW_ROTATION …
#define mmDCP4_HW_ROTATION …
#define mmDCP5_HW_ROTATION …
#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL …
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL …
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL …
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL …
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL …
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL …
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL …
#define mmREGAMMA_CONTROL …
#define mmDCP0_REGAMMA_CONTROL …
#define mmDCP1_REGAMMA_CONTROL …
#define mmDCP2_REGAMMA_CONTROL …
#define mmDCP3_REGAMMA_CONTROL …
#define mmDCP4_REGAMMA_CONTROL …
#define mmDCP5_REGAMMA_CONTROL …
#define mmREGAMMA_LUT_INDEX …
#define mmDCP0_REGAMMA_LUT_INDEX …
#define mmDCP1_REGAMMA_LUT_INDEX …
#define mmDCP2_REGAMMA_LUT_INDEX …
#define mmDCP3_REGAMMA_LUT_INDEX …
#define mmDCP4_REGAMMA_LUT_INDEX …
#define mmDCP5_REGAMMA_LUT_INDEX …
#define mmREGAMMA_LUT_DATA …
#define mmDCP0_REGAMMA_LUT_DATA …
#define mmDCP1_REGAMMA_LUT_DATA …
#define mmDCP2_REGAMMA_LUT_DATA …
#define mmDCP3_REGAMMA_LUT_DATA …
#define mmDCP4_REGAMMA_LUT_DATA …
#define mmDCP5_REGAMMA_LUT_DATA …
#define mmREGAMMA_LUT_WRITE_EN_MASK …
#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK …
#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK …
#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK …
#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK …
#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK …
#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK …
#define mmREGAMMA_CNTLA_START_CNTL …
#define mmDCP0_REGAMMA_CNTLA_START_CNTL …
#define mmDCP1_REGAMMA_CNTLA_START_CNTL …
#define mmDCP2_REGAMMA_CNTLA_START_CNTL …
#define mmDCP3_REGAMMA_CNTLA_START_CNTL …
#define mmDCP4_REGAMMA_CNTLA_START_CNTL …
#define mmDCP5_REGAMMA_CNTLA_START_CNTL …
#define mmREGAMMA_CNTLA_SLOPE_CNTL …
#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL …
#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL …
#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL …
#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL …
#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL …
#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL …
#define mmREGAMMA_CNTLA_END_CNTL1 …
#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 …
#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 …
#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 …
#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 …
#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 …
#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 …
#define mmREGAMMA_CNTLA_END_CNTL2 …
#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 …
#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 …
#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 …
#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 …
#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 …
#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 …
#define mmREGAMMA_CNTLA_REGION_0_1 …
#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 …
#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 …
#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 …
#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 …
#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 …
#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 …
#define mmREGAMMA_CNTLA_REGION_2_3 …
#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 …
#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 …
#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 …
#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 …
#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 …
#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 …
#define mmREGAMMA_CNTLA_REGION_4_5 …
#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 …
#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 …
#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 …
#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 …
#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 …
#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 …
#define mmREGAMMA_CNTLA_REGION_6_7 …
#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 …
#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 …
#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 …
#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 …
#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 …
#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 …
#define mmREGAMMA_CNTLA_REGION_8_9 …
#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 …
#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 …
#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 …
#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 …
#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 …
#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 …
#define mmREGAMMA_CNTLA_REGION_10_11 …
#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 …
#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 …
#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 …
#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 …
#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 …
#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 …
#define mmREGAMMA_CNTLA_REGION_12_13 …
#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 …
#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 …
#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 …
#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 …
#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 …
#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 …
#define mmREGAMMA_CNTLA_REGION_14_15 …
#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 …
#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 …
#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 …
#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 …
#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 …
#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 …
#define mmREGAMMA_CNTLB_START_CNTL …
#define mmDCP0_REGAMMA_CNTLB_START_CNTL …
#define mmDCP1_REGAMMA_CNTLB_START_CNTL …
#define mmDCP2_REGAMMA_CNTLB_START_CNTL …
#define mmDCP3_REGAMMA_CNTLB_START_CNTL …
#define mmDCP4_REGAMMA_CNTLB_START_CNTL …
#define mmDCP5_REGAMMA_CNTLB_START_CNTL …
#define mmREGAMMA_CNTLB_SLOPE_CNTL …
#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL …
#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL …
#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL …
#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL …
#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL …
#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL …
#define mmREGAMMA_CNTLB_END_CNTL1 …
#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 …
#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 …
#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 …
#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 …
#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 …
#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 …
#define mmREGAMMA_CNTLB_END_CNTL2 …
#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 …
#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 …
#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 …
#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 …
#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 …
#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 …
#define mmREGAMMA_CNTLB_REGION_0_1 …
#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 …
#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 …
#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 …
#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 …
#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 …
#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 …
#define mmREGAMMA_CNTLB_REGION_2_3 …
#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 …
#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 …
#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 …
#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 …
#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 …
#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 …
#define mmREGAMMA_CNTLB_REGION_4_5 …
#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 …
#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 …
#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 …
#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 …
#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 …
#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 …
#define mmREGAMMA_CNTLB_REGION_6_7 …
#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 …
#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 …
#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 …
#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 …
#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 …
#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 …
#define mmREGAMMA_CNTLB_REGION_8_9 …
#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 …
#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 …
#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 …
#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 …
#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 …
#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 …
#define mmREGAMMA_CNTLB_REGION_10_11 …
#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 …
#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 …
#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 …
#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 …
#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 …
#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 …
#define mmREGAMMA_CNTLB_REGION_12_13 …
#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 …
#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 …
#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 …
#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 …
#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 …
#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 …
#define mmREGAMMA_CNTLB_REGION_14_15 …
#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 …
#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 …
#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 …
#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 …
#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 …
#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 …
#define mmALPHA_CONTROL …
#define mmDCP0_ALPHA_CONTROL …
#define mmDCP1_ALPHA_CONTROL …
#define mmDCP2_ALPHA_CONTROL …
#define mmDCP3_ALPHA_CONTROL …
#define mmDCP4_ALPHA_CONTROL …
#define mmDCP5_ALPHA_CONTROL …
#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS …
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS …
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS …
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS …
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS …
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS …
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS …
#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH …
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH …
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH …
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH …
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH …
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH …
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH …
#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS …
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS …
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS …
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS …
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS …
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS …
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS …
#define mmDIG_FE_CNTL …
#define mmDIG0_DIG_FE_CNTL …
#define mmDIG1_DIG_FE_CNTL …
#define mmDIG2_DIG_FE_CNTL …
#define mmDIG3_DIG_FE_CNTL …
#define mmDIG4_DIG_FE_CNTL …
#define mmDIG5_DIG_FE_CNTL …
#define mmDIG6_DIG_FE_CNTL …
#define mmDIG_OUTPUT_CRC_CNTL …
#define mmDIG0_DIG_OUTPUT_CRC_CNTL …
#define mmDIG1_DIG_OUTPUT_CRC_CNTL …
#define mmDIG2_DIG_OUTPUT_CRC_CNTL …
#define mmDIG3_DIG_OUTPUT_CRC_CNTL …
#define mmDIG4_DIG_OUTPUT_CRC_CNTL …
#define mmDIG5_DIG_OUTPUT_CRC_CNTL …
#define mmDIG6_DIG_OUTPUT_CRC_CNTL …
#define mmDIG_OUTPUT_CRC_RESULT …
#define mmDIG0_DIG_OUTPUT_CRC_RESULT …
#define mmDIG1_DIG_OUTPUT_CRC_RESULT …
#define mmDIG2_DIG_OUTPUT_CRC_RESULT …
#define mmDIG3_DIG_OUTPUT_CRC_RESULT …
#define mmDIG4_DIG_OUTPUT_CRC_RESULT …
#define mmDIG5_DIG_OUTPUT_CRC_RESULT …
#define mmDIG6_DIG_OUTPUT_CRC_RESULT …
#define mmDIG_CLOCK_PATTERN …
#define mmDIG0_DIG_CLOCK_PATTERN …
#define mmDIG1_DIG_CLOCK_PATTERN …
#define mmDIG2_DIG_CLOCK_PATTERN …
#define mmDIG3_DIG_CLOCK_PATTERN …
#define mmDIG4_DIG_CLOCK_PATTERN …
#define mmDIG5_DIG_CLOCK_PATTERN …
#define mmDIG6_DIG_CLOCK_PATTERN …
#define mmDIG_TEST_PATTERN …
#define mmDIG0_DIG_TEST_PATTERN …
#define mmDIG1_DIG_TEST_PATTERN …
#define mmDIG2_DIG_TEST_PATTERN …
#define mmDIG3_DIG_TEST_PATTERN …
#define mmDIG4_DIG_TEST_PATTERN …
#define mmDIG5_DIG_TEST_PATTERN …
#define mmDIG6_DIG_TEST_PATTERN …
#define mmDIG_RANDOM_PATTERN_SEED …
#define mmDIG0_DIG_RANDOM_PATTERN_SEED …
#define mmDIG1_DIG_RANDOM_PATTERN_SEED …
#define mmDIG2_DIG_RANDOM_PATTERN_SEED …
#define mmDIG3_DIG_RANDOM_PATTERN_SEED …
#define mmDIG4_DIG_RANDOM_PATTERN_SEED …
#define mmDIG5_DIG_RANDOM_PATTERN_SEED …
#define mmDIG6_DIG_RANDOM_PATTERN_SEED …
#define mmDIG_FIFO_STATUS …
#define mmDIG0_DIG_FIFO_STATUS …
#define mmDIG1_DIG_FIFO_STATUS …
#define mmDIG2_DIG_FIFO_STATUS …
#define mmDIG3_DIG_FIFO_STATUS …
#define mmDIG4_DIG_FIFO_STATUS …
#define mmDIG5_DIG_FIFO_STATUS …
#define mmDIG6_DIG_FIFO_STATUS …
#define mmDIG_DISPCLK_SWITCH_CNTL …
#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL …
#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL …
#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL …
#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL …
#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL …
#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL …
#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL …
#define mmDIG_DISPCLK_SWITCH_STATUS …
#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS …
#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS …
#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS …
#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS …
#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS …
#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS …
#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS …
#define mmHDMI_CONTROL …
#define mmDIG0_HDMI_CONTROL …
#define mmDIG1_HDMI_CONTROL …
#define mmDIG2_HDMI_CONTROL …
#define mmDIG3_HDMI_CONTROL …
#define mmDIG4_HDMI_CONTROL …
#define mmDIG5_HDMI_CONTROL …
#define mmDIG6_HDMI_CONTROL …
#define mmHDMI_STATUS …
#define mmDIG0_HDMI_STATUS …
#define mmDIG1_HDMI_STATUS …
#define mmDIG2_HDMI_STATUS …
#define mmDIG3_HDMI_STATUS …
#define mmDIG4_HDMI_STATUS …
#define mmDIG5_HDMI_STATUS …
#define mmDIG6_HDMI_STATUS …
#define mmHDMI_AUDIO_PACKET_CONTROL …
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL …
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL …
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL …
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL …
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL …
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL …
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL …
#define mmHDMI_ACR_PACKET_CONTROL …
#define mmDIG0_HDMI_ACR_PACKET_CONTROL …
#define mmDIG1_HDMI_ACR_PACKET_CONTROL …
#define mmDIG2_HDMI_ACR_PACKET_CONTROL …
#define mmDIG3_HDMI_ACR_PACKET_CONTROL …
#define mmDIG4_HDMI_ACR_PACKET_CONTROL …
#define mmDIG5_HDMI_ACR_PACKET_CONTROL …
#define mmDIG6_HDMI_ACR_PACKET_CONTROL …
#define mmHDMI_VBI_PACKET_CONTROL …
#define mmDIG0_HDMI_VBI_PACKET_CONTROL …
#define mmDIG1_HDMI_VBI_PACKET_CONTROL …
#define mmDIG2_HDMI_VBI_PACKET_CONTROL …
#define mmDIG3_HDMI_VBI_PACKET_CONTROL …
#define mmDIG4_HDMI_VBI_PACKET_CONTROL …
#define mmDIG5_HDMI_VBI_PACKET_CONTROL …
#define mmDIG6_HDMI_VBI_PACKET_CONTROL …
#define mmHDMI_INFOFRAME_CONTROL0 …
#define mmDIG0_HDMI_INFOFRAME_CONTROL0 …
#define mmDIG1_HDMI_INFOFRAME_CONTROL0 …
#define mmDIG2_HDMI_INFOFRAME_CONTROL0 …
#define mmDIG3_HDMI_INFOFRAME_CONTROL0 …
#define mmDIG4_HDMI_INFOFRAME_CONTROL0 …
#define mmDIG5_HDMI_INFOFRAME_CONTROL0 …
#define mmDIG6_HDMI_INFOFRAME_CONTROL0 …
#define mmHDMI_INFOFRAME_CONTROL1 …
#define mmDIG0_HDMI_INFOFRAME_CONTROL1 …
#define mmDIG1_HDMI_INFOFRAME_CONTROL1 …
#define mmDIG2_HDMI_INFOFRAME_CONTROL1 …
#define mmDIG3_HDMI_INFOFRAME_CONTROL1 …
#define mmDIG4_HDMI_INFOFRAME_CONTROL1 …
#define mmDIG5_HDMI_INFOFRAME_CONTROL1 …
#define mmDIG6_HDMI_INFOFRAME_CONTROL1 …
#define mmHDMI_GENERIC_PACKET_CONTROL0 …
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 …
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 …
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 …
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 …
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 …
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 …
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 …
#define mmAFMT_INTERRUPT_STATUS …
#define mmDIG0_AFMT_INTERRUPT_STATUS …
#define mmDIG1_AFMT_INTERRUPT_STATUS …
#define mmDIG2_AFMT_INTERRUPT_STATUS …
#define mmDIG3_AFMT_INTERRUPT_STATUS …
#define mmDIG4_AFMT_INTERRUPT_STATUS …
#define mmDIG5_AFMT_INTERRUPT_STATUS …
#define mmDIG6_AFMT_INTERRUPT_STATUS …
#define mmHDMI_GC …
#define mmDIG0_HDMI_GC …
#define mmDIG1_HDMI_GC …
#define mmDIG2_HDMI_GC …
#define mmDIG3_HDMI_GC …
#define mmDIG4_HDMI_GC …
#define mmDIG5_HDMI_GC …
#define mmDIG6_HDMI_GC …
#define mmAFMT_AUDIO_PACKET_CONTROL2 …
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 …
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 …
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 …
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 …
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 …
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 …
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 …
#define mmAFMT_ISRC1_0 …
#define mmDIG0_AFMT_ISRC1_0 …
#define mmDIG1_AFMT_ISRC1_0 …
#define mmDIG2_AFMT_ISRC1_0 …
#define mmDIG3_AFMT_ISRC1_0 …
#define mmDIG4_AFMT_ISRC1_0 …
#define mmDIG5_AFMT_ISRC1_0 …
#define mmDIG6_AFMT_ISRC1_0 …
#define mmAFMT_ISRC1_1 …
#define mmDIG0_AFMT_ISRC1_1 …
#define mmDIG1_AFMT_ISRC1_1 …
#define mmDIG2_AFMT_ISRC1_1 …
#define mmDIG3_AFMT_ISRC1_1 …
#define mmDIG4_AFMT_ISRC1_1 …
#define mmDIG5_AFMT_ISRC1_1 …
#define mmDIG6_AFMT_ISRC1_1 …
#define mmAFMT_ISRC1_2 …
#define mmDIG0_AFMT_ISRC1_2 …
#define mmDIG1_AFMT_ISRC1_2 …
#define mmDIG2_AFMT_ISRC1_2 …
#define mmDIG3_AFMT_ISRC1_2 …
#define mmDIG4_AFMT_ISRC1_2 …
#define mmDIG5_AFMT_ISRC1_2 …
#define mmDIG6_AFMT_ISRC1_2 …
#define mmAFMT_ISRC1_3 …
#define mmDIG0_AFMT_ISRC1_3 …
#define mmDIG1_AFMT_ISRC1_3 …
#define mmDIG2_AFMT_ISRC1_3 …
#define mmDIG3_AFMT_ISRC1_3 …
#define mmDIG4_AFMT_ISRC1_3 …
#define mmDIG5_AFMT_ISRC1_3 …
#define mmDIG6_AFMT_ISRC1_3 …
#define mmAFMT_ISRC1_4 …
#define mmDIG0_AFMT_ISRC1_4 …
#define mmDIG1_AFMT_ISRC1_4 …
#define mmDIG2_AFMT_ISRC1_4 …
#define mmDIG3_AFMT_ISRC1_4 …
#define mmDIG4_AFMT_ISRC1_4 …
#define mmDIG5_AFMT_ISRC1_4 …
#define mmDIG6_AFMT_ISRC1_4 …
#define mmAFMT_ISRC2_0 …
#define mmDIG0_AFMT_ISRC2_0 …
#define mmDIG1_AFMT_ISRC2_0 …
#define mmDIG2_AFMT_ISRC2_0 …
#define mmDIG3_AFMT_ISRC2_0 …
#define mmDIG4_AFMT_ISRC2_0 …
#define mmDIG5_AFMT_ISRC2_0 …
#define mmDIG6_AFMT_ISRC2_0 …
#define mmAFMT_ISRC2_1 …
#define mmDIG0_AFMT_ISRC2_1 …
#define mmDIG1_AFMT_ISRC2_1 …
#define mmDIG2_AFMT_ISRC2_1 …
#define mmDIG3_AFMT_ISRC2_1 …
#define mmDIG4_AFMT_ISRC2_1 …
#define mmDIG5_AFMT_ISRC2_1 …
#define mmDIG6_AFMT_ISRC2_1 …
#define mmAFMT_ISRC2_2 …
#define mmDIG0_AFMT_ISRC2_2 …
#define mmDIG1_AFMT_ISRC2_2 …
#define mmDIG2_AFMT_ISRC2_2 …
#define mmDIG3_AFMT_ISRC2_2 …
#define mmDIG4_AFMT_ISRC2_2 …
#define mmDIG5_AFMT_ISRC2_2 …
#define mmDIG6_AFMT_ISRC2_2 …
#define mmAFMT_ISRC2_3 …
#define mmDIG0_AFMT_ISRC2_3 …
#define mmDIG1_AFMT_ISRC2_3 …
#define mmDIG2_AFMT_ISRC2_3 …
#define mmDIG3_AFMT_ISRC2_3 …
#define mmDIG4_AFMT_ISRC2_3 …
#define mmDIG5_AFMT_ISRC2_3 …
#define mmDIG6_AFMT_ISRC2_3 …
#define mmAFMT_AVI_INFO0 …
#define mmDIG0_AFMT_AVI_INFO0 …
#define mmDIG1_AFMT_AVI_INFO0 …
#define mmDIG2_AFMT_AVI_INFO0 …
#define mmDIG3_AFMT_AVI_INFO0 …
#define mmDIG4_AFMT_AVI_INFO0 …
#define mmDIG5_AFMT_AVI_INFO0 …
#define mmDIG6_AFMT_AVI_INFO0 …
#define mmAFMT_AVI_INFO1 …
#define mmDIG0_AFMT_AVI_INFO1 …
#define mmDIG1_AFMT_AVI_INFO1 …
#define mmDIG2_AFMT_AVI_INFO1 …
#define mmDIG3_AFMT_AVI_INFO1 …
#define mmDIG4_AFMT_AVI_INFO1 …
#define mmDIG5_AFMT_AVI_INFO1 …
#define mmDIG6_AFMT_AVI_INFO1 …
#define mmAFMT_AVI_INFO2 …
#define mmDIG0_AFMT_AVI_INFO2 …
#define mmDIG1_AFMT_AVI_INFO2 …
#define mmDIG2_AFMT_AVI_INFO2 …
#define mmDIG3_AFMT_AVI_INFO2 …
#define mmDIG4_AFMT_AVI_INFO2 …
#define mmDIG5_AFMT_AVI_INFO2 …
#define mmDIG6_AFMT_AVI_INFO2 …
#define mmAFMT_AVI_INFO3 …
#define mmDIG0_AFMT_AVI_INFO3 …
#define mmDIG1_AFMT_AVI_INFO3 …
#define mmDIG2_AFMT_AVI_INFO3 …
#define mmDIG3_AFMT_AVI_INFO3 …
#define mmDIG4_AFMT_AVI_INFO3 …
#define mmDIG5_AFMT_AVI_INFO3 …
#define mmDIG6_AFMT_AVI_INFO3 …
#define mmAFMT_MPEG_INFO0 …
#define mmDIG0_AFMT_MPEG_INFO0 …
#define mmDIG1_AFMT_MPEG_INFO0 …
#define mmDIG2_AFMT_MPEG_INFO0 …
#define mmDIG3_AFMT_MPEG_INFO0 …
#define mmDIG4_AFMT_MPEG_INFO0 …
#define mmDIG5_AFMT_MPEG_INFO0 …
#define mmDIG6_AFMT_MPEG_INFO0 …
#define mmAFMT_MPEG_INFO1 …
#define mmDIG0_AFMT_MPEG_INFO1 …
#define mmDIG1_AFMT_MPEG_INFO1 …
#define mmDIG2_AFMT_MPEG_INFO1 …
#define mmDIG3_AFMT_MPEG_INFO1 …
#define mmDIG4_AFMT_MPEG_INFO1 …
#define mmDIG5_AFMT_MPEG_INFO1 …
#define mmDIG6_AFMT_MPEG_INFO1 …
#define mmAFMT_GENERIC_HDR …
#define mmDIG0_AFMT_GENERIC_HDR …
#define mmDIG1_AFMT_GENERIC_HDR …
#define mmDIG2_AFMT_GENERIC_HDR …
#define mmDIG3_AFMT_GENERIC_HDR …
#define mmDIG4_AFMT_GENERIC_HDR …
#define mmDIG5_AFMT_GENERIC_HDR …
#define mmDIG6_AFMT_GENERIC_HDR …
#define mmAFMT_GENERIC_0 …
#define mmDIG0_AFMT_GENERIC_0 …
#define mmDIG1_AFMT_GENERIC_0 …
#define mmDIG2_AFMT_GENERIC_0 …
#define mmDIG3_AFMT_GENERIC_0 …
#define mmDIG4_AFMT_GENERIC_0 …
#define mmDIG5_AFMT_GENERIC_0 …
#define mmDIG6_AFMT_GENERIC_0 …
#define mmAFMT_GENERIC_1 …
#define mmDIG0_AFMT_GENERIC_1 …
#define mmDIG1_AFMT_GENERIC_1 …
#define mmDIG2_AFMT_GENERIC_1 …
#define mmDIG3_AFMT_GENERIC_1 …
#define mmDIG4_AFMT_GENERIC_1 …
#define mmDIG5_AFMT_GENERIC_1 …
#define mmDIG6_AFMT_GENERIC_1 …
#define mmAFMT_GENERIC_2 …
#define mmDIG0_AFMT_GENERIC_2 …
#define mmDIG1_AFMT_GENERIC_2 …
#define mmDIG2_AFMT_GENERIC_2 …
#define mmDIG3_AFMT_GENERIC_2 …
#define mmDIG4_AFMT_GENERIC_2 …
#define mmDIG5_AFMT_GENERIC_2 …
#define mmDIG6_AFMT_GENERIC_2 …
#define mmAFMT_GENERIC_3 …
#define mmDIG0_AFMT_GENERIC_3 …
#define mmDIG1_AFMT_GENERIC_3 …
#define mmDIG2_AFMT_GENERIC_3 …
#define mmDIG3_AFMT_GENERIC_3 …
#define mmDIG4_AFMT_GENERIC_3 …
#define mmDIG5_AFMT_GENERIC_3 …
#define mmDIG6_AFMT_GENERIC_3 …
#define mmAFMT_GENERIC_4 …
#define mmDIG0_AFMT_GENERIC_4 …
#define mmDIG1_AFMT_GENERIC_4 …
#define mmDIG2_AFMT_GENERIC_4 …
#define mmDIG3_AFMT_GENERIC_4 …
#define mmDIG4_AFMT_GENERIC_4 …
#define mmDIG5_AFMT_GENERIC_4 …
#define mmDIG6_AFMT_GENERIC_4 …
#define mmAFMT_GENERIC_5 …
#define mmDIG0_AFMT_GENERIC_5 …
#define mmDIG1_AFMT_GENERIC_5 …
#define mmDIG2_AFMT_GENERIC_5 …
#define mmDIG3_AFMT_GENERIC_5 …
#define mmDIG4_AFMT_GENERIC_5 …
#define mmDIG5_AFMT_GENERIC_5 …
#define mmDIG6_AFMT_GENERIC_5 …
#define mmAFMT_GENERIC_6 …
#define mmDIG0_AFMT_GENERIC_6 …
#define mmDIG1_AFMT_GENERIC_6 …
#define mmDIG2_AFMT_GENERIC_6 …
#define mmDIG3_AFMT_GENERIC_6 …
#define mmDIG4_AFMT_GENERIC_6 …
#define mmDIG5_AFMT_GENERIC_6 …
#define mmDIG6_AFMT_GENERIC_6 …
#define mmAFMT_GENERIC_7 …
#define mmDIG0_AFMT_GENERIC_7 …
#define mmDIG1_AFMT_GENERIC_7 …
#define mmDIG2_AFMT_GENERIC_7 …
#define mmDIG3_AFMT_GENERIC_7 …
#define mmDIG4_AFMT_GENERIC_7 …
#define mmDIG5_AFMT_GENERIC_7 …
#define mmDIG6_AFMT_GENERIC_7 …
#define mmHDMI_GENERIC_PACKET_CONTROL1 …
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 …
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 …
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 …
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 …
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 …
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 …
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 …
#define mmHDMI_ACR_32_0 …
#define mmDIG0_HDMI_ACR_32_0 …
#define mmDIG1_HDMI_ACR_32_0 …
#define mmDIG2_HDMI_ACR_32_0 …
#define mmDIG3_HDMI_ACR_32_0 …
#define mmDIG4_HDMI_ACR_32_0 …
#define mmDIG5_HDMI_ACR_32_0 …
#define mmDIG6_HDMI_ACR_32_0 …
#define mmHDMI_ACR_32_1 …
#define mmDIG0_HDMI_ACR_32_1 …
#define mmDIG1_HDMI_ACR_32_1 …
#define mmDIG2_HDMI_ACR_32_1 …
#define mmDIG3_HDMI_ACR_32_1 …
#define mmDIG4_HDMI_ACR_32_1 …
#define mmDIG5_HDMI_ACR_32_1 …
#define mmDIG6_HDMI_ACR_32_1 …
#define mmHDMI_ACR_44_0 …
#define mmDIG0_HDMI_ACR_44_0 …
#define mmDIG1_HDMI_ACR_44_0 …
#define mmDIG2_HDMI_ACR_44_0 …
#define mmDIG3_HDMI_ACR_44_0 …
#define mmDIG4_HDMI_ACR_44_0 …
#define mmDIG5_HDMI_ACR_44_0 …
#define mmDIG6_HDMI_ACR_44_0 …
#define mmHDMI_ACR_44_1 …
#define mmDIG0_HDMI_ACR_44_1 …
#define mmDIG1_HDMI_ACR_44_1 …
#define mmDIG2_HDMI_ACR_44_1 …
#define mmDIG3_HDMI_ACR_44_1 …
#define mmDIG4_HDMI_ACR_44_1 …
#define mmDIG5_HDMI_ACR_44_1 …
#define mmDIG6_HDMI_ACR_44_1 …
#define mmHDMI_ACR_48_0 …
#define mmDIG0_HDMI_ACR_48_0 …
#define mmDIG1_HDMI_ACR_48_0 …
#define mmDIG2_HDMI_ACR_48_0 …
#define mmDIG3_HDMI_ACR_48_0 …
#define mmDIG4_HDMI_ACR_48_0 …
#define mmDIG5_HDMI_ACR_48_0 …
#define mmDIG6_HDMI_ACR_48_0 …
#define mmHDMI_ACR_48_1 …
#define mmDIG0_HDMI_ACR_48_1 …
#define mmDIG1_HDMI_ACR_48_1 …
#define mmDIG2_HDMI_ACR_48_1 …
#define mmDIG3_HDMI_ACR_48_1 …
#define mmDIG4_HDMI_ACR_48_1 …
#define mmDIG5_HDMI_ACR_48_1 …
#define mmDIG6_HDMI_ACR_48_1 …
#define mmHDMI_ACR_STATUS_0 …
#define mmDIG0_HDMI_ACR_STATUS_0 …
#define mmDIG1_HDMI_ACR_STATUS_0 …
#define mmDIG2_HDMI_ACR_STATUS_0 …
#define mmDIG3_HDMI_ACR_STATUS_0 …
#define mmDIG4_HDMI_ACR_STATUS_0 …
#define mmDIG5_HDMI_ACR_STATUS_0 …
#define mmDIG6_HDMI_ACR_STATUS_0 …
#define mmHDMI_ACR_STATUS_1 …
#define mmDIG0_HDMI_ACR_STATUS_1 …
#define mmDIG1_HDMI_ACR_STATUS_1 …
#define mmDIG2_HDMI_ACR_STATUS_1 …
#define mmDIG3_HDMI_ACR_STATUS_1 …
#define mmDIG4_HDMI_ACR_STATUS_1 …
#define mmDIG5_HDMI_ACR_STATUS_1 …
#define mmDIG6_HDMI_ACR_STATUS_1 …
#define mmAFMT_AUDIO_INFO0 …
#define mmDIG0_AFMT_AUDIO_INFO0 …
#define mmDIG1_AFMT_AUDIO_INFO0 …
#define mmDIG2_AFMT_AUDIO_INFO0 …
#define mmDIG3_AFMT_AUDIO_INFO0 …
#define mmDIG4_AFMT_AUDIO_INFO0 …
#define mmDIG5_AFMT_AUDIO_INFO0 …
#define mmDIG6_AFMT_AUDIO_INFO0 …
#define mmAFMT_AUDIO_INFO1 …
#define mmDIG0_AFMT_AUDIO_INFO1 …
#define mmDIG1_AFMT_AUDIO_INFO1 …
#define mmDIG2_AFMT_AUDIO_INFO1 …
#define mmDIG3_AFMT_AUDIO_INFO1 …
#define mmDIG4_AFMT_AUDIO_INFO1 …
#define mmDIG5_AFMT_AUDIO_INFO1 …
#define mmDIG6_AFMT_AUDIO_INFO1 …
#define mmAFMT_60958_0 …
#define mmDIG0_AFMT_60958_0 …
#define mmDIG1_AFMT_60958_0 …
#define mmDIG2_AFMT_60958_0 …
#define mmDIG3_AFMT_60958_0 …
#define mmDIG4_AFMT_60958_0 …
#define mmDIG5_AFMT_60958_0 …
#define mmDIG6_AFMT_60958_0 …
#define mmAFMT_60958_1 …
#define mmDIG0_AFMT_60958_1 …
#define mmDIG1_AFMT_60958_1 …
#define mmDIG2_AFMT_60958_1 …
#define mmDIG3_AFMT_60958_1 …
#define mmDIG4_AFMT_60958_1 …
#define mmDIG5_AFMT_60958_1 …
#define mmDIG6_AFMT_60958_1 …
#define mmAFMT_AUDIO_CRC_CONTROL …
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL …
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL …
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL …
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL …
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL …
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL …
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL …
#define mmAFMT_RAMP_CONTROL0 …
#define mmDIG0_AFMT_RAMP_CONTROL0 …
#define mmDIG1_AFMT_RAMP_CONTROL0 …
#define mmDIG2_AFMT_RAMP_CONTROL0 …
#define mmDIG3_AFMT_RAMP_CONTROL0 …
#define mmDIG4_AFMT_RAMP_CONTROL0 …
#define mmDIG5_AFMT_RAMP_CONTROL0 …
#define mmDIG6_AFMT_RAMP_CONTROL0 …
#define mmAFMT_RAMP_CONTROL1 …
#define mmDIG0_AFMT_RAMP_CONTROL1 …
#define mmDIG1_AFMT_RAMP_CONTROL1 …
#define mmDIG2_AFMT_RAMP_CONTROL1 …
#define mmDIG3_AFMT_RAMP_CONTROL1 …
#define mmDIG4_AFMT_RAMP_CONTROL1 …
#define mmDIG5_AFMT_RAMP_CONTROL1 …
#define mmDIG6_AFMT_RAMP_CONTROL1 …
#define mmAFMT_RAMP_CONTROL2 …
#define mmDIG0_AFMT_RAMP_CONTROL2 …
#define mmDIG1_AFMT_RAMP_CONTROL2 …
#define mmDIG2_AFMT_RAMP_CONTROL2 …
#define mmDIG3_AFMT_RAMP_CONTROL2 …
#define mmDIG4_AFMT_RAMP_CONTROL2 …
#define mmDIG5_AFMT_RAMP_CONTROL2 …
#define mmDIG6_AFMT_RAMP_CONTROL2 …
#define mmAFMT_RAMP_CONTROL3 …
#define mmDIG0_AFMT_RAMP_CONTROL3 …
#define mmDIG1_AFMT_RAMP_CONTROL3 …
#define mmDIG2_AFMT_RAMP_CONTROL3 …
#define mmDIG3_AFMT_RAMP_CONTROL3 …
#define mmDIG4_AFMT_RAMP_CONTROL3 …
#define mmDIG5_AFMT_RAMP_CONTROL3 …
#define mmDIG6_AFMT_RAMP_CONTROL3 …
#define mmAFMT_60958_2 …
#define mmDIG0_AFMT_60958_2 …
#define mmDIG1_AFMT_60958_2 …
#define mmDIG2_AFMT_60958_2 …
#define mmDIG3_AFMT_60958_2 …
#define mmDIG4_AFMT_60958_2 …
#define mmDIG5_AFMT_60958_2 …
#define mmDIG6_AFMT_60958_2 …
#define mmAFMT_AUDIO_CRC_RESULT …
#define mmDIG0_AFMT_AUDIO_CRC_RESULT …
#define mmDIG1_AFMT_AUDIO_CRC_RESULT …
#define mmDIG2_AFMT_AUDIO_CRC_RESULT …
#define mmDIG3_AFMT_AUDIO_CRC_RESULT …
#define mmDIG4_AFMT_AUDIO_CRC_RESULT …
#define mmDIG5_AFMT_AUDIO_CRC_RESULT …
#define mmDIG6_AFMT_AUDIO_CRC_RESULT …
#define mmAFMT_STATUS …
#define mmDIG0_AFMT_STATUS …
#define mmDIG1_AFMT_STATUS …
#define mmDIG2_AFMT_STATUS …
#define mmDIG3_AFMT_STATUS …
#define mmDIG4_AFMT_STATUS …
#define mmDIG5_AFMT_STATUS …
#define mmDIG6_AFMT_STATUS …
#define mmAFMT_AUDIO_PACKET_CONTROL …
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL …
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL …
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL …
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL …
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL …
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL …
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL …
#define mmAFMT_VBI_PACKET_CONTROL …
#define mmDIG0_AFMT_VBI_PACKET_CONTROL …
#define mmDIG1_AFMT_VBI_PACKET_CONTROL …
#define mmDIG2_AFMT_VBI_PACKET_CONTROL …
#define mmDIG3_AFMT_VBI_PACKET_CONTROL …
#define mmDIG4_AFMT_VBI_PACKET_CONTROL …
#define mmDIG5_AFMT_VBI_PACKET_CONTROL …
#define mmDIG6_AFMT_VBI_PACKET_CONTROL …
#define mmAFMT_INFOFRAME_CONTROL0 …
#define mmDIG0_AFMT_INFOFRAME_CONTROL0 …
#define mmDIG1_AFMT_INFOFRAME_CONTROL0 …
#define mmDIG2_AFMT_INFOFRAME_CONTROL0 …
#define mmDIG3_AFMT_INFOFRAME_CONTROL0 …
#define mmDIG4_AFMT_INFOFRAME_CONTROL0 …
#define mmDIG5_AFMT_INFOFRAME_CONTROL0 …
#define mmDIG6_AFMT_INFOFRAME_CONTROL0 …
#define mmAFMT_AUDIO_SRC_CONTROL …
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL …
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL …
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL …
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL …
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL …
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL …
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL …
#define mmAFMT_AUDIO_DBG_DTO_CNTL …
#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL …
#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL …
#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL …
#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL …
#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL …
#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL …
#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL …
#define mmDIG_BE_CNTL …
#define mmDIG0_DIG_BE_CNTL …
#define mmDIG1_DIG_BE_CNTL …
#define mmDIG2_DIG_BE_CNTL …
#define mmDIG3_DIG_BE_CNTL …
#define mmDIG4_DIG_BE_CNTL …
#define mmDIG5_DIG_BE_CNTL …
#define mmDIG6_DIG_BE_CNTL …
#define mmDIG_BE_EN_CNTL …
#define mmDIG0_DIG_BE_EN_CNTL …
#define mmDIG1_DIG_BE_EN_CNTL …
#define mmDIG2_DIG_BE_EN_CNTL …
#define mmDIG3_DIG_BE_EN_CNTL …
#define mmDIG4_DIG_BE_EN_CNTL …
#define mmDIG5_DIG_BE_EN_CNTL …
#define mmDIG6_DIG_BE_EN_CNTL …
#define mmTMDS_CNTL …
#define mmDIG0_TMDS_CNTL …
#define mmDIG1_TMDS_CNTL …
#define mmDIG2_TMDS_CNTL …
#define mmDIG3_TMDS_CNTL …
#define mmDIG4_TMDS_CNTL …
#define mmDIG5_TMDS_CNTL …
#define mmDIG6_TMDS_CNTL …
#define mmTMDS_CONTROL_CHAR …
#define mmDIG0_TMDS_CONTROL_CHAR …
#define mmDIG1_TMDS_CONTROL_CHAR …
#define mmDIG2_TMDS_CONTROL_CHAR …
#define mmDIG3_TMDS_CONTROL_CHAR …
#define mmDIG4_TMDS_CONTROL_CHAR …
#define mmDIG5_TMDS_CONTROL_CHAR …
#define mmDIG6_TMDS_CONTROL_CHAR …
#define mmTMDS_CONTROL0_FEEDBACK …
#define mmDIG0_TMDS_CONTROL0_FEEDBACK …
#define mmDIG1_TMDS_CONTROL0_FEEDBACK …
#define mmDIG2_TMDS_CONTROL0_FEEDBACK …
#define mmDIG3_TMDS_CONTROL0_FEEDBACK …
#define mmDIG4_TMDS_CONTROL0_FEEDBACK …
#define mmDIG5_TMDS_CONTROL0_FEEDBACK …
#define mmDIG6_TMDS_CONTROL0_FEEDBACK …
#define mmTMDS_STEREOSYNC_CTL_SEL …
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL …
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL …
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL …
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL …
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL …
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL …
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL …
#define mmTMDS_SYNC_CHAR_PATTERN_0_1 …
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 …
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 …
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 …
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 …
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 …
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 …
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 …
#define mmTMDS_SYNC_CHAR_PATTERN_2_3 …
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 …
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 …
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 …
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 …
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 …
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 …
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 …
#define mmTMDS_DEBUG …
#define mmDIG0_TMDS_DEBUG …
#define mmDIG1_TMDS_DEBUG …
#define mmDIG2_TMDS_DEBUG …
#define mmDIG3_TMDS_DEBUG …
#define mmDIG4_TMDS_DEBUG …
#define mmDIG5_TMDS_DEBUG …
#define mmDIG6_TMDS_DEBUG …
#define mmTMDS_CTL_BITS …
#define mmDIG0_TMDS_CTL_BITS …
#define mmDIG1_TMDS_CTL_BITS …
#define mmDIG2_TMDS_CTL_BITS …
#define mmDIG3_TMDS_CTL_BITS …
#define mmDIG4_TMDS_CTL_BITS …
#define mmDIG5_TMDS_CTL_BITS …
#define mmDIG6_TMDS_CTL_BITS …
#define mmTMDS_DCBALANCER_CONTROL …
#define mmDIG0_TMDS_DCBALANCER_CONTROL …
#define mmDIG1_TMDS_DCBALANCER_CONTROL …
#define mmDIG2_TMDS_DCBALANCER_CONTROL …
#define mmDIG3_TMDS_DCBALANCER_CONTROL …
#define mmDIG4_TMDS_DCBALANCER_CONTROL …
#define mmDIG5_TMDS_DCBALANCER_CONTROL …
#define mmDIG6_TMDS_DCBALANCER_CONTROL …
#define mmTMDS_CTL0_1_GEN_CNTL …
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL …
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL …
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL …
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL …
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL …
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL …
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL …
#define mmTMDS_CTL2_3_GEN_CNTL …
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL …
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL …
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL …
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL …
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL …
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL …
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL …
#define mmLVDS_DATA_CNTL …
#define mmDIG0_LVDS_DATA_CNTL …
#define mmDIG1_LVDS_DATA_CNTL …
#define mmDIG2_LVDS_DATA_CNTL …
#define mmDIG3_LVDS_DATA_CNTL …
#define mmDIG4_LVDS_DATA_CNTL …
#define mmDIG5_LVDS_DATA_CNTL …
#define mmDIG6_LVDS_DATA_CNTL …
#define mmDIG_LANE_ENABLE …
#define mmDIG0_DIG_LANE_ENABLE …
#define mmDIG1_DIG_LANE_ENABLE …
#define mmDIG2_DIG_LANE_ENABLE …
#define mmDIG3_DIG_LANE_ENABLE …
#define mmDIG4_DIG_LANE_ENABLE …
#define mmDIG5_DIG_LANE_ENABLE …
#define mmDIG6_DIG_LANE_ENABLE …
#define mmDOUT_SCRATCH0 …
#define mmDOUT_SCRATCH1 …
#define mmDOUT_SCRATCH2 …
#define mmDOUT_SCRATCH3 …
#define mmDOUT_SCRATCH4 …
#define mmDOUT_SCRATCH5 …
#define mmDOUT_SCRATCH6 …
#define mmDOUT_SCRATCH7 …
#define mmDOUT_DCE_VCE_CONTROL …
#define mmDC_HPD1_INT_STATUS …
#define mmDC_HPD1_INT_CONTROL …
#define mmDC_HPD1_CONTROL …
#define mmDC_HPD2_INT_STATUS …
#define mmDC_HPD2_INT_CONTROL …
#define mmDC_HPD2_CONTROL …
#define mmDC_HPD3_INT_STATUS …
#define mmDC_HPD3_INT_CONTROL …
#define mmDC_HPD3_CONTROL …
#define mmDC_HPD4_INT_STATUS …
#define mmDC_HPD4_INT_CONTROL …
#define mmDC_HPD4_CONTROL …
#define mmDC_HPD5_INT_STATUS …
#define mmDC_HPD5_INT_CONTROL …
#define mmDC_HPD5_CONTROL …
#define mmDC_HPD6_INT_STATUS …
#define mmDC_HPD6_INT_CONTROL …
#define mmDC_HPD6_CONTROL …
#define mmDC_HPD1_FAST_TRAIN_CNTL …
#define mmDC_HPD2_FAST_TRAIN_CNTL …
#define mmDC_HPD3_FAST_TRAIN_CNTL …
#define mmDC_HPD4_FAST_TRAIN_CNTL …
#define mmDC_HPD5_FAST_TRAIN_CNTL …
#define mmDC_HPD6_FAST_TRAIN_CNTL …
#define mmDC_HPD1_TOGGLE_FILT_CNTL …
#define mmDC_HPD2_TOGGLE_FILT_CNTL …
#define mmDC_HPD3_TOGGLE_FILT_CNTL …
#define mmDC_HPD4_TOGGLE_FILT_CNTL …
#define mmDC_HPD5_TOGGLE_FILT_CNTL …
#define mmDC_HPD6_TOGGLE_FILT_CNTL …
#define mmDC_I2C_CONTROL …
#define mmDC_I2C_ARBITRATION …
#define mmDC_I2C_INTERRUPT_CONTROL …
#define mmDC_I2C_SW_STATUS …
#define mmDC_I2C_DDC1_HW_STATUS …
#define mmDC_I2C_DDC2_HW_STATUS …
#define mmDC_I2C_DDC3_HW_STATUS …
#define mmDC_I2C_DDC4_HW_STATUS …
#define mmDC_I2C_DDC5_HW_STATUS …
#define mmDC_I2C_DDC6_HW_STATUS …
#define mmDC_I2C_DDC1_SPEED …
#define mmDC_I2C_DDC1_SETUP …
#define mmDC_I2C_DDC2_SPEED …
#define mmDC_I2C_DDC2_SETUP …
#define mmDC_I2C_DDC3_SPEED …
#define mmDC_I2C_DDC3_SETUP …
#define mmDC_I2C_DDC4_SPEED …
#define mmDC_I2C_DDC4_SETUP …
#define mmDC_I2C_DDC5_SPEED …
#define mmDC_I2C_DDC5_SETUP …
#define mmDC_I2C_DDC6_SPEED …
#define mmDC_I2C_DDC6_SETUP …
#define mmDC_I2C_TRANSACTION0 …
#define mmDC_I2C_TRANSACTION1 …
#define mmDC_I2C_TRANSACTION2 …
#define mmDC_I2C_TRANSACTION3 …
#define mmDC_I2C_DATA …
#define mmGENERIC_I2C_CONTROL …
#define mmGENERIC_I2C_INTERRUPT_CONTROL …
#define mmGENERIC_I2C_STATUS …
#define mmGENERIC_I2C_SPEED …
#define mmGENERIC_I2C_SETUP …
#define mmGENERIC_I2C_TRANSACTION …
#define mmGENERIC_I2C_DATA …
#define mmGENERIC_I2C_PIN_SELECTION …
#define mmGENERIC_I2C_PIN_DEBUG …
#define mmDISP_INTERRUPT_STATUS …
#define mmDISP_INTERRUPT_STATUS_CONTINUE …
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 …
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 …
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 …
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 …
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 …
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 …
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 …
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 …
#define mmDOUT_POWER_MANAGEMENT_CNTL …
#define mmDISP_TIMER_CONTROL …
#define mmDC_I2C_DDCVGA_HW_STATUS …
#define mmDC_I2C_DDCVGA_SPEED …
#define mmDC_I2C_DDCVGA_SETUP …
#define mmDC_I2C_EDID_DETECT_CTRL …
#define mmDISPOUT_STEREOSYNC_SEL …
#define mmDOUT_TEST_DEBUG_INDEX …
#define mmDOUT_TEST_DEBUG_DATA …
#define ixDP_AUX1_DEBUG_A …
#define ixDP_AUX1_DEBUG_B …
#define ixDP_AUX1_DEBUG_C …
#define ixDP_AUX1_DEBUG_D …
#define ixDP_AUX1_DEBUG_E …
#define ixDP_AUX1_DEBUG_F …
#define ixDP_AUX1_DEBUG_G …
#define ixDP_AUX1_DEBUG_H …
#define ixDP_AUX1_DEBUG_I …
#define ixDP_AUX1_DEBUG_J …
#define ixDP_AUX1_DEBUG_K …
#define ixDP_AUX1_DEBUG_L …
#define ixDP_AUX1_DEBUG_M …
#define ixDP_AUX1_DEBUG_N …
#define ixDP_AUX1_DEBUG_O …
#define ixDP_AUX1_DEBUG_P …
#define ixDP_AUX1_DEBUG_Q …
#define ixDP_AUX2_DEBUG_A …
#define ixDP_AUX2_DEBUG_B …
#define ixDP_AUX2_DEBUG_C …
#define ixDP_AUX2_DEBUG_D …
#define ixDP_AUX2_DEBUG_E …
#define ixDP_AUX2_DEBUG_F …
#define ixDP_AUX2_DEBUG_G …
#define ixDP_AUX2_DEBUG_H …
#define ixDP_AUX2_DEBUG_I …
#define ixDP_AUX2_DEBUG_J …
#define ixDP_AUX2_DEBUG_K …
#define ixDP_AUX2_DEBUG_L …
#define ixDP_AUX2_DEBUG_M …
#define ixDP_AUX2_DEBUG_N …
#define ixDP_AUX2_DEBUG_O …
#define ixDP_AUX2_DEBUG_P …
#define ixDP_AUX2_DEBUG_Q …
#define ixDP_AUX3_DEBUG_A …
#define ixDP_AUX3_DEBUG_B …
#define ixDP_AUX3_DEBUG_C …
#define ixDP_AUX3_DEBUG_D …
#define ixDP_AUX3_DEBUG_E …
#define ixDP_AUX3_DEBUG_F …
#define ixDP_AUX3_DEBUG_G …
#define ixDP_AUX3_DEBUG_H …
#define ixDP_AUX3_DEBUG_I …
#define ixDP_AUX3_DEBUG_J …
#define ixDP_AUX3_DEBUG_K …
#define ixDP_AUX3_DEBUG_L …
#define ixDP_AUX3_DEBUG_M …
#define ixDP_AUX3_DEBUG_N …
#define ixDP_AUX3_DEBUG_O …
#define ixDP_AUX3_DEBUG_P …
#define ixDP_AUX3_DEBUG_Q …
#define ixDP_AUX4_DEBUG_A …
#define ixDP_AUX4_DEBUG_B …
#define ixDP_AUX4_DEBUG_C …
#define ixDP_AUX4_DEBUG_D …
#define ixDP_AUX4_DEBUG_E …
#define ixDP_AUX4_DEBUG_F …
#define ixDP_AUX4_DEBUG_G …
#define ixDP_AUX4_DEBUG_H …
#define ixDP_AUX4_DEBUG_I …
#define ixDP_AUX4_DEBUG_J …
#define ixDP_AUX4_DEBUG_K …
#define ixDP_AUX4_DEBUG_L …
#define ixDP_AUX4_DEBUG_M …
#define ixDP_AUX4_DEBUG_N …
#define ixDP_AUX4_DEBUG_O …
#define ixDP_AUX4_DEBUG_P …
#define ixDP_AUX4_DEBUG_Q …
#define ixDP_AUX5_DEBUG_A …
#define ixDP_AUX5_DEBUG_B …
#define ixDP_AUX5_DEBUG_C …
#define ixDP_AUX5_DEBUG_D …
#define ixDP_AUX5_DEBUG_E …
#define ixDP_AUX5_DEBUG_F …
#define ixDP_AUX5_DEBUG_G …
#define ixDP_AUX5_DEBUG_H …
#define ixDP_AUX5_DEBUG_I …
#define ixDP_AUX5_DEBUG_J …
#define ixDP_AUX5_DEBUG_K …
#define ixDP_AUX5_DEBUG_L …
#define ixDP_AUX5_DEBUG_M …
#define ixDP_AUX5_DEBUG_N …
#define ixDP_AUX5_DEBUG_O …
#define ixDP_AUX5_DEBUG_P …
#define ixDP_AUX5_DEBUG_Q …
#define ixDP_AUX6_DEBUG_A …
#define ixDP_AUX6_DEBUG_B …
#define ixDP_AUX6_DEBUG_C …
#define ixDP_AUX6_DEBUG_D …
#define ixDP_AUX6_DEBUG_E …
#define ixDP_AUX6_DEBUG_F …
#define ixDP_AUX6_DEBUG_G …
#define ixDP_AUX6_DEBUG_H …
#define ixDP_AUX6_DEBUG_I …
#define ixDP_AUX6_DEBUG_J …
#define ixDP_AUX6_DEBUG_K …
#define ixDP_AUX6_DEBUG_L …
#define ixDP_AUX6_DEBUG_M …
#define ixDP_AUX6_DEBUG_N …
#define ixDP_AUX6_DEBUG_O …
#define ixDP_AUX6_DEBUG_P …
#define ixDP_AUX6_DEBUG_Q …
#define mmDMCU_CTRL …
#define mmDMCU_STATUS …
#define mmDMCU_PC_START_ADDR …
#define mmDMCU_FW_START_ADDR …
#define mmDMCU_FW_END_ADDR …
#define mmDMCU_FW_ISR_START_ADDR …
#define mmDMCU_FW_CS_HI …
#define mmDMCU_FW_CS_LO …
#define mmDMCU_RAM_ACCESS_CTRL …
#define mmDMCU_ERAM_WR_CTRL …
#define mmDMCU_ERAM_WR_DATA …
#define mmDMCU_ERAM_RD_CTRL …
#define mmDMCU_ERAM_RD_DATA …
#define mmDMCU_IRAM_WR_CTRL …
#define mmDMCU_IRAM_WR_DATA …
#define mmDMCU_IRAM_RD_CTRL …
#define mmDMCU_IRAM_RD_DATA …
#define mmDMCU_EVENT_TRIGGER …
#define mmDMCU_UC_INTERNAL_INT_STATUS …
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS …
#define mmDMCU_INTERRUPT_STATUS …
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK …
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK …
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL …
#define mmDC_DMCU_SCRATCH …
#define mmDMCU_INT_CNT …
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS …
#define mmDMCU_UC_CLK_GATING_CNTL …
#define mmMASTER_COMM_DATA_REG1 …
#define mmMASTER_COMM_DATA_REG2 …
#define mmMASTER_COMM_DATA_REG3 …
#define mmMASTER_COMM_CMD_REG …
#define mmMASTER_COMM_CNTL_REG …
#define mmSLAVE_COMM_DATA_REG1 …
#define mmSLAVE_COMM_DATA_REG2 …
#define mmSLAVE_COMM_DATA_REG3 …
#define mmSLAVE_COMM_CMD_REG …
#define mmSLAVE_COMM_CNTL_REG …
#define mmDMCU_TEST_DEBUG_INDEX …
#define mmDMCU_TEST_DEBUG_DATA …
#define mmDMCU_PERFMON_INTERRUPT_STATUS1 …
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 …
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 …
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 …
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 …
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 …
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 …
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 …
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 …
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 …
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 …
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 …
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 …
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 …
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 …
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 …
#define mmDP_LINK_CNTL …
#define mmDP0_DP_LINK_CNTL …
#define mmDP1_DP_LINK_CNTL …
#define mmDP2_DP_LINK_CNTL …
#define mmDP3_DP_LINK_CNTL …
#define mmDP4_DP_LINK_CNTL …
#define mmDP5_DP_LINK_CNTL …
#define mmDP6_DP_LINK_CNTL …
#define mmDP_PIXEL_FORMAT …
#define mmDP0_DP_PIXEL_FORMAT …
#define mmDP1_DP_PIXEL_FORMAT …
#define mmDP2_DP_PIXEL_FORMAT …
#define mmDP3_DP_PIXEL_FORMAT …
#define mmDP4_DP_PIXEL_FORMAT …
#define mmDP5_DP_PIXEL_FORMAT …
#define mmDP6_DP_PIXEL_FORMAT …
#define mmDP_MSA_COLORIMETRY …
#define mmDP0_DP_MSA_COLORIMETRY …
#define mmDP1_DP_MSA_COLORIMETRY …
#define mmDP2_DP_MSA_COLORIMETRY …
#define mmDP3_DP_MSA_COLORIMETRY …
#define mmDP4_DP_MSA_COLORIMETRY …
#define mmDP5_DP_MSA_COLORIMETRY …
#define mmDP6_DP_MSA_COLORIMETRY …
#define mmDP_CONFIG …
#define mmDP0_DP_CONFIG …
#define mmDP1_DP_CONFIG …
#define mmDP2_DP_CONFIG …
#define mmDP3_DP_CONFIG …
#define mmDP4_DP_CONFIG …
#define mmDP5_DP_CONFIG …
#define mmDP6_DP_CONFIG …
#define mmDP_VID_STREAM_CNTL …
#define mmDP0_DP_VID_STREAM_CNTL …
#define mmDP1_DP_VID_STREAM_CNTL …
#define mmDP2_DP_VID_STREAM_CNTL …
#define mmDP3_DP_VID_STREAM_CNTL …
#define mmDP4_DP_VID_STREAM_CNTL …
#define mmDP5_DP_VID_STREAM_CNTL …
#define mmDP6_DP_VID_STREAM_CNTL …
#define mmDP_STEER_FIFO …
#define mmDP0_DP_STEER_FIFO …
#define mmDP1_DP_STEER_FIFO …
#define mmDP2_DP_STEER_FIFO …
#define mmDP3_DP_STEER_FIFO …
#define mmDP4_DP_STEER_FIFO …
#define mmDP5_DP_STEER_FIFO …
#define mmDP6_DP_STEER_FIFO …
#define mmDP_MSA_MISC …
#define mmDP0_DP_MSA_MISC …
#define mmDP1_DP_MSA_MISC …
#define mmDP2_DP_MSA_MISC …
#define mmDP3_DP_MSA_MISC …
#define mmDP4_DP_MSA_MISC …
#define mmDP5_DP_MSA_MISC …
#define mmDP6_DP_MSA_MISC …
#define mmDP_VID_TIMING …
#define mmDP0_DP_VID_TIMING …
#define mmDP1_DP_VID_TIMING …
#define mmDP2_DP_VID_TIMING …
#define mmDP3_DP_VID_TIMING …
#define mmDP4_DP_VID_TIMING …
#define mmDP5_DP_VID_TIMING …
#define mmDP6_DP_VID_TIMING …
#define mmDP_VID_N …
#define mmDP0_DP_VID_N …
#define mmDP1_DP_VID_N …
#define mmDP2_DP_VID_N …
#define mmDP3_DP_VID_N …
#define mmDP4_DP_VID_N …
#define mmDP5_DP_VID_N …
#define mmDP6_DP_VID_N …
#define mmDP_VID_M …
#define mmDP0_DP_VID_M …
#define mmDP1_DP_VID_M …
#define mmDP2_DP_VID_M …
#define mmDP3_DP_VID_M …
#define mmDP4_DP_VID_M …
#define mmDP5_DP_VID_M …
#define mmDP6_DP_VID_M …
#define mmDP_LINK_FRAMING_CNTL …
#define mmDP0_DP_LINK_FRAMING_CNTL …
#define mmDP1_DP_LINK_FRAMING_CNTL …
#define mmDP2_DP_LINK_FRAMING_CNTL …
#define mmDP3_DP_LINK_FRAMING_CNTL …
#define mmDP4_DP_LINK_FRAMING_CNTL …
#define mmDP5_DP_LINK_FRAMING_CNTL …
#define mmDP6_DP_LINK_FRAMING_CNTL …
#define mmDP_HBR2_EYE_PATTERN …
#define mmDP0_DP_HBR2_EYE_PATTERN …
#define mmDP1_DP_HBR2_EYE_PATTERN …
#define mmDP2_DP_HBR2_EYE_PATTERN …
#define mmDP3_DP_HBR2_EYE_PATTERN …
#define mmDP4_DP_HBR2_EYE_PATTERN …
#define mmDP5_DP_HBR2_EYE_PATTERN …
#define mmDP6_DP_HBR2_EYE_PATTERN …
#define mmDP_VID_MSA_VBID …
#define mmDP0_DP_VID_MSA_VBID …
#define mmDP1_DP_VID_MSA_VBID …
#define mmDP2_DP_VID_MSA_VBID …
#define mmDP3_DP_VID_MSA_VBID …
#define mmDP4_DP_VID_MSA_VBID …
#define mmDP5_DP_VID_MSA_VBID …
#define mmDP6_DP_VID_MSA_VBID …
#define mmDP_VID_INTERRUPT_CNTL …
#define mmDP0_DP_VID_INTERRUPT_CNTL …
#define mmDP1_DP_VID_INTERRUPT_CNTL …
#define mmDP2_DP_VID_INTERRUPT_CNTL …
#define mmDP3_DP_VID_INTERRUPT_CNTL …
#define mmDP4_DP_VID_INTERRUPT_CNTL …
#define mmDP5_DP_VID_INTERRUPT_CNTL …
#define mmDP6_DP_VID_INTERRUPT_CNTL …
#define mmDP_DPHY_CNTL …
#define mmDP0_DP_DPHY_CNTL …
#define mmDP1_DP_DPHY_CNTL …
#define mmDP2_DP_DPHY_CNTL …
#define mmDP3_DP_DPHY_CNTL …
#define mmDP4_DP_DPHY_CNTL …
#define mmDP5_DP_DPHY_CNTL …
#define mmDP6_DP_DPHY_CNTL …
#define mmDP_DPHY_TRAINING_PATTERN_SEL …
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL …
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL …
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL …
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL …
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL …
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL …
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL …
#define mmDP_DPHY_SYM0 …
#define mmDP0_DP_DPHY_SYM0 …
#define mmDP1_DP_DPHY_SYM0 …
#define mmDP2_DP_DPHY_SYM0 …
#define mmDP3_DP_DPHY_SYM0 …
#define mmDP4_DP_DPHY_SYM0 …
#define mmDP5_DP_DPHY_SYM0 …
#define mmDP6_DP_DPHY_SYM0 …
#define mmDP_DPHY_SYM1 …
#define mmDP0_DP_DPHY_SYM1 …
#define mmDP1_DP_DPHY_SYM1 …
#define mmDP2_DP_DPHY_SYM1 …
#define mmDP3_DP_DPHY_SYM1 …
#define mmDP4_DP_DPHY_SYM1 …
#define mmDP5_DP_DPHY_SYM1 …
#define mmDP6_DP_DPHY_SYM1 …
#define mmDP_DPHY_SYM2 …
#define mmDP0_DP_DPHY_SYM2 …
#define mmDP1_DP_DPHY_SYM2 …
#define mmDP2_DP_DPHY_SYM2 …
#define mmDP3_DP_DPHY_SYM2 …
#define mmDP4_DP_DPHY_SYM2 …
#define mmDP5_DP_DPHY_SYM2 …
#define mmDP6_DP_DPHY_SYM2 …
#define mmDP_DPHY_8B10B_CNTL …
#define mmDP0_DP_DPHY_8B10B_CNTL …
#define mmDP1_DP_DPHY_8B10B_CNTL …
#define mmDP2_DP_DPHY_8B10B_CNTL …
#define mmDP3_DP_DPHY_8B10B_CNTL …
#define mmDP4_DP_DPHY_8B10B_CNTL …
#define mmDP5_DP_DPHY_8B10B_CNTL …
#define mmDP6_DP_DPHY_8B10B_CNTL …
#define mmDP_DPHY_PRBS_CNTL …
#define mmDP0_DP_DPHY_PRBS_CNTL …
#define mmDP1_DP_DPHY_PRBS_CNTL …
#define mmDP2_DP_DPHY_PRBS_CNTL …
#define mmDP3_DP_DPHY_PRBS_CNTL …
#define mmDP4_DP_DPHY_PRBS_CNTL …
#define mmDP5_DP_DPHY_PRBS_CNTL …
#define mmDP6_DP_DPHY_PRBS_CNTL …
#define mmDP_DPHY_SCRAM_CNTL …
#define mmDP0_DP_DPHY_SCRAM_CNTL …
#define mmDP1_DP_DPHY_SCRAM_CNTL …
#define mmDP2_DP_DPHY_SCRAM_CNTL …
#define mmDP3_DP_DPHY_SCRAM_CNTL …
#define mmDP4_DP_DPHY_SCRAM_CNTL …
#define mmDP5_DP_DPHY_SCRAM_CNTL …
#define mmDP6_DP_DPHY_SCRAM_CNTL …
#define mmDP_DPHY_CRC_EN …
#define mmDP0_DP_DPHY_CRC_EN …
#define mmDP1_DP_DPHY_CRC_EN …
#define mmDP2_DP_DPHY_CRC_EN …
#define mmDP3_DP_DPHY_CRC_EN …
#define mmDP4_DP_DPHY_CRC_EN …
#define mmDP5_DP_DPHY_CRC_EN …
#define mmDP6_DP_DPHY_CRC_EN …
#define mmDP_DPHY_CRC_CNTL …
#define mmDP0_DP_DPHY_CRC_CNTL …
#define mmDP1_DP_DPHY_CRC_CNTL …
#define mmDP2_DP_DPHY_CRC_CNTL …
#define mmDP3_DP_DPHY_CRC_CNTL …
#define mmDP4_DP_DPHY_CRC_CNTL …
#define mmDP5_DP_DPHY_CRC_CNTL …
#define mmDP6_DP_DPHY_CRC_CNTL …
#define mmDP_DPHY_CRC_RESULT …
#define mmDP0_DP_DPHY_CRC_RESULT …
#define mmDP1_DP_DPHY_CRC_RESULT …
#define mmDP2_DP_DPHY_CRC_RESULT …
#define mmDP3_DP_DPHY_CRC_RESULT …
#define mmDP4_DP_DPHY_CRC_RESULT …
#define mmDP5_DP_DPHY_CRC_RESULT …
#define mmDP6_DP_DPHY_CRC_RESULT …
#define mmDP_DPHY_CRC_MST_CNTL …
#define mmDP0_DP_DPHY_CRC_MST_CNTL …
#define mmDP1_DP_DPHY_CRC_MST_CNTL …
#define mmDP2_DP_DPHY_CRC_MST_CNTL …
#define mmDP3_DP_DPHY_CRC_MST_CNTL …
#define mmDP4_DP_DPHY_CRC_MST_CNTL …
#define mmDP5_DP_DPHY_CRC_MST_CNTL …
#define mmDP6_DP_DPHY_CRC_MST_CNTL …
#define mmDP_DPHY_CRC_MST_STATUS …
#define mmDP0_DP_DPHY_CRC_MST_STATUS …
#define mmDP1_DP_DPHY_CRC_MST_STATUS …
#define mmDP2_DP_DPHY_CRC_MST_STATUS …
#define mmDP3_DP_DPHY_CRC_MST_STATUS …
#define mmDP4_DP_DPHY_CRC_MST_STATUS …
#define mmDP5_DP_DPHY_CRC_MST_STATUS …
#define mmDP6_DP_DPHY_CRC_MST_STATUS …
#define mmDP_DPHY_FAST_TRAINING …
#define mmDP0_DP_DPHY_FAST_TRAINING …
#define mmDP1_DP_DPHY_FAST_TRAINING …
#define mmDP2_DP_DPHY_FAST_TRAINING …
#define mmDP3_DP_DPHY_FAST_TRAINING …
#define mmDP4_DP_DPHY_FAST_TRAINING …
#define mmDP5_DP_DPHY_FAST_TRAINING …
#define mmDP6_DP_DPHY_FAST_TRAINING …
#define mmDP_DPHY_FAST_TRAINING_STATUS …
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS …
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS …
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS …
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS …
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS …
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS …
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS …
#define mmDP_MSA_V_TIMING_OVERRIDE1 …
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 …
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 …
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 …
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 …
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 …
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 …
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 …
#define mmDP_MSA_V_TIMING_OVERRIDE2 …
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 …
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 …
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 …
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 …
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 …
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 …
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 …
#define mmDP_SEC_CNTL …
#define mmDP0_DP_SEC_CNTL …
#define mmDP1_DP_SEC_CNTL …
#define mmDP2_DP_SEC_CNTL …
#define mmDP3_DP_SEC_CNTL …
#define mmDP4_DP_SEC_CNTL …
#define mmDP5_DP_SEC_CNTL …
#define mmDP6_DP_SEC_CNTL …
#define mmDP_SEC_CNTL1 …
#define mmDP0_DP_SEC_CNTL1 …
#define mmDP1_DP_SEC_CNTL1 …
#define mmDP2_DP_SEC_CNTL1 …
#define mmDP3_DP_SEC_CNTL1 …
#define mmDP4_DP_SEC_CNTL1 …
#define mmDP5_DP_SEC_CNTL1 …
#define mmDP6_DP_SEC_CNTL1 …
#define mmDP_SEC_FRAMING1 …
#define mmDP0_DP_SEC_FRAMING1 …
#define mmDP1_DP_SEC_FRAMING1 …
#define mmDP2_DP_SEC_FRAMING1 …
#define mmDP3_DP_SEC_FRAMING1 …
#define mmDP4_DP_SEC_FRAMING1 …
#define mmDP5_DP_SEC_FRAMING1 …
#define mmDP6_DP_SEC_FRAMING1 …
#define mmDP_SEC_FRAMING2 …
#define mmDP0_DP_SEC_FRAMING2 …
#define mmDP1_DP_SEC_FRAMING2 …
#define mmDP2_DP_SEC_FRAMING2 …
#define mmDP3_DP_SEC_FRAMING2 …
#define mmDP4_DP_SEC_FRAMING2 …
#define mmDP5_DP_SEC_FRAMING2 …
#define mmDP6_DP_SEC_FRAMING2 …
#define mmDP_SEC_FRAMING3 …
#define mmDP0_DP_SEC_FRAMING3 …
#define mmDP1_DP_SEC_FRAMING3 …
#define mmDP2_DP_SEC_FRAMING3 …
#define mmDP3_DP_SEC_FRAMING3 …
#define mmDP4_DP_SEC_FRAMING3 …
#define mmDP5_DP_SEC_FRAMING3 …
#define mmDP6_DP_SEC_FRAMING3 …
#define mmDP_SEC_FRAMING4 …
#define mmDP0_DP_SEC_FRAMING4 …
#define mmDP1_DP_SEC_FRAMING4 …
#define mmDP2_DP_SEC_FRAMING4 …
#define mmDP3_DP_SEC_FRAMING4 …
#define mmDP4_DP_SEC_FRAMING4 …
#define mmDP5_DP_SEC_FRAMING4 …
#define mmDP6_DP_SEC_FRAMING4 …
#define mmDP_SEC_AUD_N …
#define mmDP0_DP_SEC_AUD_N …
#define mmDP1_DP_SEC_AUD_N …
#define mmDP2_DP_SEC_AUD_N …
#define mmDP3_DP_SEC_AUD_N …
#define mmDP4_DP_SEC_AUD_N …
#define mmDP5_DP_SEC_AUD_N …
#define mmDP6_DP_SEC_AUD_N …
#define mmDP_SEC_AUD_N_READBACK …
#define mmDP0_DP_SEC_AUD_N_READBACK …
#define mmDP1_DP_SEC_AUD_N_READBACK …
#define mmDP2_DP_SEC_AUD_N_READBACK …
#define mmDP3_DP_SEC_AUD_N_READBACK …
#define mmDP4_DP_SEC_AUD_N_READBACK …
#define mmDP5_DP_SEC_AUD_N_READBACK …
#define mmDP6_DP_SEC_AUD_N_READBACK …
#define mmDP_SEC_AUD_M …
#define mmDP0_DP_SEC_AUD_M …
#define mmDP1_DP_SEC_AUD_M …
#define mmDP2_DP_SEC_AUD_M …
#define mmDP3_DP_SEC_AUD_M …
#define mmDP4_DP_SEC_AUD_M …
#define mmDP5_DP_SEC_AUD_M …
#define mmDP6_DP_SEC_AUD_M …
#define mmDP_SEC_AUD_M_READBACK …
#define mmDP0_DP_SEC_AUD_M_READBACK …
#define mmDP1_DP_SEC_AUD_M_READBACK …
#define mmDP2_DP_SEC_AUD_M_READBACK …
#define mmDP3_DP_SEC_AUD_M_READBACK …
#define mmDP4_DP_SEC_AUD_M_READBACK …
#define mmDP5_DP_SEC_AUD_M_READBACK …
#define mmDP6_DP_SEC_AUD_M_READBACK …
#define mmDP_SEC_TIMESTAMP …
#define mmDP0_DP_SEC_TIMESTAMP …
#define mmDP1_DP_SEC_TIMESTAMP …
#define mmDP2_DP_SEC_TIMESTAMP …
#define mmDP3_DP_SEC_TIMESTAMP …
#define mmDP4_DP_SEC_TIMESTAMP …
#define mmDP5_DP_SEC_TIMESTAMP …
#define mmDP6_DP_SEC_TIMESTAMP …
#define mmDP_SEC_PACKET_CNTL …
#define mmDP0_DP_SEC_PACKET_CNTL …
#define mmDP1_DP_SEC_PACKET_CNTL …
#define mmDP2_DP_SEC_PACKET_CNTL …
#define mmDP3_DP_SEC_PACKET_CNTL …
#define mmDP4_DP_SEC_PACKET_CNTL …
#define mmDP5_DP_SEC_PACKET_CNTL …
#define mmDP6_DP_SEC_PACKET_CNTL …
#define mmDP_MSE_RATE_CNTL …
#define mmDP0_DP_MSE_RATE_CNTL …
#define mmDP1_DP_MSE_RATE_CNTL …
#define mmDP2_DP_MSE_RATE_CNTL …
#define mmDP3_DP_MSE_RATE_CNTL …
#define mmDP4_DP_MSE_RATE_CNTL …
#define mmDP5_DP_MSE_RATE_CNTL …
#define mmDP6_DP_MSE_RATE_CNTL …
#define mmDP_MSE_RATE_UPDATE …
#define mmDP0_DP_MSE_RATE_UPDATE …
#define mmDP1_DP_MSE_RATE_UPDATE …
#define mmDP2_DP_MSE_RATE_UPDATE …
#define mmDP3_DP_MSE_RATE_UPDATE …
#define mmDP4_DP_MSE_RATE_UPDATE …
#define mmDP5_DP_MSE_RATE_UPDATE …
#define mmDP6_DP_MSE_RATE_UPDATE …
#define mmDP_MSE_SAT0 …
#define mmDP0_DP_MSE_SAT0 …
#define mmDP1_DP_MSE_SAT0 …
#define mmDP2_DP_MSE_SAT0 …
#define mmDP3_DP_MSE_SAT0 …
#define mmDP4_DP_MSE_SAT0 …
#define mmDP5_DP_MSE_SAT0 …
#define mmDP6_DP_MSE_SAT0 …
#define mmDP_MSE_SAT1 …
#define mmDP0_DP_MSE_SAT1 …
#define mmDP1_DP_MSE_SAT1 …
#define mmDP2_DP_MSE_SAT1 …
#define mmDP3_DP_MSE_SAT1 …
#define mmDP4_DP_MSE_SAT1 …
#define mmDP5_DP_MSE_SAT1 …
#define mmDP6_DP_MSE_SAT1 …
#define mmDP_MSE_SAT2 …
#define mmDP0_DP_MSE_SAT2 …
#define mmDP1_DP_MSE_SAT2 …
#define mmDP2_DP_MSE_SAT2 …
#define mmDP3_DP_MSE_SAT2 …
#define mmDP4_DP_MSE_SAT2 …
#define mmDP5_DP_MSE_SAT2 …
#define mmDP6_DP_MSE_SAT2 …
#define mmDP_MSE_SAT_UPDATE …
#define mmDP0_DP_MSE_SAT_UPDATE …
#define mmDP1_DP_MSE_SAT_UPDATE …
#define mmDP2_DP_MSE_SAT_UPDATE …
#define mmDP3_DP_MSE_SAT_UPDATE …
#define mmDP4_DP_MSE_SAT_UPDATE …
#define mmDP5_DP_MSE_SAT_UPDATE …
#define mmDP6_DP_MSE_SAT_UPDATE …
#define mmDP_MSE_LINK_TIMING …
#define mmDP0_DP_MSE_LINK_TIMING …
#define mmDP1_DP_MSE_LINK_TIMING …
#define mmDP2_DP_MSE_LINK_TIMING …
#define mmDP3_DP_MSE_LINK_TIMING …
#define mmDP4_DP_MSE_LINK_TIMING …
#define mmDP5_DP_MSE_LINK_TIMING …
#define mmDP6_DP_MSE_LINK_TIMING …
#define mmDP_MSE_MISC_CNTL …
#define mmDP0_DP_MSE_MISC_CNTL …
#define mmDP1_DP_MSE_MISC_CNTL …
#define mmDP2_DP_MSE_MISC_CNTL …
#define mmDP3_DP_MSE_MISC_CNTL …
#define mmDP4_DP_MSE_MISC_CNTL …
#define mmDP5_DP_MSE_MISC_CNTL …
#define mmDP6_DP_MSE_MISC_CNTL …
#define mmDP_TEST_DEBUG_INDEX …
#define mmDP0_DP_TEST_DEBUG_INDEX …
#define mmDP1_DP_TEST_DEBUG_INDEX …
#define mmDP2_DP_TEST_DEBUG_INDEX …
#define mmDP3_DP_TEST_DEBUG_INDEX …
#define mmDP4_DP_TEST_DEBUG_INDEX …
#define mmDP5_DP_TEST_DEBUG_INDEX …
#define mmDP6_DP_TEST_DEBUG_INDEX …
#define mmDP_TEST_DEBUG_DATA …
#define mmDP0_DP_TEST_DEBUG_DATA …
#define mmDP1_DP_TEST_DEBUG_DATA …
#define mmDP2_DP_TEST_DEBUG_DATA …
#define mmDP3_DP_TEST_DEBUG_DATA …
#define mmDP4_DP_TEST_DEBUG_DATA …
#define mmDP5_DP_TEST_DEBUG_DATA …
#define mmDP6_DP_TEST_DEBUG_DATA …
#define mmAUX_CONTROL …
#define mmDP_AUX0_AUX_CONTROL …
#define mmDP_AUX1_AUX_CONTROL …
#define mmDP_AUX2_AUX_CONTROL …
#define mmDP_AUX3_AUX_CONTROL …
#define mmDP_AUX4_AUX_CONTROL …
#define mmDP_AUX5_AUX_CONTROL …
#define mmAUX_SW_CONTROL …
#define mmDP_AUX0_AUX_SW_CONTROL …
#define mmDP_AUX1_AUX_SW_CONTROL …
#define mmDP_AUX2_AUX_SW_CONTROL …
#define mmDP_AUX3_AUX_SW_CONTROL …
#define mmDP_AUX4_AUX_SW_CONTROL …
#define mmDP_AUX5_AUX_SW_CONTROL …
#define mmAUX_ARB_CONTROL …
#define mmDP_AUX0_AUX_ARB_CONTROL …
#define mmDP_AUX1_AUX_ARB_CONTROL …
#define mmDP_AUX2_AUX_ARB_CONTROL …
#define mmDP_AUX3_AUX_ARB_CONTROL …
#define mmDP_AUX4_AUX_ARB_CONTROL …
#define mmDP_AUX5_AUX_ARB_CONTROL …
#define mmAUX_INTERRUPT_CONTROL …
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL …
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL …
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL …
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL …
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL …
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL …
#define mmAUX_SW_STATUS …
#define mmDP_AUX0_AUX_SW_STATUS …
#define mmDP_AUX1_AUX_SW_STATUS …
#define mmDP_AUX2_AUX_SW_STATUS …
#define mmDP_AUX3_AUX_SW_STATUS …
#define mmDP_AUX4_AUX_SW_STATUS …
#define mmDP_AUX5_AUX_SW_STATUS …
#define mmAUX_LS_STATUS …
#define mmDP_AUX0_AUX_LS_STATUS …
#define mmDP_AUX1_AUX_LS_STATUS …
#define mmDP_AUX2_AUX_LS_STATUS …
#define mmDP_AUX3_AUX_LS_STATUS …
#define mmDP_AUX4_AUX_LS_STATUS …
#define mmDP_AUX5_AUX_LS_STATUS …
#define mmAUX_SW_DATA …
#define mmDP_AUX0_AUX_SW_DATA …
#define mmDP_AUX1_AUX_SW_DATA …
#define mmDP_AUX2_AUX_SW_DATA …
#define mmDP_AUX3_AUX_SW_DATA …
#define mmDP_AUX4_AUX_SW_DATA …
#define mmDP_AUX5_AUX_SW_DATA …
#define mmAUX_LS_DATA …
#define mmDP_AUX0_AUX_LS_DATA …
#define mmDP_AUX1_AUX_LS_DATA …
#define mmDP_AUX2_AUX_LS_DATA …
#define mmDP_AUX3_AUX_LS_DATA …
#define mmDP_AUX4_AUX_LS_DATA …
#define mmDP_AUX5_AUX_LS_DATA …
#define mmAUX_DPHY_TX_REF_CONTROL …
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL …
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL …
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL …
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL …
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL …
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL …
#define mmAUX_DPHY_TX_CONTROL …
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL …
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL …
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL …
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL …
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL …
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL …
#define mmAUX_DPHY_RX_CONTROL0 …
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 …
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 …
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 …
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 …
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 …
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 …
#define mmAUX_DPHY_RX_CONTROL1 …
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 …
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 …
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 …
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 …
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 …
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 …
#define mmAUX_DPHY_TX_STATUS …
#define mmDP_AUX0_AUX_DPHY_TX_STATUS …
#define mmDP_AUX1_AUX_DPHY_TX_STATUS …
#define mmDP_AUX2_AUX_DPHY_TX_STATUS …
#define mmDP_AUX3_AUX_DPHY_TX_STATUS …
#define mmDP_AUX4_AUX_DPHY_TX_STATUS …
#define mmDP_AUX5_AUX_DPHY_TX_STATUS …
#define mmAUX_DPHY_RX_STATUS …
#define mmDP_AUX0_AUX_DPHY_RX_STATUS …
#define mmDP_AUX1_AUX_DPHY_RX_STATUS …
#define mmDP_AUX2_AUX_DPHY_RX_STATUS …
#define mmDP_AUX3_AUX_DPHY_RX_STATUS …
#define mmDP_AUX4_AUX_DPHY_RX_STATUS …
#define mmDP_AUX5_AUX_DPHY_RX_STATUS …
#define mmAUX_GTC_SYNC_CONTROL …
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL …
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL …
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL …
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL …
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL …
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL …
#define mmAUX_GTC_SYNC_ERROR_CONTROL …
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL …
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL …
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL …
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL …
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL …
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL …
#define mmAUX_GTC_SYNC_CONTROLLER_STATUS …
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS …
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS …
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS …
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS …
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS …
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS …
#define mmAUX_GTC_SYNC_STATUS …
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS …
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS …
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS …
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS …
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS …
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS …
#define mmAUX_GTC_SYNC_DATA …
#define mmDP_AUX0_AUX_GTC_SYNC_DATA …
#define mmDP_AUX1_AUX_GTC_SYNC_DATA …
#define mmDP_AUX2_AUX_GTC_SYNC_DATA …
#define mmDP_AUX3_AUX_GTC_SYNC_DATA …
#define mmDP_AUX4_AUX_GTC_SYNC_DATA …
#define mmDP_AUX5_AUX_GTC_SYNC_DATA …
#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE …
#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE …
#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE …
#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE …
#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE …
#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE …
#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE …
#define mmDVO_ENABLE …
#define mmDVO_SOURCE_SELECT …
#define mmDVO_OUTPUT …
#define mmDVO_CONTROL …
#define mmDVO_CRC_EN …
#define mmDVO_CRC2_SIG_MASK …
#define mmDVO_CRC2_SIG_RESULT …
#define mmDVO_FIFO_ERROR_STATUS …
#define mmFBC_CNTL …
#define mmFBC_IDLE_MASK …
#define mmFBC_IDLE_FORCE_CLEAR_MASK …
#define mmFBC_START_STOP_DELAY …
#define mmFBC_COMP_CNTL …
#define mmFBC_COMP_MODE …
#define mmFBC_DEBUG0 …
#define mmFBC_DEBUG1 …
#define mmFBC_DEBUG2 …
#define mmFBC_IND_LUT0 …
#define mmFBC_IND_LUT1 …
#define mmFBC_IND_LUT2 …
#define mmFBC_IND_LUT3 …
#define mmFBC_IND_LUT4 …
#define mmFBC_IND_LUT5 …
#define mmFBC_IND_LUT6 …
#define mmFBC_IND_LUT7 …
#define mmFBC_IND_LUT8 …
#define mmFBC_IND_LUT9 …
#define mmFBC_IND_LUT10 …
#define mmFBC_IND_LUT11 …
#define mmFBC_IND_LUT12 …
#define mmFBC_IND_LUT13 …
#define mmFBC_IND_LUT14 …
#define mmFBC_IND_LUT15 …
#define mmFBC_CSM_REGION_OFFSET_01 …
#define mmFBC_CSM_REGION_OFFSET_23 …
#define mmFBC_CLIENT_REGION_MASK …
#define mmFBC_DEBUG_COMP …
#define mmFBC_DEBUG_CSR …
#define mmFBC_DEBUG_CSR_RDATA …
#define mmFBC_DEBUG_CSR_WDATA …
#define mmFBC_DEBUG_CSR_RDATA_HI …
#define mmFBC_DEBUG_CSR_WDATA_HI …
#define mmFBC_MISC …
#define mmFBC_STATUS …
#define mmFBC_TEST_DEBUG_INDEX …
#define mmFBC_TEST_DEBUG_DATA …
#define mmFMT_CLAMP_COMPONENT_R …
#define mmFMT0_FMT_CLAMP_COMPONENT_R …
#define mmFMT1_FMT_CLAMP_COMPONENT_R …
#define mmFMT2_FMT_CLAMP_COMPONENT_R …
#define mmFMT3_FMT_CLAMP_COMPONENT_R …
#define mmFMT4_FMT_CLAMP_COMPONENT_R …
#define mmFMT5_FMT_CLAMP_COMPONENT_R …
#define mmFMT_CLAMP_COMPONENT_G …
#define mmFMT0_FMT_CLAMP_COMPONENT_G …
#define mmFMT1_FMT_CLAMP_COMPONENT_G …
#define mmFMT2_FMT_CLAMP_COMPONENT_G …
#define mmFMT3_FMT_CLAMP_COMPONENT_G …
#define mmFMT4_FMT_CLAMP_COMPONENT_G …
#define mmFMT5_FMT_CLAMP_COMPONENT_G …
#define mmFMT_CLAMP_COMPONENT_B …
#define mmFMT0_FMT_CLAMP_COMPONENT_B …
#define mmFMT1_FMT_CLAMP_COMPONENT_B …
#define mmFMT2_FMT_CLAMP_COMPONENT_B …
#define mmFMT3_FMT_CLAMP_COMPONENT_B …
#define mmFMT4_FMT_CLAMP_COMPONENT_B …
#define mmFMT5_FMT_CLAMP_COMPONENT_B …
#define mmFMT_DYNAMIC_EXP_CNTL …
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL …
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL …
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL …
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL …
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL …
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL …
#define mmFMT_CONTROL …
#define mmFMT0_FMT_CONTROL …
#define mmFMT1_FMT_CONTROL …
#define mmFMT2_FMT_CONTROL …
#define mmFMT3_FMT_CONTROL …
#define mmFMT4_FMT_CONTROL …
#define mmFMT5_FMT_CONTROL …
#define mmFMT_FORCE_OUTPUT_CNTL …
#define mmFMT0_FMT_FORCE_OUTPUT_CNTL …
#define mmFMT1_FMT_FORCE_OUTPUT_CNTL …
#define mmFMT2_FMT_FORCE_OUTPUT_CNTL …
#define mmFMT3_FMT_FORCE_OUTPUT_CNTL …
#define mmFMT4_FMT_FORCE_OUTPUT_CNTL …
#define mmFMT5_FMT_FORCE_OUTPUT_CNTL …
#define mmFMT_FORCE_DATA_0_1 …
#define mmFMT0_FMT_FORCE_DATA_0_1 …
#define mmFMT1_FMT_FORCE_DATA_0_1 …
#define mmFMT2_FMT_FORCE_DATA_0_1 …
#define mmFMT3_FMT_FORCE_DATA_0_1 …
#define mmFMT4_FMT_FORCE_DATA_0_1 …
#define mmFMT5_FMT_FORCE_DATA_0_1 …
#define mmFMT_FORCE_DATA_2_3 …
#define mmFMT0_FMT_FORCE_DATA_2_3 …
#define mmFMT1_FMT_FORCE_DATA_2_3 …
#define mmFMT2_FMT_FORCE_DATA_2_3 …
#define mmFMT3_FMT_FORCE_DATA_2_3 …
#define mmFMT4_FMT_FORCE_DATA_2_3 …
#define mmFMT5_FMT_FORCE_DATA_2_3 …
#define mmFMT_BIT_DEPTH_CONTROL …
#define mmFMT0_FMT_BIT_DEPTH_CONTROL …
#define mmFMT1_FMT_BIT_DEPTH_CONTROL …
#define mmFMT2_FMT_BIT_DEPTH_CONTROL …
#define mmFMT3_FMT_BIT_DEPTH_CONTROL …
#define mmFMT4_FMT_BIT_DEPTH_CONTROL …
#define mmFMT5_FMT_BIT_DEPTH_CONTROL …
#define mmFMT_DITHER_RAND_R_SEED …
#define mmFMT0_FMT_DITHER_RAND_R_SEED …
#define mmFMT1_FMT_DITHER_RAND_R_SEED …
#define mmFMT2_FMT_DITHER_RAND_R_SEED …
#define mmFMT3_FMT_DITHER_RAND_R_SEED …
#define mmFMT4_FMT_DITHER_RAND_R_SEED …
#define mmFMT5_FMT_DITHER_RAND_R_SEED …
#define mmFMT_DITHER_RAND_G_SEED …
#define mmFMT0_FMT_DITHER_RAND_G_SEED …
#define mmFMT1_FMT_DITHER_RAND_G_SEED …
#define mmFMT2_FMT_DITHER_RAND_G_SEED …
#define mmFMT3_FMT_DITHER_RAND_G_SEED …
#define mmFMT4_FMT_DITHER_RAND_G_SEED …
#define mmFMT5_FMT_DITHER_RAND_G_SEED …
#define mmFMT_DITHER_RAND_B_SEED …
#define mmFMT0_FMT_DITHER_RAND_B_SEED …
#define mmFMT1_FMT_DITHER_RAND_B_SEED …
#define mmFMT2_FMT_DITHER_RAND_B_SEED …
#define mmFMT3_FMT_DITHER_RAND_B_SEED …
#define mmFMT4_FMT_DITHER_RAND_B_SEED …
#define mmFMT5_FMT_DITHER_RAND_B_SEED …
#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL …
#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL …
#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL …
#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL …
#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL …
#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL …
#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL …
#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX …
#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX …
#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX …
#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX …
#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX …
#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX …
#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX …
#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX …
#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX …
#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX …
#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX …
#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX …
#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX …
#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX …
#define mmFMT_CLAMP_CNTL …
#define mmFMT0_FMT_CLAMP_CNTL …
#define mmFMT1_FMT_CLAMP_CNTL …
#define mmFMT2_FMT_CLAMP_CNTL …
#define mmFMT3_FMT_CLAMP_CNTL …
#define mmFMT4_FMT_CLAMP_CNTL …
#define mmFMT5_FMT_CLAMP_CNTL …
#define mmFMT_CRC_CNTL …
#define mmFMT0_FMT_CRC_CNTL …
#define mmFMT1_FMT_CRC_CNTL …
#define mmFMT2_FMT_CRC_CNTL …
#define mmFMT3_FMT_CRC_CNTL …
#define mmFMT4_FMT_CRC_CNTL …
#define mmFMT5_FMT_CRC_CNTL …
#define mmFMT_CRC_SIG_RED_GREEN_MASK …
#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK …
#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK …
#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK …
#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK …
#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK …
#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK …
#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK …
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK …
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK …
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK …
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK …
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK …
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK …
#define mmFMT_CRC_SIG_RED_GREEN …
#define mmFMT0_FMT_CRC_SIG_RED_GREEN …
#define mmFMT1_FMT_CRC_SIG_RED_GREEN …
#define mmFMT2_FMT_CRC_SIG_RED_GREEN …
#define mmFMT3_FMT_CRC_SIG_RED_GREEN …
#define mmFMT4_FMT_CRC_SIG_RED_GREEN …
#define mmFMT5_FMT_CRC_SIG_RED_GREEN …
#define mmFMT_CRC_SIG_BLUE_CONTROL …
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL …
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL …
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL …
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL …
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL …
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL …
#define mmFMT_DEBUG_CNTL …
#define mmFMT0_FMT_DEBUG_CNTL …
#define mmFMT1_FMT_DEBUG_CNTL …
#define mmFMT2_FMT_DEBUG_CNTL …
#define mmFMT3_FMT_DEBUG_CNTL …
#define mmFMT4_FMT_DEBUG_CNTL …
#define mmFMT5_FMT_DEBUG_CNTL …
#define mmFMT_TEST_DEBUG_INDEX …
#define mmFMT0_FMT_TEST_DEBUG_INDEX …
#define mmFMT1_FMT_TEST_DEBUG_INDEX …
#define mmFMT2_FMT_TEST_DEBUG_INDEX …
#define mmFMT3_FMT_TEST_DEBUG_INDEX …
#define mmFMT4_FMT_TEST_DEBUG_INDEX …
#define mmFMT5_FMT_TEST_DEBUG_INDEX …
#define mmFMT_TEST_DEBUG_DATA …
#define mmFMT0_FMT_TEST_DEBUG_DATA …
#define mmFMT1_FMT_TEST_DEBUG_DATA …
#define mmFMT2_FMT_TEST_DEBUG_DATA …
#define mmFMT3_FMT_TEST_DEBUG_DATA …
#define mmFMT4_FMT_TEST_DEBUG_DATA …
#define mmFMT5_FMT_TEST_DEBUG_DATA …
#define ixFMT_DEBUG0 …
#define ixFMT_DEBUG1 …
#define ixFMT_DEBUG2 …
#define ixFMT_DEBUG_ID …
#define mmLB_DATA_FORMAT …
#define mmLB0_LB_DATA_FORMAT …
#define mmLB1_LB_DATA_FORMAT …
#define mmLB2_LB_DATA_FORMAT …
#define mmLB3_LB_DATA_FORMAT …
#define mmLB4_LB_DATA_FORMAT …
#define mmLB5_LB_DATA_FORMAT …
#define mmLB_MEMORY_CTRL …
#define mmLB0_LB_MEMORY_CTRL …
#define mmLB1_LB_MEMORY_CTRL …
#define mmLB2_LB_MEMORY_CTRL …
#define mmLB3_LB_MEMORY_CTRL …
#define mmLB4_LB_MEMORY_CTRL …
#define mmLB5_LB_MEMORY_CTRL …
#define mmLB_MEMORY_SIZE_STATUS …
#define mmLB0_LB_MEMORY_SIZE_STATUS …
#define mmLB1_LB_MEMORY_SIZE_STATUS …
#define mmLB2_LB_MEMORY_SIZE_STATUS …
#define mmLB3_LB_MEMORY_SIZE_STATUS …
#define mmLB4_LB_MEMORY_SIZE_STATUS …
#define mmLB5_LB_MEMORY_SIZE_STATUS …
#define mmLB_DESKTOP_HEIGHT …
#define mmLB0_LB_DESKTOP_HEIGHT …
#define mmLB1_LB_DESKTOP_HEIGHT …
#define mmLB2_LB_DESKTOP_HEIGHT …
#define mmLB3_LB_DESKTOP_HEIGHT …
#define mmLB4_LB_DESKTOP_HEIGHT …
#define mmLB5_LB_DESKTOP_HEIGHT …
#define mmLB_VLINE_START_END …
#define mmLB0_LB_VLINE_START_END …
#define mmLB1_LB_VLINE_START_END …
#define mmLB2_LB_VLINE_START_END …
#define mmLB3_LB_VLINE_START_END …
#define mmLB4_LB_VLINE_START_END …
#define mmLB5_LB_VLINE_START_END …
#define mmLB_VLINE2_START_END …
#define mmLB0_LB_VLINE2_START_END …
#define mmLB1_LB_VLINE2_START_END …
#define mmLB2_LB_VLINE2_START_END …
#define mmLB3_LB_VLINE2_START_END …
#define mmLB4_LB_VLINE2_START_END …
#define mmLB5_LB_VLINE2_START_END …
#define mmLB_V_COUNTER …
#define mmLB0_LB_V_COUNTER …
#define mmLB1_LB_V_COUNTER …
#define mmLB2_LB_V_COUNTER …
#define mmLB3_LB_V_COUNTER …
#define mmLB4_LB_V_COUNTER …
#define mmLB5_LB_V_COUNTER …
#define mmLB_SNAPSHOT_V_COUNTER …
#define mmLB0_LB_SNAPSHOT_V_COUNTER …
#define mmLB1_LB_SNAPSHOT_V_COUNTER …
#define mmLB2_LB_SNAPSHOT_V_COUNTER …
#define mmLB3_LB_SNAPSHOT_V_COUNTER …
#define mmLB4_LB_SNAPSHOT_V_COUNTER …
#define mmLB5_LB_SNAPSHOT_V_COUNTER …
#define mmLB_INTERRUPT_MASK …
#define mmLB0_LB_INTERRUPT_MASK …
#define mmLB1_LB_INTERRUPT_MASK …
#define mmLB2_LB_INTERRUPT_MASK …
#define mmLB3_LB_INTERRUPT_MASK …
#define mmLB4_LB_INTERRUPT_MASK …
#define mmLB5_LB_INTERRUPT_MASK …
#define mmLB_VLINE_STATUS …
#define mmLB0_LB_VLINE_STATUS …
#define mmLB1_LB_VLINE_STATUS …
#define mmLB2_LB_VLINE_STATUS …
#define mmLB3_LB_VLINE_STATUS …
#define mmLB4_LB_VLINE_STATUS …
#define mmLB5_LB_VLINE_STATUS …
#define mmLB_VLINE2_STATUS …
#define mmLB0_LB_VLINE2_STATUS …
#define mmLB1_LB_VLINE2_STATUS …
#define mmLB2_LB_VLINE2_STATUS …
#define mmLB3_LB_VLINE2_STATUS …
#define mmLB4_LB_VLINE2_STATUS …
#define mmLB5_LB_VLINE2_STATUS …
#define mmLB_VBLANK_STATUS …
#define mmLB0_LB_VBLANK_STATUS …
#define mmLB1_LB_VBLANK_STATUS …
#define mmLB2_LB_VBLANK_STATUS …
#define mmLB3_LB_VBLANK_STATUS …
#define mmLB4_LB_VBLANK_STATUS …
#define mmLB5_LB_VBLANK_STATUS …
#define mmLB_SYNC_RESET_SEL …
#define mmLB0_LB_SYNC_RESET_SEL …
#define mmLB1_LB_SYNC_RESET_SEL …
#define mmLB2_LB_SYNC_RESET_SEL …
#define mmLB3_LB_SYNC_RESET_SEL …
#define mmLB4_LB_SYNC_RESET_SEL …
#define mmLB5_LB_SYNC_RESET_SEL …
#define mmLB_BLACK_KEYER_R_CR …
#define mmLB0_LB_BLACK_KEYER_R_CR …
#define mmLB1_LB_BLACK_KEYER_R_CR …
#define mmLB2_LB_BLACK_KEYER_R_CR …
#define mmLB3_LB_BLACK_KEYER_R_CR …
#define mmLB4_LB_BLACK_KEYER_R_CR …
#define mmLB5_LB_BLACK_KEYER_R_CR …
#define mmLB_BLACK_KEYER_G_Y …
#define mmLB0_LB_BLACK_KEYER_G_Y …
#define mmLB1_LB_BLACK_KEYER_G_Y …
#define mmLB2_LB_BLACK_KEYER_G_Y …
#define mmLB3_LB_BLACK_KEYER_G_Y …
#define mmLB4_LB_BLACK_KEYER_G_Y …
#define mmLB5_LB_BLACK_KEYER_G_Y …
#define mmLB_BLACK_KEYER_B_CB …
#define mmLB0_LB_BLACK_KEYER_B_CB …
#define mmLB1_LB_BLACK_KEYER_B_CB …
#define mmLB2_LB_BLACK_KEYER_B_CB …
#define mmLB3_LB_BLACK_KEYER_B_CB …
#define mmLB4_LB_BLACK_KEYER_B_CB …
#define mmLB5_LB_BLACK_KEYER_B_CB …
#define mmLB_KEYER_COLOR_CTRL …
#define mmLB0_LB_KEYER_COLOR_CTRL …
#define mmLB1_LB_KEYER_COLOR_CTRL …
#define mmLB2_LB_KEYER_COLOR_CTRL …
#define mmLB3_LB_KEYER_COLOR_CTRL …
#define mmLB4_LB_KEYER_COLOR_CTRL …
#define mmLB5_LB_KEYER_COLOR_CTRL …
#define mmLB_KEYER_COLOR_R_CR …
#define mmLB0_LB_KEYER_COLOR_R_CR …
#define mmLB1_LB_KEYER_COLOR_R_CR …
#define mmLB2_LB_KEYER_COLOR_R_CR …
#define mmLB3_LB_KEYER_COLOR_R_CR …
#define mmLB4_LB_KEYER_COLOR_R_CR …
#define mmLB5_LB_KEYER_COLOR_R_CR …
#define mmLB_KEYER_COLOR_G_Y …
#define mmLB0_LB_KEYER_COLOR_G_Y …
#define mmLB1_LB_KEYER_COLOR_G_Y …
#define mmLB2_LB_KEYER_COLOR_G_Y …
#define mmLB3_LB_KEYER_COLOR_G_Y …
#define mmLB4_LB_KEYER_COLOR_G_Y …
#define mmLB5_LB_KEYER_COLOR_G_Y …
#define mmLB_KEYER_COLOR_B_CB …
#define mmLB0_LB_KEYER_COLOR_B_CB …
#define mmLB1_LB_KEYER_COLOR_B_CB …
#define mmLB2_LB_KEYER_COLOR_B_CB …
#define mmLB3_LB_KEYER_COLOR_B_CB …
#define mmLB4_LB_KEYER_COLOR_B_CB …
#define mmLB5_LB_KEYER_COLOR_B_CB …
#define mmLB_KEYER_COLOR_REP_R_CR …
#define mmLB0_LB_KEYER_COLOR_REP_R_CR …
#define mmLB1_LB_KEYER_COLOR_REP_R_CR …
#define mmLB2_LB_KEYER_COLOR_REP_R_CR …
#define mmLB3_LB_KEYER_COLOR_REP_R_CR …
#define mmLB4_LB_KEYER_COLOR_REP_R_CR …
#define mmLB5_LB_KEYER_COLOR_REP_R_CR …
#define mmLB_KEYER_COLOR_REP_G_Y …
#define mmLB0_LB_KEYER_COLOR_REP_G_Y …
#define mmLB1_LB_KEYER_COLOR_REP_G_Y …
#define mmLB2_LB_KEYER_COLOR_REP_G_Y …
#define mmLB3_LB_KEYER_COLOR_REP_G_Y …
#define mmLB4_LB_KEYER_COLOR_REP_G_Y …
#define mmLB5_LB_KEYER_COLOR_REP_G_Y …
#define mmLB_KEYER_COLOR_REP_B_CB …
#define mmLB0_LB_KEYER_COLOR_REP_B_CB …
#define mmLB1_LB_KEYER_COLOR_REP_B_CB …
#define mmLB2_LB_KEYER_COLOR_REP_B_CB …
#define mmLB3_LB_KEYER_COLOR_REP_B_CB …
#define mmLB4_LB_KEYER_COLOR_REP_B_CB …
#define mmLB5_LB_KEYER_COLOR_REP_B_CB …
#define mmLB_BUFFER_LEVEL_STATUS …
#define mmLB0_LB_BUFFER_LEVEL_STATUS …
#define mmLB1_LB_BUFFER_LEVEL_STATUS …
#define mmLB2_LB_BUFFER_LEVEL_STATUS …
#define mmLB3_LB_BUFFER_LEVEL_STATUS …
#define mmLB4_LB_BUFFER_LEVEL_STATUS …
#define mmLB5_LB_BUFFER_LEVEL_STATUS …
#define mmLB_BUFFER_URGENCY_CTRL …
#define mmLB0_LB_BUFFER_URGENCY_CTRL …
#define mmLB1_LB_BUFFER_URGENCY_CTRL …
#define mmLB2_LB_BUFFER_URGENCY_CTRL …
#define mmLB3_LB_BUFFER_URGENCY_CTRL …
#define mmLB4_LB_BUFFER_URGENCY_CTRL …
#define mmLB5_LB_BUFFER_URGENCY_CTRL …
#define mmLB_BUFFER_URGENCY_STATUS …
#define mmLB0_LB_BUFFER_URGENCY_STATUS …
#define mmLB1_LB_BUFFER_URGENCY_STATUS …
#define mmLB2_LB_BUFFER_URGENCY_STATUS …
#define mmLB3_LB_BUFFER_URGENCY_STATUS …
#define mmLB4_LB_BUFFER_URGENCY_STATUS …
#define mmLB5_LB_BUFFER_URGENCY_STATUS …
#define mmLB_BUFFER_STATUS …
#define mmLB0_LB_BUFFER_STATUS …
#define mmLB1_LB_BUFFER_STATUS …
#define mmLB2_LB_BUFFER_STATUS …
#define mmLB3_LB_BUFFER_STATUS …
#define mmLB4_LB_BUFFER_STATUS …
#define mmLB5_LB_BUFFER_STATUS …
#define mmLB_NO_OUTSTANDING_REQ_STATUS …
#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS …
#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS …
#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS …
#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS …
#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS …
#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS …
#define mmMVP_AFR_FLIP_MODE …
#define mmLB0_MVP_AFR_FLIP_MODE …
#define mmLB1_MVP_AFR_FLIP_MODE …
#define mmLB2_MVP_AFR_FLIP_MODE …
#define mmLB3_MVP_AFR_FLIP_MODE …
#define mmLB4_MVP_AFR_FLIP_MODE …
#define mmLB5_MVP_AFR_FLIP_MODE …
#define mmMVP_AFR_FLIP_FIFO_CNTL …
#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL …
#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL …
#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL …
#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL …
#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL …
#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL …
#define mmMVP_FLIP_LINE_NUM_INSERT …
#define mmLB0_MVP_FLIP_LINE_NUM_INSERT …
#define mmLB1_MVP_FLIP_LINE_NUM_INSERT …
#define mmLB2_MVP_FLIP_LINE_NUM_INSERT …
#define mmLB3_MVP_FLIP_LINE_NUM_INSERT …
#define mmLB4_MVP_FLIP_LINE_NUM_INSERT …
#define mmLB5_MVP_FLIP_LINE_NUM_INSERT …
#define mmDC_MVP_LB_CONTROL …
#define mmLB0_DC_MVP_LB_CONTROL …
#define mmLB1_DC_MVP_LB_CONTROL …
#define mmLB2_DC_MVP_LB_CONTROL …
#define mmLB3_DC_MVP_LB_CONTROL …
#define mmLB4_DC_MVP_LB_CONTROL …
#define mmLB5_DC_MVP_LB_CONTROL …
#define mmLB_DEBUG …
#define mmLB0_LB_DEBUG …
#define mmLB1_LB_DEBUG …
#define mmLB2_LB_DEBUG …
#define mmLB3_LB_DEBUG …
#define mmLB4_LB_DEBUG …
#define mmLB5_LB_DEBUG …
#define mmLB_DEBUG2 …
#define mmLB0_LB_DEBUG2 …
#define mmLB1_LB_DEBUG2 …
#define mmLB2_LB_DEBUG2 …
#define mmLB3_LB_DEBUG2 …
#define mmLB4_LB_DEBUG2 …
#define mmLB5_LB_DEBUG2 …
#define mmLB_DEBUG3 …
#define mmLB0_LB_DEBUG3 …
#define mmLB1_LB_DEBUG3 …
#define mmLB2_LB_DEBUG3 …
#define mmLB3_LB_DEBUG3 …
#define mmLB4_LB_DEBUG3 …
#define mmLB5_LB_DEBUG3 …
#define mmLB_TEST_DEBUG_INDEX …
#define mmLB0_LB_TEST_DEBUG_INDEX …
#define mmLB1_LB_TEST_DEBUG_INDEX …
#define mmLB2_LB_TEST_DEBUG_INDEX …
#define mmLB3_LB_TEST_DEBUG_INDEX …
#define mmLB4_LB_TEST_DEBUG_INDEX …
#define mmLB5_LB_TEST_DEBUG_INDEX …
#define mmLB_TEST_DEBUG_DATA …
#define mmLB0_LB_TEST_DEBUG_DATA …
#define mmLB1_LB_TEST_DEBUG_DATA …
#define mmLB2_LB_TEST_DEBUG_DATA …
#define mmLB3_LB_TEST_DEBUG_DATA …
#define mmLB4_LB_TEST_DEBUG_DATA …
#define mmLB5_LB_TEST_DEBUG_DATA …
#define mmMVP_CONTROL1 …
#define mmMVP_CONTROL2 …
#define mmMVP_FIFO_CONTROL …
#define mmMVP_FIFO_STATUS …
#define mmMVP_SLAVE_STATUS …
#define mmMVP_INBAND_CNTL_CAP …
#define mmMVP_BLACK_KEYER …
#define mmMVP_CRC_CNTL …
#define mmMVP_CRC_RESULT_BLUE_GREEN …
#define mmMVP_CRC_RESULT_RED …
#define mmMVP_CONTROL3 …
#define mmMVP_RECEIVE_CNT_CNTL1 …
#define mmMVP_RECEIVE_CNT_CNTL2 …
#define mmMVP_DEBUG …
#define mmMVP_TEST_DEBUG_INDEX …
#define mmMVP_TEST_DEBUG_DATA …
#define ixMVP_DEBUG_12 …
#define ixMVP_DEBUG_13 …
#define ixMVP_DEBUG_14 …
#define ixMVP_DEBUG_15 …
#define ixMVP_DEBUG_16 …
#define ixMVP_DEBUG_17 …
#define mmSCL_COEF_RAM_SELECT …
#define mmSCL0_SCL_COEF_RAM_SELECT …
#define mmSCL1_SCL_COEF_RAM_SELECT …
#define mmSCL2_SCL_COEF_RAM_SELECT …
#define mmSCL3_SCL_COEF_RAM_SELECT …
#define mmSCL4_SCL_COEF_RAM_SELECT …
#define mmSCL5_SCL_COEF_RAM_SELECT …
#define mmSCL_COEF_RAM_TAP_DATA …
#define mmSCL0_SCL_COEF_RAM_TAP_DATA …
#define mmSCL1_SCL_COEF_RAM_TAP_DATA …
#define mmSCL2_SCL_COEF_RAM_TAP_DATA …
#define mmSCL3_SCL_COEF_RAM_TAP_DATA …
#define mmSCL4_SCL_COEF_RAM_TAP_DATA …
#define mmSCL5_SCL_COEF_RAM_TAP_DATA …
#define mmSCL_MODE …
#define mmSCL0_SCL_MODE …
#define mmSCL1_SCL_MODE …
#define mmSCL2_SCL_MODE …
#define mmSCL3_SCL_MODE …
#define mmSCL4_SCL_MODE …
#define mmSCL5_SCL_MODE …
#define mmSCL_TAP_CONTROL …
#define mmSCL0_SCL_TAP_CONTROL …
#define mmSCL1_SCL_TAP_CONTROL …
#define mmSCL2_SCL_TAP_CONTROL …
#define mmSCL3_SCL_TAP_CONTROL …
#define mmSCL4_SCL_TAP_CONTROL …
#define mmSCL5_SCL_TAP_CONTROL …
#define mmSCL_CONTROL …
#define mmSCL0_SCL_CONTROL …
#define mmSCL1_SCL_CONTROL …
#define mmSCL2_SCL_CONTROL …
#define mmSCL3_SCL_CONTROL …
#define mmSCL4_SCL_CONTROL …
#define mmSCL5_SCL_CONTROL …
#define mmSCL_BYPASS_CONTROL …
#define mmSCL0_SCL_BYPASS_CONTROL …
#define mmSCL1_SCL_BYPASS_CONTROL …
#define mmSCL2_SCL_BYPASS_CONTROL …
#define mmSCL3_SCL_BYPASS_CONTROL …
#define mmSCL4_SCL_BYPASS_CONTROL …
#define mmSCL5_SCL_BYPASS_CONTROL …
#define mmSCL_MANUAL_REPLICATE_CONTROL …
#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL …
#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL …
#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL …
#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL …
#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL …
#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL …
#define mmSCL_AUTOMATIC_MODE_CONTROL …
#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL …
#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL …
#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL …
#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL …
#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL …
#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL …
#define mmSCL_HORZ_FILTER_CONTROL …
#define mmSCL0_SCL_HORZ_FILTER_CONTROL …
#define mmSCL1_SCL_HORZ_FILTER_CONTROL …
#define mmSCL2_SCL_HORZ_FILTER_CONTROL …
#define mmSCL3_SCL_HORZ_FILTER_CONTROL …
#define mmSCL4_SCL_HORZ_FILTER_CONTROL …
#define mmSCL5_SCL_HORZ_FILTER_CONTROL …
#define mmSCL_HORZ_FILTER_SCALE_RATIO …
#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO …
#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO …
#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO …
#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO …
#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO …
#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO …
#define mmSCL_HORZ_FILTER_INIT …
#define mmSCL0_SCL_HORZ_FILTER_INIT …
#define mmSCL1_SCL_HORZ_FILTER_INIT …
#define mmSCL2_SCL_HORZ_FILTER_INIT …
#define mmSCL3_SCL_HORZ_FILTER_INIT …
#define mmSCL4_SCL_HORZ_FILTER_INIT …
#define mmSCL5_SCL_HORZ_FILTER_INIT …
#define mmSCL_VERT_FILTER_CONTROL …
#define mmSCL0_SCL_VERT_FILTER_CONTROL …
#define mmSCL1_SCL_VERT_FILTER_CONTROL …
#define mmSCL2_SCL_VERT_FILTER_CONTROL …
#define mmSCL3_SCL_VERT_FILTER_CONTROL …
#define mmSCL4_SCL_VERT_FILTER_CONTROL …
#define mmSCL5_SCL_VERT_FILTER_CONTROL …
#define mmSCL_VERT_FILTER_SCALE_RATIO …
#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO …
#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO …
#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO …
#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO …
#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO …
#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO …
#define mmSCL_VERT_FILTER_INIT …
#define mmSCL0_SCL_VERT_FILTER_INIT …
#define mmSCL1_SCL_VERT_FILTER_INIT …
#define mmSCL2_SCL_VERT_FILTER_INIT …
#define mmSCL3_SCL_VERT_FILTER_INIT …
#define mmSCL4_SCL_VERT_FILTER_INIT …
#define mmSCL5_SCL_VERT_FILTER_INIT …
#define mmSCL_VERT_FILTER_INIT_BOT …
#define mmSCL0_SCL_VERT_FILTER_INIT_BOT …
#define mmSCL1_SCL_VERT_FILTER_INIT_BOT …
#define mmSCL2_SCL_VERT_FILTER_INIT_BOT …
#define mmSCL3_SCL_VERT_FILTER_INIT_BOT …
#define mmSCL4_SCL_VERT_FILTER_INIT_BOT …
#define mmSCL5_SCL_VERT_FILTER_INIT_BOT …
#define mmSCL_ROUND_OFFSET …
#define mmSCL0_SCL_ROUND_OFFSET …
#define mmSCL1_SCL_ROUND_OFFSET …
#define mmSCL2_SCL_ROUND_OFFSET …
#define mmSCL3_SCL_ROUND_OFFSET …
#define mmSCL4_SCL_ROUND_OFFSET …
#define mmSCL5_SCL_ROUND_OFFSET …
#define mmSCL_UPDATE …
#define mmSCL0_SCL_UPDATE …
#define mmSCL1_SCL_UPDATE …
#define mmSCL2_SCL_UPDATE …
#define mmSCL3_SCL_UPDATE …
#define mmSCL4_SCL_UPDATE …
#define mmSCL5_SCL_UPDATE …
#define mmSCL_F_SHARP_CONTROL …
#define mmSCL0_SCL_F_SHARP_CONTROL …
#define mmSCL1_SCL_F_SHARP_CONTROL …
#define mmSCL2_SCL_F_SHARP_CONTROL …
#define mmSCL3_SCL_F_SHARP_CONTROL …
#define mmSCL4_SCL_F_SHARP_CONTROL …
#define mmSCL5_SCL_F_SHARP_CONTROL …
#define mmSCL_ALU_CONTROL …
#define mmSCL0_SCL_ALU_CONTROL …
#define mmSCL1_SCL_ALU_CONTROL …
#define mmSCL2_SCL_ALU_CONTROL …
#define mmSCL3_SCL_ALU_CONTROL …
#define mmSCL4_SCL_ALU_CONTROL …
#define mmSCL5_SCL_ALU_CONTROL …
#define mmSCL_COEF_RAM_CONFLICT_STATUS …
#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS …
#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS …
#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS …
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS …
#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS …
#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS …
#define mmVIEWPORT_START …
#define mmSCL0_VIEWPORT_START …
#define mmSCL1_VIEWPORT_START …
#define mmSCL2_VIEWPORT_START …
#define mmSCL3_VIEWPORT_START …
#define mmSCL4_VIEWPORT_START …
#define mmSCL5_VIEWPORT_START …
#define mmVIEWPORT_SIZE …
#define mmSCL0_VIEWPORT_SIZE …
#define mmSCL1_VIEWPORT_SIZE …
#define mmSCL2_VIEWPORT_SIZE …
#define mmSCL3_VIEWPORT_SIZE …
#define mmSCL4_VIEWPORT_SIZE …
#define mmSCL5_VIEWPORT_SIZE …
#define mmEXT_OVERSCAN_LEFT_RIGHT …
#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT …
#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT …
#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT …
#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT …
#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT …
#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT …
#define mmEXT_OVERSCAN_TOP_BOTTOM …
#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM …
#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM …
#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM …
#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM …
#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM …
#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM …
#define mmSCL_MODE_CHANGE_DET1 …
#define mmSCL0_SCL_MODE_CHANGE_DET1 …
#define mmSCL1_SCL_MODE_CHANGE_DET1 …
#define mmSCL2_SCL_MODE_CHANGE_DET1 …
#define mmSCL3_SCL_MODE_CHANGE_DET1 …
#define mmSCL4_SCL_MODE_CHANGE_DET1 …
#define mmSCL5_SCL_MODE_CHANGE_DET1 …
#define mmSCL_MODE_CHANGE_DET2 …
#define mmSCL0_SCL_MODE_CHANGE_DET2 …
#define mmSCL1_SCL_MODE_CHANGE_DET2 …
#define mmSCL2_SCL_MODE_CHANGE_DET2 …
#define mmSCL3_SCL_MODE_CHANGE_DET2 …
#define mmSCL4_SCL_MODE_CHANGE_DET2 …
#define mmSCL5_SCL_MODE_CHANGE_DET2 …
#define mmSCL_MODE_CHANGE_DET3 …
#define mmSCL0_SCL_MODE_CHANGE_DET3 …
#define mmSCL1_SCL_MODE_CHANGE_DET3 …
#define mmSCL2_SCL_MODE_CHANGE_DET3 …
#define mmSCL3_SCL_MODE_CHANGE_DET3 …
#define mmSCL4_SCL_MODE_CHANGE_DET3 …
#define mmSCL5_SCL_MODE_CHANGE_DET3 …
#define mmSCL_MODE_CHANGE_MASK …
#define mmSCL0_SCL_MODE_CHANGE_MASK …
#define mmSCL1_SCL_MODE_CHANGE_MASK …
#define mmSCL2_SCL_MODE_CHANGE_MASK …
#define mmSCL3_SCL_MODE_CHANGE_MASK …
#define mmSCL4_SCL_MODE_CHANGE_MASK …
#define mmSCL5_SCL_MODE_CHANGE_MASK …
#define mmSCL_DEBUG2 …
#define mmSCL0_SCL_DEBUG2 …
#define mmSCL1_SCL_DEBUG2 …
#define mmSCL2_SCL_DEBUG2 …
#define mmSCL3_SCL_DEBUG2 …
#define mmSCL4_SCL_DEBUG2 …
#define mmSCL5_SCL_DEBUG2 …
#define mmSCL_DEBUG …
#define mmSCL0_SCL_DEBUG …
#define mmSCL1_SCL_DEBUG …
#define mmSCL2_SCL_DEBUG …
#define mmSCL3_SCL_DEBUG …
#define mmSCL4_SCL_DEBUG …
#define mmSCL5_SCL_DEBUG …
#define mmSCL_TEST_DEBUG_INDEX …
#define mmSCL0_SCL_TEST_DEBUG_INDEX …
#define mmSCL1_SCL_TEST_DEBUG_INDEX …
#define mmSCL2_SCL_TEST_DEBUG_INDEX …
#define mmSCL3_SCL_TEST_DEBUG_INDEX …
#define mmSCL4_SCL_TEST_DEBUG_INDEX …
#define mmSCL5_SCL_TEST_DEBUG_INDEX …
#define mmSCL_TEST_DEBUG_DATA …
#define mmSCL0_SCL_TEST_DEBUG_DATA …
#define mmSCL1_SCL_TEST_DEBUG_DATA …
#define mmSCL2_SCL_TEST_DEBUG_DATA …
#define mmSCL3_SCL_TEST_DEBUG_DATA …
#define mmSCL4_SCL_TEST_DEBUG_DATA …
#define mmSCL5_SCL_TEST_DEBUG_DATA …
#define mmGENMO_WT …
#define mmGENMO_RD …
#define mmGENENB …
#define mmGENFC_WT …
#define mmVGA0_GENFC_WT …
#define mmVGA1_GENFC_WT …
#define mmGENFC_RD …
#define mmGENS0 …
#define mmGENS1 …
#define mmVGA0_GENS1 …
#define mmVGA1_GENS1 …
#define mmDAC_DATA …
#define mmDAC_MASK …
#define mmDAC_R_INDEX …
#define mmDAC_W_INDEX …
#define mmSEQ8_IDX …
#define mmSEQ8_DATA …
#define ixSEQ00 …
#define ixSEQ01 …
#define ixSEQ02 …
#define ixSEQ03 …
#define ixSEQ04 …
#define mmCRTC8_IDX …
#define mmVGA0_CRTC8_IDX …
#define mmVGA1_CRTC8_IDX …
#define mmCRTC8_DATA …
#define mmVGA0_CRTC8_DATA …
#define mmVGA1_CRTC8_DATA …
#define ixCRT00 …
#define ixCRT01 …
#define ixCRT02 …
#define ixCRT03 …
#define ixCRT04 …
#define ixCRT05 …
#define ixCRT06 …
#define ixCRT07 …
#define ixCRT08 …
#define ixCRT09 …
#define ixCRT0A …
#define ixCRT0B …
#define ixCRT0C …
#define ixCRT0D …
#define ixCRT0E …
#define ixCRT0F …
#define ixCRT10 …
#define ixCRT11 …
#define ixCRT12 …
#define ixCRT13 …
#define ixCRT14 …
#define ixCRT15 …
#define ixCRT16 …
#define ixCRT17 …
#define ixCRT18 …
#define ixCRT1E …
#define ixCRT1F …
#define ixCRT22 …
#define mmGRPH8_IDX …
#define mmGRPH8_DATA …
#define ixGRA00 …
#define ixGRA01 …
#define ixGRA02 …
#define ixGRA03 …
#define ixGRA04 …
#define ixGRA05 …
#define ixGRA06 …
#define ixGRA07 …
#define ixGRA08 …
#define mmATTRX …
#define mmATTRDW …
#define mmATTRDR …
#define ixATTR00 …
#define ixATTR01 …
#define ixATTR02 …
#define ixATTR03 …
#define ixATTR04 …
#define ixATTR05 …
#define ixATTR06 …
#define ixATTR07 …
#define ixATTR08 …
#define ixATTR09 …
#define ixATTR0A …
#define ixATTR0B …
#define ixATTR0C …
#define ixATTR0D …
#define ixATTR0E …
#define ixATTR0F …
#define ixATTR10 …
#define ixATTR11 …
#define ixATTR12 …
#define ixATTR13 …
#define ixATTR14 …
#define mmVGA_RENDER_CONTROL …
#define mmVGA_SOURCE_SELECT …
#define mmVGA_SEQUENCER_RESET_CONTROL …
#define mmVGA_MODE_CONTROL …
#define mmVGA_SURFACE_PITCH_SELECT …
#define mmVGA_MEMORY_BASE_ADDRESS …
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH …
#define mmVGA_DISPBUF1_SURFACE_ADDR …
#define mmVGA_DISPBUF2_SURFACE_ADDR …
#define mmVGA_HDP_CONTROL …
#define mmVGA_CACHE_CONTROL …
#define mmD1VGA_CONTROL …
#define mmD2VGA_CONTROL …
#define mmD3VGA_CONTROL …
#define mmD4VGA_CONTROL …
#define mmD5VGA_CONTROL …
#define mmD6VGA_CONTROL …
#define mmVGA_HW_DEBUG …
#define mmVGA_STATUS …
#define mmVGA_INTERRUPT_CONTROL …
#define mmVGA_STATUS_CLEAR …
#define mmVGA_INTERRUPT_STATUS …
#define mmVGA_MAIN_CONTROL …
#define mmVGA_TEST_CONTROL …
#define mmVGA_DEBUG_READBACK_INDEX …
#define mmVGA_DEBUG_READBACK_DATA …
#define mmVGA_MEM_WRITE_PAGE_ADDR …
#define mmVGA_MEM_READ_PAGE_ADDR …
#define mmVGA_TEST_DEBUG_INDEX …
#define mmVGA_TEST_DEBUG_DATA …
#define ixVGADCC_DBG_DCCIF_C …
#define mmBPHYC_DAC_MACRO_CNTL …
#define mmBPHYC_DAC_AUTO_CALIB_CONTROL …
#define mmDPG_PIPE_ARBITRATION_CONTROL1 …
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 …
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 …
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 …
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 …
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 …
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 …
#define mmDPG_PIPE_ARBITRATION_CONTROL2 …
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 …
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 …
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 …
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 …
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 …
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 …
#define mmDPG_WATERMARK_MASK_CONTROL …
#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL …
#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL …
#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL …
#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL …
#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL …
#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL …
#define mmDPG_PIPE_URGENCY_CONTROL …
#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL …
#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL …
#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL …
#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL …
#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL …
#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL …
#define mmDPG_PIPE_DPM_CONTROL …
#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL …
#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL …
#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL …
#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL …
#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL …
#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL …
#define mmDPG_PIPE_STUTTER_CONTROL …
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL …
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL …
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL …
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL …
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL …
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL …
#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL …
#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL …
#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL …
#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL …
#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL …
#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL …
#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL …
#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH …
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH …
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH …
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH …
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH …
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH …
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH …
#define mmDPG_REPEATER_PROGRAM …
#define mmDMIF_PG0_DPG_REPEATER_PROGRAM …
#define mmDMIF_PG1_DPG_REPEATER_PROGRAM …
#define mmDMIF_PG2_DPG_REPEATER_PROGRAM …
#define mmDMIF_PG3_DPG_REPEATER_PROGRAM …
#define mmDMIF_PG4_DPG_REPEATER_PROGRAM …
#define mmDMIF_PG5_DPG_REPEATER_PROGRAM …
#define mmDPG_HW_DEBUG_A …
#define mmDMIF_PG0_DPG_HW_DEBUG_A …
#define mmDMIF_PG1_DPG_HW_DEBUG_A …
#define mmDMIF_PG2_DPG_HW_DEBUG_A …
#define mmDMIF_PG3_DPG_HW_DEBUG_A …
#define mmDMIF_PG4_DPG_HW_DEBUG_A …
#define mmDMIF_PG5_DPG_HW_DEBUG_A …
#define mmDPG_HW_DEBUG_B …
#define mmDMIF_PG0_DPG_HW_DEBUG_B …
#define mmDMIF_PG1_DPG_HW_DEBUG_B …
#define mmDMIF_PG2_DPG_HW_DEBUG_B …
#define mmDMIF_PG3_DPG_HW_DEBUG_B …
#define mmDMIF_PG4_DPG_HW_DEBUG_B …
#define mmDMIF_PG5_DPG_HW_DEBUG_B …
#define mmDPG_TEST_DEBUG_INDEX …
#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX …
#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX …
#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX …
#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX …
#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX …
#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX …
#define mmDPG_TEST_DEBUG_DATA …
#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA …
#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA …
#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA …
#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA …
#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA …
#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA …
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX …
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA …
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID …
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID …
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT …
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT …
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE …
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES …
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS …
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES …
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE …
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET …
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID …
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 …
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 …
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 …
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION …
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID …
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID …
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL …
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL …
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE …
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES …
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS …
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES …
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE …
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET …
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID …
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION …
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY …
#define mmAZALIA_F0_CODEC_DEBUG …
#define mmAZALIA_F0_GTC_GROUP_OFFSET0 …
#define mmAZALIA_F0_GTC_GROUP_OFFSET1 …
#define mmAZALIA_F0_GTC_GROUP_OFFSET2 …
#define mmAZALIA_F0_GTC_GROUP_OFFSET3 …
#define mmAZALIA_F0_GTC_GROUP_OFFSET4 …
#define mmAZALIA_F0_GTC_GROUP_OFFSET5 …
#define mmAZALIA_F0_GTC_GROUP_OFFSET6 …
#define mmGLOBAL_CAPABILITIES …
#define mmMINOR_VERSION …
#define mmMAJOR_VERSION …
#define mmOUTPUT_PAYLOAD_CAPABILITY …
#define mmINPUT_PAYLOAD_CAPABILITY …
#define mmGLOBAL_CONTROL …
#define mmWAKE_ENABLE …
#define mmSTATE_CHANGE_STATUS …
#define mmGLOBAL_STATUS …
#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY …
#define mmINTERRUPT_CONTROL …
#define mmINTERRUPT_STATUS …
#define mmWALL_CLOCK_COUNTER …
#define mmSTREAM_SYNCHRONIZATION …
#define mmCORB_LOWER_BASE_ADDRESS …
#define mmCORB_UPPER_BASE_ADDRESS …
#define mmCORB_WRITE_POINTER …
#define mmCORB_READ_POINTER …
#define mmCORB_CONTROL …
#define mmCORB_STATUS …
#define mmCORB_SIZE …
#define mmRIRB_LOWER_BASE_ADDRESS …
#define mmRIRB_UPPER_BASE_ADDRESS …
#define mmRIRB_WRITE_POINTER …
#define mmRESPONSE_INTERRUPT_COUNT …
#define mmRIRB_CONTROL …
#define mmRIRB_STATUS …
#define mmRIRB_SIZE …
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE …
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX …
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA …
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE …
#define mmIMMEDIATE_COMMAND_STATUS …
#define mmDMA_POSITION_LOWER_BASE_ADDRESS …
#define mmDMA_POSITION_UPPER_BASE_ADDRESS …
#define mmWALL_CLOCK_COUNTER_ALIAS …
#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS …
#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER …
#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH …
#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX …
#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE …
#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT …
#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS …
#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS …
#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS …
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX …
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA …
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES …
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES …
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS …
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT …
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID …
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER …
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 …
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 …
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL …
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE …
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING …
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES …
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES …
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA …
#define ixAUDIO_DESCRIPTOR0 …
#define ixAUDIO_DESCRIPTOR1 …
#define ixAUDIO_DESCRIPTOR2 …
#define ixAUDIO_DESCRIPTOR3 …
#define ixAUDIO_DESCRIPTOR4 …
#define ixAUDIO_DESCRIPTOR5 …
#define ixAUDIO_DESCRIPTOR6 …
#define ixAUDIO_DESCRIPTOR7 …
#define ixAUDIO_DESCRIPTOR8 …
#define ixAUDIO_DESCRIPTOR9 …
#define ixAUDIO_DESCRIPTOR10 …
#define ixAUDIO_DESCRIPTOR11 …
#define ixAUDIO_DESCRIPTOR12 …
#define ixAUDIO_DESCRIPTOR13 …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 …
#define ixSINK_DESCRIPTION0 …
#define ixSINK_DESCRIPTION1 …
#define ixSINK_DESCRIPTION2 …
#define ixSINK_DESCRIPTION3 …
#define ixSINK_DESCRIPTION4 …
#define ixSINK_DESCRIPTION5 …
#define ixSINK_DESCRIPTION6 …
#define ixSINK_DESCRIPTION7 …
#define ixSINK_DESCRIPTION8 …
#define ixSINK_DESCRIPTION9 …
#define ixSINK_DESCRIPTION10 …
#define ixSINK_DESCRIPTION11 …
#define ixSINK_DESCRIPTION12 …
#define ixSINK_DESCRIPTION13 …
#define ixSINK_DESCRIPTION14 …
#define ixSINK_DESCRIPTION15 …
#define ixSINK_DESCRIPTION16 …
#define ixSINK_DESCRIPTION17 …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 …
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 …
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO …
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS …
#define mmAZALIA_CONTROLLER_CLOCK_GATING …
#define mmAZALIA_AUDIO_DTO …
#define mmAZALIA_AUDIO_DTO_CONTROL …
#define mmAZALIA_SCLK_CONTROL …
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE …
#define mmAZALIA_DATA_DMA_CONTROL …
#define mmAZALIA_BDL_DMA_CONTROL …
#define mmAZALIA_RIRB_AND_DP_CONTROL …
#define mmAZALIA_CORB_DMA_CONTROL …
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER …
#define mmAZALIA_CYCLIC_BUFFER_SYNC …
#define mmAZALIA_GLOBAL_CAPABILITIES …
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY …
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL …
#define mmAZALIA_CONTROLLER_DEBUG …
#define mmAZALIA_CRC0_CONTROL0 …
#define mmAZALIA_CRC0_CONTROL1 …
#define mmAZALIA_CRC0_CONTROL2 …
#define mmAZALIA_CRC0_CONTROL3 …
#define mmAZALIA_CRC0_RESULT …
#define ixAZALIA_CRC0_CHANNEL0 …
#define ixAZALIA_CRC0_CHANNEL1 …
#define ixAZALIA_CRC0_CHANNEL2 …
#define ixAZALIA_CRC0_CHANNEL3 …
#define ixAZALIA_CRC0_CHANNEL4 …
#define ixAZALIA_CRC0_CHANNEL5 …
#define ixAZALIA_CRC0_CHANNEL6 …
#define ixAZALIA_CRC0_CHANNEL7 …
#define mmAZALIA_CRC1_CONTROL0 …
#define mmAZALIA_CRC1_CONTROL1 …
#define mmAZALIA_CRC1_CONTROL2 …
#define mmAZALIA_CRC1_CONTROL3 …
#define mmAZALIA_CRC1_RESULT …
#define ixAZALIA_CRC1_CHANNEL0 …
#define ixAZALIA_CRC1_CHANNEL1 …
#define ixAZALIA_CRC1_CHANNEL2 …
#define ixAZALIA_CRC1_CHANNEL3 …
#define ixAZALIA_CRC1_CHANNEL4 …
#define ixAZALIA_CRC1_CHANNEL5 …
#define ixAZALIA_CRC1_CHANNEL6 …
#define ixAZALIA_CRC1_CHANNEL7 …
#define mmAZ_TEST_DEBUG_INDEX …
#define mmAZ_TEST_DEBUG_DATA …
#define mmAZALIA_STREAM_INDEX …
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX …
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX …
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX …
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX …
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX …
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX …
#define mmAZALIA_STREAM_DATA …
#define mmAZF0STREAM0_AZALIA_STREAM_DATA …
#define mmAZF0STREAM1_AZALIA_STREAM_DATA …
#define mmAZF0STREAM2_AZALIA_STREAM_DATA …
#define mmAZF0STREAM3_AZALIA_STREAM_DATA …
#define mmAZF0STREAM4_AZALIA_STREAM_DATA …
#define mmAZF0STREAM5_AZALIA_STREAM_DATA …
#define ixAZALIA_FIFO_SIZE_CONTROL …
#define ixAZALIA_LATENCY_COUNTER_CONTROL …
#define ixAZALIA_WORSTCASE_LATENCY_COUNT …
#define ixAZALIA_CUMULATIVE_LATENCY_COUNT …
#define ixAZALIA_CUMULATIVE_REQUEST_COUNT …
#define ixAZALIA_STREAM_DEBUG …
#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX …
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX …
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX …
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX …
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX …
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX …
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX …
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX …
#define mmAZALIA_F0_CODEC_ENDPOINT_DATA …
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA …
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA …
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA …
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA …
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA …
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA …
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA …
#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG …
#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES …
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT …
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID …
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER …
#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS …
#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES …
#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL …
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE …
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING …
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG …
#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA …
#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN …
#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX …
#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES …
#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 …
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 …
#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO …
#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS …
#define mmBLND_CONTROL …
#define mmBLND0_BLND_CONTROL …
#define mmBLND1_BLND_CONTROL …
#define mmBLND2_BLND_CONTROL …
#define mmBLND3_BLND_CONTROL …
#define mmBLND4_BLND_CONTROL …
#define mmBLND5_BLND_CONTROL …
#define mmSM_CONTROL2 …
#define mmBLND0_SM_CONTROL2 …
#define mmBLND1_SM_CONTROL2 …
#define mmBLND2_SM_CONTROL2 …
#define mmBLND3_SM_CONTROL2 …
#define mmBLND4_SM_CONTROL2 …
#define mmBLND5_SM_CONTROL2 …
#define mmPTI_CONTROL …
#define mmBLND0_PTI_CONTROL …
#define mmBLND1_PTI_CONTROL …
#define mmBLND2_PTI_CONTROL …
#define mmBLND3_PTI_CONTROL …
#define mmBLND4_PTI_CONTROL …
#define mmBLND5_PTI_CONTROL …
#define mmBLND_UPDATE …
#define mmBLND0_BLND_UPDATE …
#define mmBLND1_BLND_UPDATE …
#define mmBLND2_BLND_UPDATE …
#define mmBLND3_BLND_UPDATE …
#define mmBLND4_BLND_UPDATE …
#define mmBLND5_BLND_UPDATE …
#define mmBLND_UNDERFLOW_INTERRUPT …
#define mmBLND0_BLND_UNDERFLOW_INTERRUPT …
#define mmBLND1_BLND_UNDERFLOW_INTERRUPT …
#define mmBLND2_BLND_UNDERFLOW_INTERRUPT …
#define mmBLND3_BLND_UNDERFLOW_INTERRUPT …
#define mmBLND4_BLND_UNDERFLOW_INTERRUPT …
#define mmBLND5_BLND_UNDERFLOW_INTERRUPT …
#define mmBLND_V_UPDATE_LOCK …
#define mmBLND0_BLND_V_UPDATE_LOCK …
#define mmBLND1_BLND_V_UPDATE_LOCK …
#define mmBLND2_BLND_V_UPDATE_LOCK …
#define mmBLND3_BLND_V_UPDATE_LOCK …
#define mmBLND4_BLND_V_UPDATE_LOCK …
#define mmBLND5_BLND_V_UPDATE_LOCK …
#define mmBLND_REG_UPDATE_STATUS …
#define mmBLND0_BLND_REG_UPDATE_STATUS …
#define mmBLND1_BLND_REG_UPDATE_STATUS …
#define mmBLND2_BLND_REG_UPDATE_STATUS …
#define mmBLND3_BLND_REG_UPDATE_STATUS …
#define mmBLND4_BLND_REG_UPDATE_STATUS …
#define mmBLND5_BLND_REG_UPDATE_STATUS …
#define mmBLND_DEBUG …
#define mmBLND0_BLND_DEBUG …
#define mmBLND1_BLND_DEBUG …
#define mmBLND2_BLND_DEBUG …
#define mmBLND3_BLND_DEBUG …
#define mmBLND4_BLND_DEBUG …
#define mmBLND5_BLND_DEBUG …
#define mmBLND_TEST_DEBUG_INDEX …
#define mmBLND0_BLND_TEST_DEBUG_INDEX …
#define mmBLND1_BLND_TEST_DEBUG_INDEX …
#define mmBLND2_BLND_TEST_DEBUG_INDEX …
#define mmBLND3_BLND_TEST_DEBUG_INDEX …
#define mmBLND4_BLND_TEST_DEBUG_INDEX …
#define mmBLND5_BLND_TEST_DEBUG_INDEX …
#define mmBLND_TEST_DEBUG_DATA …
#define mmBLND0_BLND_TEST_DEBUG_DATA …
#define mmBLND1_BLND_TEST_DEBUG_DATA …
#define mmBLND2_BLND_TEST_DEBUG_DATA …
#define mmBLND3_BLND_TEST_DEBUG_DATA …
#define mmBLND4_BLND_TEST_DEBUG_DATA …
#define mmBLND5_BLND_TEST_DEBUG_DATA …
#define mmSI_ENABLE …
#define mmSI_EC_CONFIG …
#define mmCNV_MODE …
#define mmCNV_WINDOW_START …
#define mmCNV_WINDOW_SIZE …
#define mmCNV_UPDATE …
#define mmCNV_SOURCE_SIZE …
#define mmCNV_CSC_CONTROL …
#define mmCNV_CSC_C11_C12 …
#define mmCNV_CSC_C13_C14 …
#define mmCNV_CSC_C21_C22 …
#define mmCNV_CSC_C23_C24 …
#define mmCNV_CSC_C31_C32 …
#define mmCNV_CSC_C33_C34 …
#define mmCNV_CSC_ROUND_OFFSET_R …
#define mmCNV_CSC_ROUND_OFFSET_G …
#define mmCNV_CSC_ROUND_OFFSET_B …
#define mmCNV_CSC_CLAMP_R …
#define mmCNV_CSC_CLAMP_G …
#define mmCNV_CSC_CLAMP_B …
#define mmCNV_TEST_CNTL …
#define mmCNV_TEST_CRC_RED …
#define mmCNV_TEST_CRC_GREEN …
#define mmCNV_TEST_CRC_BLUE …
#define mmSI_DEBUG_CTRL …
#define mmSI_DBG_MODE …
#define mmSI_HARD_DEBUG …
#define mmCNV_TEST_DEBUG_INDEX …
#define mmCNV_TEST_DEBUG_DATA …
#define mmSISCL_COEF_RAM_SELECT …
#define mmSISCL_COEF_RAM_TAP_DATA …
#define mmSISCL_MODE …
#define mmSISCL_TAP_CONTROL …
#define mmSISCL_DEST_SIZE …
#define mmSISCL_HORZ_FILTER_SCALE_RATIO …
#define mmSISCL_HORZ_FILTER_INIT_Y_RGB …
#define mmSISCL_HORZ_FILTER_INIT_CBCR …
#define mmSISCL_VERT_FILTER_SCALE_RATIO …
#define mmSISCL_VERT_FILTER_INIT_Y_RGB …
#define mmSISCL_VERT_FILTER_INIT_CBCR …
#define mmSISCL_ROUND_OFFSET …
#define mmSISCL_CLAMP …
#define mmSISCL_OVERFLOW_STATUS …
#define mmSISCL_COEF_RAM_CONFLICT_STATUS …
#define mmSISCL_OUTSIDE_PIX_STRATEGY …
#define mmSISCL_TEST_CNTL …
#define mmSISCL_TEST_CRC_RED …
#define mmSISCL_TEST_CRC_GREEN …
#define mmSISCL_TEST_CRC_BLUE …
#define mmSISCL_BACKPRESSURE_CNT_EN …
#define mmSISCL_MCIF_BACKPRESSURE_CNT …
#define mmSISCL_TEST_DEBUG_INDEX …
#define mmSISCL_TEST_DEBUG_DATA …
#define mmXDMA_MC_PCIE_CLIENT_CONFIG …
#define mmXDMA_LOCAL_SURFACE_TILING1 …
#define mmXDMA_LOCAL_SURFACE_TILING2 …
#define mmXDMA_INTERRUPT …
#define mmXDMA_CLOCK_GATING_CNTL …
#define mmXDMA_MEM_POWER_CNTL …
#define mmXDMA_IF_BIF_STATUS …
#define mmXDMA_PERF_MEAS_STATUS …
#define mmXDMA_IF_STATUS …
#define mmXDMA_TEST_DEBUG_INDEX …
#define mmXDMA_TEST_DEBUG_DATA …
#define mmXDMA_RBBMIF_RDWR_CNTL …
#define mmXDMA_PG_CONTROL …
#define mmXDMA_PG_WDATA …
#define mmXDMA_PG_STATUS …
#define mmXDMA_AON_TEST_DEBUG_INDEX …
#define mmXDMA_AON_TEST_DEBUG_DATA …

#endif /* DCE_8_0_D_H */