/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __SI_DPM_H__ #define __SI_DPM_H__ #include "amdgpu_atombios.h" #include "sislands_smc.h" #define MC_CG_CONFIG … #define MC_ARB_CG … #define CG_ARB_REQ(x) … #define CG_ARB_REQ_MASK … #define MC_ARB_DRAM_TIMING_1 … #define MC_ARB_DRAM_TIMING_2 … #define MC_ARB_DRAM_TIMING_3 … #define MC_ARB_DRAM_TIMING2_1 … #define MC_ARB_DRAM_TIMING2_2 … #define MC_ARB_DRAM_TIMING2_3 … #define MAX_NO_OF_MVDD_VALUES … #define MAX_NO_VREG_STEPS … #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE … #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE … #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT … #define RV770_ASI_DFLT … #define CYPRESS_HASI_DFLT … #define PCIE_PERF_REQ_PECI_GEN1 … #define PCIE_PERF_REQ_PECI_GEN2 … #define PCIE_PERF_REQ_PECI_GEN3 … #define RV770_DEFAULT_VCLK_FREQ … #define RV770_DEFAULT_DCLK_FREQ … #define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE … #define RV770_SMC_TABLE_ADDRESS … #define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE … #define SMC_STROBE_RATIO … #define SMC_STROBE_ENABLE … #define SMC_MC_EDC_RD_FLAG … #define SMC_MC_EDC_WR_FLAG … #define SMC_MC_RTT_ENABLE … #define SMC_MC_STUTTER_EN … #define RV770_SMC_VOLTAGEMASK_VDDC … #define RV770_SMC_VOLTAGEMASK_MVDD … #define RV770_SMC_VOLTAGEMASK_VDDCI … #define RV770_SMC_VOLTAGEMASK_MAX … #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE … #define NISLANDS_SMC_STROBE_RATIO … #define NISLANDS_SMC_STROBE_ENABLE … #define NISLANDS_SMC_MC_EDC_RD_FLAG … #define NISLANDS_SMC_MC_EDC_WR_FLAG … #define NISLANDS_SMC_MC_RTT_ENABLE … #define NISLANDS_SMC_MC_STUTTER_EN … #define MAX_NO_VREG_STEPS … #define NISLANDS_SMC_VOLTAGEMASK_VDDC … #define NISLANDS_SMC_VOLTAGEMASK_MVDD … #define NISLANDS_SMC_VOLTAGEMASK_VDDCI … #define NISLANDS_SMC_VOLTAGEMASK_MAX … #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT … #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT … #define SISLANDS_MCREGISTERTABLE_ULV_SLOT … #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT … #define SISLANDS_LEAKAGE_INDEX0 … #define SISLANDS_MAX_LEAKAGE_COUNT … #define SISLANDS_MAX_HARDWARE_POWERLEVELS … #define SISLANDS_INITIAL_STATE_ARB_INDEX … #define SISLANDS_ACPI_STATE_ARB_INDEX … #define SISLANDS_ULV_STATE_ARB_INDEX … #define SISLANDS_DRIVER_STATE_ARB_INDEX … #define SISLANDS_DPM2_MAX_PULSE_SKIP … #define SISLANDS_DPM2_NEAR_TDP_DEC … #define SISLANDS_DPM2_ABOVE_SAFE_INC … #define SISLANDS_DPM2_BELOW_SAFE_INC … #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT … #define SISLANDS_DPM2_MAXPS_PERCENT_H … #define SISLANDS_DPM2_MAXPS_PERCENT_M … #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER … #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER … #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA … #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE … #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO … #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN … #define SISLANDS_VRC_DFLT … #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT … #define SISLANDS_CGULVPARAMETER_DFLT … #define SISLANDS_CGULVCONTROL_DFLT … #define SI_ASI_DFLT … #define SI_BSP_DFLT … #define SI_BSU_DFLT … #define SI_AH_DFLT … #define SI_RLP_DFLT … #define SI_RMP_DFLT … #define SI_LHP_DFLT … #define SI_LMP_DFLT … #define SI_TD_DFLT … #define SI_UTC_DFLT_00 … #define SI_UTC_DFLT_01 … #define SI_UTC_DFLT_02 … #define SI_UTC_DFLT_03 … #define SI_UTC_DFLT_04 … #define SI_UTC_DFLT_05 … #define SI_UTC_DFLT_06 … #define SI_UTC_DFLT_07 … #define SI_UTC_DFLT_08 … #define SI_UTC_DFLT_09 … #define SI_UTC_DFLT_10 … #define SI_UTC_DFLT_11 … #define SI_UTC_DFLT_12 … #define SI_UTC_DFLT_13 … #define SI_UTC_DFLT_14 … #define SI_DTC_DFLT_00 … #define SI_DTC_DFLT_01 … #define SI_DTC_DFLT_02 … #define SI_DTC_DFLT_03 … #define SI_DTC_DFLT_04 … #define SI_DTC_DFLT_05 … #define SI_DTC_DFLT_06 … #define SI_DTC_DFLT_07 … #define SI_DTC_DFLT_08 … #define SI_DTC_DFLT_09 … #define SI_DTC_DFLT_10 … #define SI_DTC_DFLT_11 … #define SI_DTC_DFLT_12 … #define SI_DTC_DFLT_13 … #define SI_DTC_DFLT_14 … #define SI_VRC_DFLT … #define SI_VOLTAGERESPONSETIME_DFLT … #define SI_BACKBIASRESPONSETIME_DFLT … #define SI_VRU_DFLT … #define SI_SPLLSTEPTIME_DFLT … #define SI_SPLLSTEPUNIT_DFLT … #define SI_TPU_DFLT … #define SI_TPC_DFLT … #define SI_SSTU_DFLT … #define SI_SST_DFLT … #define SI_GICST_DFLT … #define SI_FCT_DFLT … #define SI_FCTU_DFLT … #define SI_CTXCGTT3DRPHC_DFLT … #define SI_CTXCGTT3DRSDC_DFLT … #define SI_VDDC3DOORPHC_DFLT … #define SI_VDDC3DOORSDC_DFLT … #define SI_VDDC3DOORSU_DFLT … #define SI_MPLLLOCKTIME_DFLT … #define SI_MPLLRESETTIME_DFLT … #define SI_VCOSTEPPCT_DFLT … #define SI_ENDINGVCOSTEPPCT_DFLT … #define SI_REFERENCEDIVIDER_DFLT … #define SI_PM_NUMBER_OF_TC … #define SI_PM_NUMBER_OF_SCLKS … #define SI_PM_NUMBER_OF_MCLKS … #define SI_PM_NUMBER_OF_VOLTAGE_LEVELS … #define SI_PM_NUMBER_OF_ACTIVITY_LEVELS … /* XXX are these ok? */ #define SI_TEMP_RANGE_MIN … #define SI_TEMP_RANGE_MAX … #define FDO_PWM_MODE_STATIC … #define FDO_PWM_MODE_STATIC_RPM … enum ni_dc_cac_level { … }; enum si_cac_config_reg_type { … }; enum si_power_level { … }; enum si_td { … }; enum si_display_watermark { … }; enum si_display_gap { … }; extern const struct amdgpu_ip_block_version si_smu_ip_block; struct ni_leakage_coeffients { … }; struct SMC_Evergreen_MCRegisterAddress { … }; SMC_Evergreen_MCRegisterAddress; struct evergreen_mc_reg_entry { … }; struct evergreen_mc_reg_table { … }; struct SMC_Evergreen_MCRegisterSet { … }; SMC_Evergreen_MCRegisterSet; struct SMC_Evergreen_MCRegisters { … }; SMC_Evergreen_MCRegisters; struct SMC_NIslands_MCRegisterSet { … }; SMC_NIslands_MCRegisterSet; struct ni_mc_reg_entry { … }; struct SMC_NIslands_MCRegisterAddress { … }; SMC_NIslands_MCRegisterAddress; struct SMC_NIslands_MCRegisters { … }; SMC_NIslands_MCRegisters; struct evergreen_ulv_param { … }; struct evergreen_arb_registers { … }; struct at { … }; struct ni_clock_registers { … }; struct RV770_SMC_SCLK_VALUE { … }; RV770_SMC_SCLK_VALUE; struct RV770_SMC_MCLK_VALUE { … }; RV770_SMC_MCLK_VALUE; struct RV730_SMC_MCLK_VALUE { … }; RV730_SMC_MCLK_VALUE; struct RV770_SMC_VOLTAGE_VALUE { … }; RV770_SMC_VOLTAGE_VALUE; RV7XX_SMC_MCLK_VALUE; LPRV7XX_SMC_MCLK_VALUE; struct RV770_SMC_HW_PERFORMANCE_LEVEL { … }; RV770_SMC_HW_PERFORMANCE_LEVEL; struct RV770_SMC_SWSTATE { … }; RV770_SMC_SWSTATE; struct RV770_SMC_VOLTAGEMASKTABLE { … }; RV770_SMC_VOLTAGEMASKTABLE; struct RV770_SMC_STATETABLE { … }; RV770_SMC_STATETABLE; struct vddc_table_entry { … }; struct rv770_clock_registers { … }; struct rv730_clock_registers { … }; r7xx_clock_registers; struct rv7xx_power_info { … }; enum si_pcie_gen { … }; struct rv7xx_pl { … }; struct rv7xx_ps { … }; struct si_ps { … }; struct ni_mc_reg_table { … }; struct ni_cac_data { … }; struct evergreen_power_info { … }; struct PP_NIslands_Dpm2PerfLevel { … }; PP_NIslands_Dpm2PerfLevel; struct PP_NIslands_DPM2Parameters { … }; PP_NIslands_DPM2Parameters; struct NISLANDS_SMC_SCLK_VALUE { … }; NISLANDS_SMC_SCLK_VALUE; struct NISLANDS_SMC_MCLK_VALUE { … }; NISLANDS_SMC_MCLK_VALUE; struct NISLANDS_SMC_VOLTAGE_VALUE { … }; NISLANDS_SMC_VOLTAGE_VALUE; struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL { … }; NISLANDS_SMC_HW_PERFORMANCE_LEVEL; struct NISLANDS_SMC_SWSTATE { … }; NISLANDS_SMC_SWSTATE; struct NISLANDS_SMC_VOLTAGEMASKTABLE { … }; NISLANDS_SMC_VOLTAGEMASKTABLE; #define NISLANDS_MAX_NO_VREG_STEPS … struct NISLANDS_SMC_STATETABLE { … }; NISLANDS_SMC_STATETABLE; struct ni_power_info { … }; struct si_cac_config_reg { … }; struct si_powertune_data { … }; struct si_dyn_powertune_data { … }; struct si_dte_data { … }; struct si_clock_registers { … }; struct si_mc_reg_entry { … }; struct si_mc_reg_table { … }; struct si_leakage_voltage_entry { … }; struct si_leakage_voltage { … }; struct si_ulv_param { … }; struct si_power_info { … }; #endif
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