/* * Copyright 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef SI_H #define SI_H #define TAHITI_RB_BITMAP_WIDTH_PER_SH … #define TAHITI_GB_ADDR_CONFIG_GOLDEN … #define VERDE_GB_ADDR_CONFIG_GOLDEN … #define HAINAN_GB_ADDR_CONFIG_GOLDEN … #define SI_MAX_SH_GPRS … #define SI_MAX_TEMP_GPRS … #define SI_MAX_SH_THREADS … #define SI_MAX_SH_STACK_ENTRIES … #define SI_MAX_FRC_EOV_CNT … #define SI_MAX_BACKENDS … #define SI_MAX_BACKENDS_MASK … #define SI_MAX_BACKENDS_PER_SE_MASK … #define SI_MAX_SIMDS … #define SI_MAX_SIMDS_MASK … #define SI_MAX_SIMDS_PER_SE_MASK … #define SI_MAX_PIPES … #define SI_MAX_PIPES_MASK … #define SI_MAX_PIPES_PER_SIMD_MASK … #define SI_MAX_LDS_NUM … #define SI_MAX_TCC … #define SI_MAX_TCC_MASK … #define SI_MAX_CTLACKS_ASSERTION_WAIT … /* SMC IND accessor regs */ #define SMC_IND_INDEX_0 … #define SMC_IND_DATA_0 … #define SMC_IND_ACCESS_CNTL … #define AUTO_INCREMENT_IND_0 … #define SMC_MESSAGE_0 … #define SMC_RESP_0 … /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ #define SMC_CG_IND_START … #define SMC_CG_IND_END … #define CG_CGTT_LOCAL_0 … #define CG_CGTT_LOCAL_1 … /* SMC IND registers */ #define SMC_SYSCON_RESET_CNTL … #define RST_REG … #define SMC_SYSCON_CLOCK_CNTL_0 … #define CK_DISABLE … #define CKEN … #define VGA_HDP_CONTROL … #define VGA_MEMORY_DISABLE … #define DCCG_DISP_SLOW_SELECT_REG … #define DCCG_DISP1_SLOW_SELECT(x) … #define DCCG_DISP1_SLOW_SELECT_MASK … #define DCCG_DISP1_SLOW_SELECT_SHIFT … #define DCCG_DISP2_SLOW_SELECT(x) … #define DCCG_DISP2_SLOW_SELECT_MASK … #define DCCG_DISP2_SLOW_SELECT_SHIFT … #define CG_SPLL_FUNC_CNTL … #define SPLL_RESET … #define SPLL_SLEEP … #define SPLL_BYPASS_EN … #define SPLL_REF_DIV(x) … #define SPLL_REF_DIV_MASK … #define SPLL_PDIV_A(x) … #define SPLL_PDIV_A_MASK … #define SPLL_PDIV_A_SHIFT … #define CG_SPLL_FUNC_CNTL_2 … #define SCLK_MUX_SEL(x) … #define SCLK_MUX_SEL_MASK … #define SPLL_CTLREQ_CHG … #define SCLK_MUX_UPDATE … #define CG_SPLL_FUNC_CNTL_3 … #define SPLL_FB_DIV(x) … #define SPLL_FB_DIV_MASK … #define SPLL_FB_DIV_SHIFT … #define SPLL_DITHEN … #define CG_SPLL_FUNC_CNTL_4 … #define SPLL_STATUS … #define SPLL_CHG_STATUS … #define SPLL_CNTL_MODE … #define SPLL_SW_DIR_CONTROL … #define SPLL_REFCLK_SEL(x) … #define SPLL_REFCLK_SEL_MASK … #define CG_SPLL_SPREAD_SPECTRUM … #define SSEN … #define CLK_S(x) … #define CLK_S_MASK … #define CLK_S_SHIFT … #define CG_SPLL_SPREAD_SPECTRUM_2 … #define CLK_V(x) … #define CLK_V_MASK … #define CLK_V_SHIFT … #define CG_SPLL_AUTOSCALE_CNTL … #define AUTOSCALE_ON_SS_CLEAR … /* discrete uvd clocks */ #define CG_UPLL_FUNC_CNTL … #define UPLL_RESET_MASK … #define UPLL_SLEEP_MASK … #define UPLL_BYPASS_EN_MASK … #define UPLL_CTLREQ_MASK … #define UPLL_VCO_MODE_MASK … #define UPLL_REF_DIV_MASK … #define UPLL_CTLACK_MASK … #define UPLL_CTLACK2_MASK … #define CG_UPLL_FUNC_CNTL_2 … #define UPLL_PDIV_A(x) … #define UPLL_PDIV_A_MASK … #define UPLL_PDIV_B(x) … #define UPLL_PDIV_B_MASK … #define VCLK_SRC_SEL(x) … #define VCLK_SRC_SEL_MASK … #define DCLK_SRC_SEL(x) … #define DCLK_SRC_SEL_MASK … #define CG_UPLL_FUNC_CNTL_3 … #define UPLL_FB_DIV(x) … #define UPLL_FB_DIV_MASK … #define CG_UPLL_FUNC_CNTL_4 … #define UPLL_SPARE_ISPARE9 … #define CG_UPLL_FUNC_CNTL_5 … #define RESET_ANTI_MUX_MASK … #define CG_UPLL_SPREAD_SPECTRUM … #define SSEN_MASK … #define MPLL_BYPASSCLK_SEL … #define MPLL_CLKOUT_SEL(x) … #define MPLL_CLKOUT_SEL_MASK … #define CG_CLKPIN_CNTL … #define XTALIN_DIVIDE … #define BCLK_AS_XCLK … #define CG_CLKPIN_CNTL_2 … #define FORCE_BIF_REFCLK_EN … #define MUX_TCLK_TO_XCLK … #define THM_CLK_CNTL … #define CMON_CLK_SEL(x) … #define CMON_CLK_SEL_MASK … #define TMON_CLK_SEL(x) … #define TMON_CLK_SEL_MASK … #define MISC_CLK_CNTL … #define DEEP_SLEEP_CLK_SEL(x) … #define DEEP_SLEEP_CLK_SEL_MASK … #define ZCLK_SEL(x) … #define ZCLK_SEL_MASK … #define CG_THERMAL_CTRL … #define DPM_EVENT_SRC(x) … #define DPM_EVENT_SRC_MASK … #define DIG_THERM_DPM(x) … #define DIG_THERM_DPM_MASK … #define DIG_THERM_DPM_SHIFT … #define CG_THERMAL_STATUS … #define FDO_PWM_DUTY(x) … #define FDO_PWM_DUTY_MASK … #define FDO_PWM_DUTY_SHIFT … #define CG_THERMAL_INT … #define DIG_THERM_INTH(x) … #define DIG_THERM_INTH_MASK … #define DIG_THERM_INTH_SHIFT … #define DIG_THERM_INTL(x) … #define DIG_THERM_INTL_MASK … #define DIG_THERM_INTL_SHIFT … #define THERM_INT_MASK_HIGH … #define THERM_INT_MASK_LOW … #define CG_MULT_THERMAL_CTRL … #define TEMP_SEL(x) … #define TEMP_SEL_MASK … #define TEMP_SEL_SHIFT … #define CG_MULT_THERMAL_STATUS … #define ASIC_MAX_TEMP(x) … #define ASIC_MAX_TEMP_MASK … #define ASIC_MAX_TEMP_SHIFT … #define CTF_TEMP(x) … #define CTF_TEMP_MASK … #define CTF_TEMP_SHIFT … #define CG_FDO_CTRL0 … #define FDO_STATIC_DUTY(x) … #define FDO_STATIC_DUTY_MASK … #define FDO_STATIC_DUTY_SHIFT … #define CG_FDO_CTRL1 … #define FMAX_DUTY100(x) … #define FMAX_DUTY100_MASK … #define FMAX_DUTY100_SHIFT … #define CG_FDO_CTRL2 … #define TMIN(x) … #define TMIN_MASK … #define TMIN_SHIFT … #define FDO_PWM_MODE(x) … #define FDO_PWM_MODE_MASK … #define FDO_PWM_MODE_SHIFT … #define TACH_PWM_RESP_RATE(x) … #define TACH_PWM_RESP_RATE_MASK … #define TACH_PWM_RESP_RATE_SHIFT … #define CG_TACH_CTRL … #define EDGE_PER_REV(x) … #define EDGE_PER_REV_MASK … #define EDGE_PER_REV_SHIFT … #define TARGET_PERIOD(x) … #define TARGET_PERIOD_MASK … #define TARGET_PERIOD_SHIFT … #define CG_TACH_STATUS … #define TACH_PERIOD(x) … #define TACH_PERIOD_MASK … #define TACH_PERIOD_SHIFT … #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define STATIC_PM_EN … #define THERMAL_PROTECTION_DIS … #define THERMAL_PROTECTION_TYPE … #define SW_SMIO_INDEX(x) … #define SW_SMIO_INDEX_MASK … #define SW_SMIO_INDEX_SHIFT … #define VOLT_PWRMGT_EN … #define DYN_SPREAD_SPECTRUM_EN … #define CG_TPC … #define SCLK_PWRMGT_CNTL … #define SCLK_PWRMGT_OFF … #define SCLK_LOW_D1 … #define FIR_RESET … #define FIR_FORCE_TREND_SEL … #define FIR_TREND_MODE … #define DYN_GFX_CLK_OFF_EN … #define GFX_CLK_FORCE_ON … #define GFX_CLK_REQUEST_OFF … #define GFX_CLK_FORCE_OFF … #define GFX_CLK_OFF_ACPI_D1 … #define GFX_CLK_OFF_ACPI_D2 … #define GFX_CLK_OFF_ACPI_D3 … #define DYN_LIGHT_SLEEP_EN … #define TARGET_AND_CURRENT_PROFILE_INDEX … #define CURRENT_STATE_INDEX_MASK … #define CURRENT_STATE_INDEX_SHIFT … #define CG_FTV … #define CG_FFCT_0 … #define UTC_0(x) … #define UTC_0_MASK … #define DTC_0(x) … #define DTC_0_MASK … #define CG_BSP … #define BSP(x) … #define BSP_MASK … #define BSU(x) … #define BSU_MASK … #define CG_AT … #define CG_R(x) … #define CG_R_MASK … #define CG_L(x) … #define CG_L_MASK … #define CG_GIT … #define CG_GICST(x) … #define CG_GICST_MASK … #define CG_GIPOT(x) … #define CG_GIPOT_MASK … #define CG_SSP … #define SST(x) … #define SST_MASK … #define SSTU(x) … #define SSTU_MASK … #define CG_DISPLAY_GAP_CNTL … #define DISP1_GAP(x) … #define DISP1_GAP_MASK … #define DISP2_GAP(x) … #define DISP2_GAP_MASK … #define VBI_TIMER_COUNT(x) … #define VBI_TIMER_COUNT_MASK … #define VBI_TIMER_UNIT(x) … #define VBI_TIMER_UNIT_MASK … #define DISP1_GAP_MCHG(x) … #define DISP1_GAP_MCHG_MASK … #define DISP2_GAP_MCHG(x) … #define DISP2_GAP_MCHG_MASK … #define CG_ULV_CONTROL … #define CG_ULV_PARAMETER … #define SMC_SCRATCH0 … #define CG_CAC_CTRL … #define CAC_WINDOW(x) … #define CAC_WINDOW_MASK … #define DMIF_ADDR_CONFIG … #define DMIF_ADDR_CALC … #define PIPE0_DMIF_BUFFER_CONTROL … #define DMIF_BUFFERS_ALLOCATED(x) … #define DMIF_BUFFERS_ALLOCATED_COMPLETED … #define SRBM_STATUS … #define GRBM_RQ_PENDING … #define VMC_BUSY … #define MCB_BUSY … #define MCB_NON_DISPLAY_BUSY … #define MCC_BUSY … #define MCD_BUSY … #define SEM_BUSY … #define IH_BUSY … #define SRBM_SOFT_RESET … #define SOFT_RESET_BIF … #define SOFT_RESET_DC … #define SOFT_RESET_DMA1 … #define SOFT_RESET_GRBM … #define SOFT_RESET_HDP … #define SOFT_RESET_IH … #define SOFT_RESET_MC … #define SOFT_RESET_ROM … #define SOFT_RESET_SEM … #define SOFT_RESET_VMC … #define SOFT_RESET_DMA … #define SOFT_RESET_TST … #define SOFT_RESET_REGBB … #define SOFT_RESET_ORB … #define CC_SYS_RB_BACKEND_DISABLE … #define GC_USER_SYS_RB_BACKEND_DISABLE … #define SRBM_READ_ERROR … #define SRBM_INT_CNTL … #define SRBM_INT_ACK … #define SRBM_STATUS2 … #define DMA_BUSY … #define DMA1_BUSY … #define VM_L2_CNTL … #define ENABLE_L2_CACHE … #define ENABLE_L2_FRAGMENT_PROCESSING … #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) … #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) … #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE … #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE … #define EFFECTIVE_L2_QUEUE_SIZE(x) … #define CONTEXT1_IDENTITY_ACCESS_MODE(x) … #define VM_L2_CNTL2 … #define INVALIDATE_ALL_L1_TLBS … #define INVALIDATE_L2_CACHE … #define INVALIDATE_CACHE_MODE(x) … #define INVALIDATE_PTE_AND_PDE_CACHES … #define INVALIDATE_ONLY_PTE_CACHES … #define INVALIDATE_ONLY_PDE_CACHES … #define VM_L2_CNTL3 … #define BANK_SELECT(x) … #define L2_CACHE_UPDATE_MODE(x) … #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) … #define L2_CACHE_BIGK_ASSOCIATIVITY … #define VM_L2_STATUS … #define L2_BUSY … #define VM_CONTEXT0_CNTL … #define ENABLE_CONTEXT … #define PAGE_TABLE_DEPTH(x) … #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT … #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT … #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT … #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT … #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT … #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT … #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT … #define READ_PROTECTION_FAULT_ENABLE_DEFAULT … #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT … #define PAGE_TABLE_BLOCK_SIZE(x) … #define VM_CONTEXT1_CNTL … #define VM_CONTEXT0_CNTL2 … #define VM_CONTEXT1_CNTL2 … #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT1_PROTECTION_FAULT_ADDR … #define VM_CONTEXT1_PROTECTION_FAULT_STATUS … #define PROTECTIONS_MASK … #define PROTECTIONS_SHIFT … /* bit 0: range * bit 1: pde0 * bit 2: valid * bit 3: read * bit 4: write */ #define MEMORY_CLIENT_ID_MASK … #define MEMORY_CLIENT_ID_SHIFT … #define MEMORY_CLIENT_RW_MASK … #define MEMORY_CLIENT_RW_SHIFT … #define FAULT_VMID_MASK … #define FAULT_VMID_SHIFT … #define VM_INVALIDATE_REQUEST … #define VM_INVALIDATE_RESPONSE … #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR … #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR … #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT0_PAGE_TABLE_START_ADDR … #define VM_CONTEXT1_PAGE_TABLE_START_ADDR … #define VM_CONTEXT0_PAGE_TABLE_END_ADDR … #define VM_CONTEXT1_PAGE_TABLE_END_ADDR … #define VM_L2_CG … #define MC_CG_ENABLE … #define MC_LS_ENABLE … #define MC_SHARED_CHMAP … #define NOOFCHAN_SHIFT … #define NOOFCHAN_MASK … #define MC_SHARED_CHREMAP … #define MC_VM_FB_LOCATION … #define MC_VM_AGP_TOP … #define MC_VM_AGP_BOT … #define MC_VM_AGP_BASE … #define MC_VM_SYSTEM_APERTURE_LOW_ADDR … #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR … #define MC_VM_MX_L1_TLB_CNTL … #define ENABLE_L1_TLB … #define ENABLE_L1_FRAGMENT_PROCESSING … #define SYSTEM_ACCESS_MODE_PA_ONLY … #define SYSTEM_ACCESS_MODE_USE_SYS_MAP … #define SYSTEM_ACCESS_MODE_IN_SYS … #define SYSTEM_ACCESS_MODE_NOT_IN_SYS … #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU … #define ENABLE_ADVANCED_DRIVER_MODEL … #define MC_SHARED_BLACKOUT_CNTL … #define MC_HUB_MISC_HUB_CG … #define MC_HUB_MISC_VM_CG … #define MC_HUB_MISC_SIP_CG … #define MC_XPB_CLK_GAT … #define MC_CITF_MISC_RD_CG … #define MC_CITF_MISC_WR_CG … #define MC_CITF_MISC_VM_CG … #define MC_ARB_RAMCFG … #define NOOFBANK_SHIFT … #define NOOFBANK_MASK … #define NOOFRANK_SHIFT … #define NOOFRANK_MASK … #define NOOFROWS_SHIFT … #define NOOFROWS_MASK … #define NOOFCOLS_SHIFT … #define NOOFCOLS_MASK … #define CHANSIZE_SHIFT … #define CHANSIZE_MASK … #define CHANSIZE_OVERRIDE … #define NOOFGROUPS_SHIFT … #define NOOFGROUPS_MASK … #define MC_ARB_DRAM_TIMING … #define MC_ARB_DRAM_TIMING2 … #define MC_ARB_BURST_TIME … #define STATE0(x) … #define STATE0_MASK … #define STATE0_SHIFT … #define STATE1(x) … #define STATE1_MASK … #define STATE1_SHIFT … #define STATE2(x) … #define STATE2_MASK … #define STATE2_SHIFT … #define STATE3(x) … #define STATE3_MASK … #define STATE3_SHIFT … #define MC_SEQ_TRAIN_WAKEUP_CNTL … #define TRAIN_DONE_D0 … #define TRAIN_DONE_D1 … #define MC_SEQ_SUP_CNTL … #define RUN_MASK … #define MC_SEQ_SUP_PGM … #define MC_PMG_AUTO_CMD … #define MC_IO_PAD_CNTL_D0 … #define MEM_FALL_OUT_CMD … #define MC_SEQ_RAS_TIMING … #define MC_SEQ_CAS_TIMING … #define MC_SEQ_MISC_TIMING … #define MC_SEQ_MISC_TIMING2 … #define MC_SEQ_PMG_TIMING … #define MC_SEQ_RD_CTL_D0 … #define MC_SEQ_RD_CTL_D1 … #define MC_SEQ_WR_CTL_D0 … #define MC_SEQ_WR_CTL_D1 … #define MC_SEQ_MISC0 … #define MC_SEQ_MISC0_VEN_ID_SHIFT … #define MC_SEQ_MISC0_VEN_ID_MASK … #define MC_SEQ_MISC0_VEN_ID_VALUE … #define MC_SEQ_MISC0_REV_ID_SHIFT … #define MC_SEQ_MISC0_REV_ID_MASK … #define MC_SEQ_MISC0_REV_ID_VALUE … #define MC_SEQ_MISC0_GDDR5_SHIFT … #define MC_SEQ_MISC0_GDDR5_MASK … #define MC_SEQ_MISC0_GDDR5_VALUE … #define MC_SEQ_MISC1 … #define MC_SEQ_RESERVE_M … #define MC_PMG_CMD_EMRS … #define MC_SEQ_IO_DEBUG_INDEX … #define MC_SEQ_IO_DEBUG_DATA … #define MC_SEQ_MISC5 … #define MC_SEQ_MISC6 … #define MC_SEQ_MISC7 … #define MC_SEQ_RAS_TIMING_LP … #define MC_SEQ_CAS_TIMING_LP … #define MC_SEQ_MISC_TIMING_LP … #define MC_SEQ_MISC_TIMING2_LP … #define MC_SEQ_WR_CTL_D0_LP … #define MC_SEQ_WR_CTL_D1_LP … #define MC_SEQ_PMG_CMD_EMRS_LP … #define MC_SEQ_PMG_CMD_MRS_LP … #define MC_PMG_CMD_MRS … #define MC_SEQ_RD_CTL_D0_LP … #define MC_SEQ_RD_CTL_D1_LP … #define MC_PMG_CMD_MRS1 … #define MC_SEQ_PMG_CMD_MRS1_LP … #define MC_SEQ_PMG_TIMING_LP … #define MC_SEQ_WR_CTL_2 … #define MC_SEQ_WR_CTL_2_LP … #define MC_PMG_CMD_MRS2 … #define MC_SEQ_PMG_CMD_MRS2_LP … #define MCLK_PWRMGT_CNTL … #define DLL_SPEED(x) … #define DLL_SPEED_MASK … #define DLL_READY … #define MC_INT_CNTL … #define MRDCK0_PDNB … #define MRDCK1_PDNB … #define MRDCK0_RESET … #define MRDCK1_RESET … #define DLL_READY_READ … #define DLL_CNTL … #define MRDCK0_BYPASS … #define MRDCK1_BYPASS … #define MPLL_CNTL_MODE … #define MPLL_MCLK_SEL … #define MPLL_FUNC_CNTL … #define BWCTRL(x) … #define BWCTRL_MASK … #define MPLL_FUNC_CNTL_1 … #define VCO_MODE(x) … #define VCO_MODE_MASK … #define CLKFRAC(x) … #define CLKFRAC_MASK … #define CLKF(x) … #define CLKF_MASK … #define MPLL_FUNC_CNTL_2 … #define MPLL_AD_FUNC_CNTL … #define YCLK_POST_DIV(x) … #define YCLK_POST_DIV_MASK … #define MPLL_DQ_FUNC_CNTL … #define YCLK_SEL(x) … #define YCLK_SEL_MASK … #define MPLL_SS1 … #define CLKV(x) … #define CLKV_MASK … #define MPLL_SS2 … #define CLKS(x) … #define CLKS_MASK … #define HDP_HOST_PATH_CNTL … #define CLOCK_GATING_DIS … #define HDP_NONSURFACE_BASE … #define HDP_NONSURFACE_INFO … #define HDP_NONSURFACE_SIZE … #define HDP_DEBUG0 … #define HDP_ADDR_CONFIG … #define HDP_MISC_CNTL … #define HDP_FLUSH_INVALIDATE_CACHE … #define HDP_MEM_POWER_LS … #define HDP_LS_ENABLE … #define ATC_MISC_CG … #define IH_RB_CNTL … #define IH_RB_ENABLE … #define IH_IB_SIZE(x) … #define IH_RB_FULL_DRAIN_ENABLE … #define IH_WPTR_WRITEBACK_ENABLE … #define IH_WPTR_WRITEBACK_TIMER(x) … #define IH_WPTR_OVERFLOW_ENABLE … #define IH_WPTR_OVERFLOW_CLEAR … #define IH_RB_BASE … #define IH_RB_RPTR … #define IH_RB_WPTR … #define RB_OVERFLOW … #define WPTR_OFFSET_MASK … #define IH_RB_WPTR_ADDR_HI … #define IH_RB_WPTR_ADDR_LO … #define IH_CNTL … #define ENABLE_INTR … #define IH_MC_SWAP(x) … #define IH_MC_SWAP_NONE … #define IH_MC_SWAP_16BIT … #define IH_MC_SWAP_32BIT … #define IH_MC_SWAP_64BIT … #define RPTR_REARM … #define MC_WRREQ_CREDIT(x) … #define MC_WR_CLEAN_CNT(x) … #define MC_VMID(x) … #define CONFIG_MEMSIZE … #define INTERRUPT_CNTL … #define IH_DUMMY_RD_OVERRIDE … #define IH_DUMMY_RD_EN … #define IH_REQ_NONSNOOP_EN … #define GEN_IH_INT_EN … #define INTERRUPT_CNTL2 … #define HDP_MEM_COHERENCY_FLUSH_CNTL … #define BIF_FB_EN … #define FB_READ_EN … #define FB_WRITE_EN … #define HDP_REG_COHERENCY_FLUSH_CNTL … /* DCE6 ELD audio interface */ #define AZ_F0_CODEC_ENDPOINT_INDEX … #define AZ_ENDPOINT_REG_INDEX(x) … #define AZ_ENDPOINT_REG_WRITE_EN … #define AZ_F0_CODEC_ENDPOINT_DATA … #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define SPEAKER_ALLOCATION(x) … #define SPEAKER_ALLOCATION_MASK … #define SPEAKER_ALLOCATION_SHIFT … #define HDMI_CONNECTION … #define DP_CONNECTION … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define MAX_CHANNELS(x) … /* max channels minus one. 7 = 8 channels */ #define SUPPORTED_FREQUENCIES(x) … #define DESCRIPTOR_BYTE_2(x) … #define SUPPORTED_FREQUENCIES_STEREO(x) … /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO * bit0 = 32 kHz * bit1 = 44.1 kHz * bit2 = 48 kHz * bit3 = 88.2 kHz * bit4 = 96 kHz * bit5 = 176.4 kHz * bit6 = 192 kHz */ #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define VIDEO_LIPSYNC(x) … #define AUDIO_LIPSYNC(x) … /* VIDEO_LIPSYNC, AUDIO_LIPSYNC * 0 = invalid * x = legal delay value * 255 = sync not supported */ #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define HBR_CAPABLE … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define MANUFACTURER_ID(x) … #define PRODUCT_ID(x) … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define SINK_DESCRIPTION_LEN(x) … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define PORT_ID0(x) … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define PORT_ID1(x) … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define DESCRIPTION0(x) … #define DESCRIPTION1(x) … #define DESCRIPTION2(x) … #define DESCRIPTION3(x) … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define DESCRIPTION4(x) … #define DESCRIPTION5(x) … #define DESCRIPTION6(x) … #define DESCRIPTION7(x) … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define DESCRIPTION8(x) … #define DESCRIPTION9(x) … #define DESCRIPTION10(x) … #define DESCRIPTION11(x) … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define DESCRIPTION12(x) … #define DESCRIPTION13(x) … #define DESCRIPTION14(x) … #define DESCRIPTION15(x) … #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define DESCRIPTION16(x) … #define DESCRIPTION17(x) … #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define AUDIO_ENABLED … #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define PORT_CONNECTIVITY_MASK … #define PORT_CONNECTIVITY_SHIFT … #define DC_LB_MEMORY_SPLIT … #define DC_LB_MEMORY_CONFIG(x) … #define PRIORITY_A_CNT … #define PRIORITY_MARK_MASK … #define PRIORITY_OFF … #define PRIORITY_ALWAYS_ON … #define PRIORITY_B_CNT … #define DPG_PIPE_ARBITRATION_CONTROL3 … #define LATENCY_WATERMARK_MASK(x) … #define DPG_PIPE_LATENCY_CONTROL … #define LATENCY_LOW_WATERMARK(x) … #define LATENCY_HIGH_WATERMARK(x) … /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ #define VLINE_STATUS … #define VLINE_OCCURRED … #define VLINE_ACK … #define VLINE_STAT … #define VLINE_INTERRUPT … #define VLINE_INTERRUPT_TYPE … /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ #define VBLANK_STATUS … #define VBLANK_OCCURRED … #define VBLANK_ACK … #define VBLANK_STAT … #define VBLANK_INTERRUPT … #define VBLANK_INTERRUPT_TYPE … /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ #define INT_MASK … #define VBLANK_INT_MASK … #define VLINE_INT_MASK … #define DISP_INTERRUPT_STATUS … #define LB_D1_VLINE_INTERRUPT … #define LB_D1_VBLANK_INTERRUPT … #define DC_HPD1_INTERRUPT … #define DC_HPD1_RX_INTERRUPT … #define DACA_AUTODETECT_INTERRUPT … #define DACB_AUTODETECT_INTERRUPT … #define DC_I2C_SW_DONE_INTERRUPT … #define DC_I2C_HW_DONE_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE … #define LB_D2_VLINE_INTERRUPT … #define LB_D2_VBLANK_INTERRUPT … #define DC_HPD2_INTERRUPT … #define DC_HPD2_RX_INTERRUPT … #define DISP_TIMER_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE2 … #define LB_D3_VLINE_INTERRUPT … #define LB_D3_VBLANK_INTERRUPT … #define DC_HPD3_INTERRUPT … #define DC_HPD3_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE3 … #define LB_D4_VLINE_INTERRUPT … #define LB_D4_VBLANK_INTERRUPT … #define DC_HPD4_INTERRUPT … #define DC_HPD4_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE4 … #define LB_D5_VLINE_INTERRUPT … #define LB_D5_VBLANK_INTERRUPT … #define DC_HPD5_INTERRUPT … #define DC_HPD5_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE5 … #define LB_D6_VLINE_INTERRUPT … #define LB_D6_VBLANK_INTERRUPT … #define DC_HPD6_INTERRUPT … #define DC_HPD6_RX_INTERRUPT … /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ #define GRPH_INT_STATUS … #define GRPH_PFLIP_INT_OCCURRED … #define GRPH_PFLIP_INT_CLEAR … /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ #define GRPH_INT_CONTROL … #define GRPH_PFLIP_INT_MASK … #define GRPH_PFLIP_INT_TYPE … #define DAC_AUTODETECT_INT_CONTROL … #define DC_HPD1_INT_STATUS … #define DC_HPD2_INT_STATUS … #define DC_HPD3_INT_STATUS … #define DC_HPD4_INT_STATUS … #define DC_HPD5_INT_STATUS … #define DC_HPD6_INT_STATUS … #define DC_HPDx_INT_STATUS … #define DC_HPDx_SENSE … #define DC_HPDx_RX_INT_STATUS … #define DC_HPD1_INT_CONTROL … #define DC_HPD2_INT_CONTROL … #define DC_HPD3_INT_CONTROL … #define DC_HPD4_INT_CONTROL … #define DC_HPD5_INT_CONTROL … #define DC_HPD6_INT_CONTROL … #define DC_HPDx_INT_ACK … #define DC_HPDx_INT_POLARITY … #define DC_HPDx_INT_EN … #define DC_HPDx_RX_INT_ACK … #define DC_HPDx_RX_INT_EN … #define DC_HPD1_CONTROL … #define DC_HPD2_CONTROL … #define DC_HPD3_CONTROL … #define DC_HPD4_CONTROL … #define DC_HPD5_CONTROL … #define DC_HPD6_CONTROL … #define DC_HPDx_CONNECTION_TIMER(x) … #define DC_HPDx_RX_INT_TIMER(x) … #define DC_HPDx_EN … #define DPG_PIPE_STUTTER_CONTROL … #define STUTTER_ENABLE … /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ #define CRTC_STATUS_FRAME_COUNT … /* Audio clocks */ #define DCCG_AUDIO_DTO_SOURCE … #define DCCG_AUDIO_DTO0_SOURCE_SEL(x) … #define DCCG_AUDIO_DTO_SEL … #define DCCG_AUDIO_DTO0_PHASE … #define DCCG_AUDIO_DTO0_MODULE … #define DCCG_AUDIO_DTO1_PHASE … #define DCCG_AUDIO_DTO1_MODULE … #define AFMT_AUDIO_SRC_CONTROL … #define AFMT_AUDIO_SRC_SELECT(x) … /* AFMT_AUDIO_SRC_SELECT * 0 = stream0 * 1 = stream1 * 2 = stream2 * 3 = stream3 * 4 = stream4 * 5 = stream5 */ #define GRBM_CNTL … #define GRBM_READ_TIMEOUT(x) … #define GRBM_STATUS2 … #define RLC_RQ_PENDING … #define RLC_BUSY … #define TC_BUSY … #define GRBM_STATUS … #define CMDFIFO_AVAIL_MASK … #define RING2_RQ_PENDING … #define SRBM_RQ_PENDING … #define RING1_RQ_PENDING … #define CF_RQ_PENDING … #define PF_RQ_PENDING … #define GDS_DMA_RQ_PENDING … #define GRBM_EE_BUSY … #define DB_CLEAN … #define CB_CLEAN … #define TA_BUSY … #define GDS_BUSY … #define VGT_BUSY … #define IA_BUSY_NO_DMA … #define IA_BUSY … #define SX_BUSY … #define SPI_BUSY … #define BCI_BUSY … #define SC_BUSY … #define PA_BUSY … #define DB_BUSY … #define CP_COHERENCY_BUSY … #define CP_BUSY … #define CB_BUSY … #define GUI_ACTIVE … #define GRBM_STATUS_SE0 … #define GRBM_STATUS_SE1 … #define SE_DB_CLEAN … #define SE_CB_CLEAN … #define SE_BCI_BUSY … #define SE_VGT_BUSY … #define SE_PA_BUSY … #define SE_TA_BUSY … #define SE_SX_BUSY … #define SE_SPI_BUSY … #define SE_SC_BUSY … #define SE_DB_BUSY … #define SE_CB_BUSY … #define GRBM_SOFT_RESET … #define SOFT_RESET_CP … #define SOFT_RESET_CB … #define SOFT_RESET_RLC … #define SOFT_RESET_DB … #define SOFT_RESET_GDS … #define SOFT_RESET_PA … #define SOFT_RESET_SC … #define SOFT_RESET_BCI … #define SOFT_RESET_SPI … #define SOFT_RESET_SX … #define SOFT_RESET_TC … #define SOFT_RESET_TA … #define SOFT_RESET_VGT … #define SOFT_RESET_IA … #define GRBM_GFX_INDEX … #define INSTANCE_INDEX(x) … #define SH_INDEX(x) … #define SE_INDEX(x) … #define SH_BROADCAST_WRITES … #define INSTANCE_BROADCAST_WRITES … #define SE_BROADCAST_WRITES … #define GRBM_INT_CNTL … #define RDERR_INT_ENABLE … #define GUI_IDLE_INT_ENABLE … #define CP_STRMOUT_CNTL … #define SCRATCH_REG0 … #define SCRATCH_REG1 … #define SCRATCH_REG2 … #define SCRATCH_REG3 … #define SCRATCH_REG4 … #define SCRATCH_REG5 … #define SCRATCH_REG6 … #define SCRATCH_REG7 … #define SCRATCH_UMSK … #define SCRATCH_ADDR … #define CP_SEM_WAIT_TIMER … #define CP_SEM_INCOMPLETE_TIMER_CNTL … #define CP_ME_CNTL … #define CP_CE_HALT … #define CP_PFP_HALT … #define CP_ME_HALT … #define CP_COHER_CNTL2 … #define CP_RB2_RPTR … #define CP_RB1_RPTR … #define CP_RB0_RPTR … #define CP_RB_WPTR_DELAY … #define CP_QUEUE_THRESHOLDS … #define ROQ_IB1_START(x) … #define ROQ_IB2_START(x) … #define CP_MEQ_THRESHOLDS … #define MEQ1_START(x) … #define MEQ2_START(x) … #define CP_PERFMON_CNTL … #define VGT_VTX_VECT_EJECT_REG … #define VGT_CACHE_INVALIDATION … #define CACHE_INVALIDATION(x) … #define VC_ONLY … #define TC_ONLY … #define VC_AND_TC … #define AUTO_INVLD_EN(x) … #define NO_AUTO … #define ES_AUTO … #define GS_AUTO … #define ES_AND_GS_AUTO … #define VGT_ESGS_RING_SIZE … #define VGT_GSVS_RING_SIZE … #define VGT_GS_VERTEX_REUSE … #define VGT_PRIMITIVE_TYPE … #define VGT_INDEX_TYPE … #define VGT_NUM_INDICES … #define VGT_NUM_INSTANCES … #define VGT_TF_RING_SIZE … #define VGT_HS_OFFCHIP_PARAM … #define VGT_TF_MEMORY_BASE … #define CC_GC_SHADER_ARRAY_CONFIG … #define INACTIVE_CUS_MASK … #define INACTIVE_CUS_SHIFT … #define GC_USER_SHADER_ARRAY_CONFIG … #define PA_CL_ENHANCE … #define CLIP_VTX_REORDER_ENA … #define NUM_CLIP_SEQ(x) … #define PA_SU_LINE_STIPPLE_VALUE … #define PA_SC_LINE_STIPPLE_STATE … #define PA_SC_FORCE_EOV_MAX_CNTS … #define FORCE_EOV_MAX_CLK_CNT(x) … #define FORCE_EOV_MAX_REZ_CNT(x) … #define PA_SC_FIFO_SIZE … #define SC_FRONTEND_PRIM_FIFO_SIZE(x) … #define SC_BACKEND_PRIM_FIFO_SIZE(x) … #define SC_HIZ_TILE_FIFO_SIZE(x) … #define SC_EARLYZ_TILE_FIFO_SIZE(x) … #define PA_SC_ENHANCE … #define SQ_CONFIG … #define SQC_CACHES … #define SQ_POWER_THROTTLE … #define MIN_POWER(x) … #define MIN_POWER_MASK … #define MIN_POWER_SHIFT … #define MAX_POWER(x) … #define MAX_POWER_MASK … #define MAX_POWER_SHIFT … #define SQ_POWER_THROTTLE2 … #define MAX_POWER_DELTA(x) … #define MAX_POWER_DELTA_MASK … #define MAX_POWER_DELTA_SHIFT … #define STI_SIZE(x) … #define STI_SIZE_MASK … #define STI_SIZE_SHIFT … #define LTI_RATIO(x) … #define LTI_RATIO_MASK … #define LTI_RATIO_SHIFT … #define SX_DEBUG_1 … #define SPI_STATIC_THREAD_MGMT_1 … #define SPI_STATIC_THREAD_MGMT_2 … #define SPI_STATIC_THREAD_MGMT_3 … #define SPI_PS_MAX_WAVE_ID … #define SPI_CONFIG_CNTL … #define SPI_CONFIG_CNTL_1 … #define VTX_DONE_DELAY(x) … #define INTERP_ONE_PRIM_PER_ROW … #define CGTS_TCC_DISABLE … #define CGTS_USER_TCC_DISABLE … #define TCC_DISABLE_MASK … #define TCC_DISABLE_SHIFT … #define CGTS_SM_CTRL_REG … #define OVERRIDE … #define LS_OVERRIDE … #define SPI_LB_CU_MASK … #define TA_CNTL_AUX … #define CC_RB_BACKEND_DISABLE … #define BACKEND_DISABLE(x) … #define GB_ADDR_CONFIG … #define NUM_PIPES(x) … #define NUM_PIPES_MASK … #define NUM_PIPES_SHIFT … #define PIPE_INTERLEAVE_SIZE(x) … #define PIPE_INTERLEAVE_SIZE_MASK … #define PIPE_INTERLEAVE_SIZE_SHIFT … #define NUM_SHADER_ENGINES(x) … #define NUM_SHADER_ENGINES_MASK … #define NUM_SHADER_ENGINES_SHIFT … #define SHADER_ENGINE_TILE_SIZE(x) … #define SHADER_ENGINE_TILE_SIZE_MASK … #define SHADER_ENGINE_TILE_SIZE_SHIFT … #define NUM_GPUS(x) … #define NUM_GPUS_MASK … #define NUM_GPUS_SHIFT … #define MULTI_GPU_TILE_SIZE(x) … #define MULTI_GPU_TILE_SIZE_MASK … #define MULTI_GPU_TILE_SIZE_SHIFT … #define ROW_SIZE(x) … #define ROW_SIZE_MASK … #define ROW_SIZE_SHIFT … #define GB_TILE_MODE0 … #define MICRO_TILE_MODE(x) … #define ADDR_SURF_DISPLAY_MICRO_TILING … #define ADDR_SURF_THIN_MICRO_TILING … #define ADDR_SURF_DEPTH_MICRO_TILING … #define ARRAY_MODE(x) … #define ARRAY_LINEAR_GENERAL … #define ARRAY_LINEAR_ALIGNED … #define ARRAY_1D_TILED_THIN1 … #define ARRAY_2D_TILED_THIN1 … #define PIPE_CONFIG(x) … #define ADDR_SURF_P2 … #define ADDR_SURF_P4_8x16 … #define ADDR_SURF_P4_16x16 … #define ADDR_SURF_P4_16x32 … #define ADDR_SURF_P4_32x32 … #define ADDR_SURF_P8_16x16_8x16 … #define ADDR_SURF_P8_16x32_8x16 … #define ADDR_SURF_P8_32x32_8x16 … #define ADDR_SURF_P8_16x32_16x16 … #define ADDR_SURF_P8_32x32_16x16 … #define ADDR_SURF_P8_32x32_16x32 … #define ADDR_SURF_P8_32x64_32x32 … #define TILE_SPLIT(x) … #define ADDR_SURF_TILE_SPLIT_64B … #define ADDR_SURF_TILE_SPLIT_128B … #define ADDR_SURF_TILE_SPLIT_256B … #define ADDR_SURF_TILE_SPLIT_512B … #define ADDR_SURF_TILE_SPLIT_1KB … #define ADDR_SURF_TILE_SPLIT_2KB … #define ADDR_SURF_TILE_SPLIT_4KB … #define BANK_WIDTH(x) … #define ADDR_SURF_BANK_WIDTH_1 … #define ADDR_SURF_BANK_WIDTH_2 … #define ADDR_SURF_BANK_WIDTH_4 … #define ADDR_SURF_BANK_WIDTH_8 … #define BANK_HEIGHT(x) … #define ADDR_SURF_BANK_HEIGHT_1 … #define ADDR_SURF_BANK_HEIGHT_2 … #define ADDR_SURF_BANK_HEIGHT_4 … #define ADDR_SURF_BANK_HEIGHT_8 … #define MACRO_TILE_ASPECT(x) … #define ADDR_SURF_MACRO_ASPECT_1 … #define ADDR_SURF_MACRO_ASPECT_2 … #define ADDR_SURF_MACRO_ASPECT_4 … #define ADDR_SURF_MACRO_ASPECT_8 … #define NUM_BANKS(x) … #define ADDR_SURF_2_BANK … #define ADDR_SURF_4_BANK … #define ADDR_SURF_8_BANK … #define ADDR_SURF_16_BANK … #define GB_TILE_MODE1 … #define GB_TILE_MODE2 … #define GB_TILE_MODE3 … #define GB_TILE_MODE4 … #define GB_TILE_MODE5 … #define GB_TILE_MODE6 … #define GB_TILE_MODE7 … #define GB_TILE_MODE8 … #define GB_TILE_MODE9 … #define GB_TILE_MODE10 … #define GB_TILE_MODE11 … #define GB_TILE_MODE12 … #define GB_TILE_MODE13 … #define GB_TILE_MODE14 … #define GB_TILE_MODE15 … #define GB_TILE_MODE16 … #define GB_TILE_MODE17 … #define GB_TILE_MODE18 … #define GB_TILE_MODE19 … #define GB_TILE_MODE20 … #define GB_TILE_MODE21 … #define GB_TILE_MODE22 … #define GB_TILE_MODE23 … #define GB_TILE_MODE24 … #define GB_TILE_MODE25 … #define GB_TILE_MODE26 … #define GB_TILE_MODE27 … #define GB_TILE_MODE28 … #define GB_TILE_MODE29 … #define GB_TILE_MODE30 … #define GB_TILE_MODE31 … #define CB_PERFCOUNTER0_SELECT0 … #define CB_PERFCOUNTER0_SELECT1 … #define CB_PERFCOUNTER1_SELECT0 … #define CB_PERFCOUNTER1_SELECT1 … #define CB_PERFCOUNTER2_SELECT0 … #define CB_PERFCOUNTER2_SELECT1 … #define CB_PERFCOUNTER3_SELECT0 … #define CB_PERFCOUNTER3_SELECT1 … #define CB_CGTT_SCLK_CTRL … #define GC_USER_RB_BACKEND_DISABLE … #define BACKEND_DISABLE_MASK … #define BACKEND_DISABLE_SHIFT … #define TCP_CHAN_STEER_LO … #define TCP_CHAN_STEER_HI … #define CP_RB0_BASE … #define CP_RB0_CNTL … #define RB_BUFSZ(x) … #define RB_BLKSZ(x) … #define BUF_SWAP_32BIT … #define RB_NO_UPDATE … #define RB_RPTR_WR_ENA … #define CP_RB0_RPTR_ADDR … #define CP_RB0_RPTR_ADDR_HI … #define CP_RB0_WPTR … #define CP_PFP_UCODE_ADDR … #define CP_PFP_UCODE_DATA … #define CP_ME_RAM_RADDR … #define CP_ME_RAM_WADDR … #define CP_ME_RAM_DATA … #define CP_CE_UCODE_ADDR … #define CP_CE_UCODE_DATA … #define CP_RB1_BASE … #define CP_RB1_CNTL … #define CP_RB1_RPTR_ADDR … #define CP_RB1_RPTR_ADDR_HI … #define CP_RB1_WPTR … #define CP_RB2_BASE … #define CP_RB2_CNTL … #define CP_RB2_RPTR_ADDR … #define CP_RB2_RPTR_ADDR_HI … #define CP_RB2_WPTR … #define CP_INT_CNTL_RING0 … #define CP_INT_CNTL_RING1 … #define CP_INT_CNTL_RING2 … #define CNTX_BUSY_INT_ENABLE … #define CNTX_EMPTY_INT_ENABLE … #define WAIT_MEM_SEM_INT_ENABLE … #define TIME_STAMP_INT_ENABLE … #define CP_RINGID2_INT_ENABLE … #define CP_RINGID1_INT_ENABLE … #define CP_RINGID0_INT_ENABLE … #define CP_INT_STATUS_RING0 … #define CP_INT_STATUS_RING1 … #define CP_INT_STATUS_RING2 … #define WAIT_MEM_SEM_INT_STAT … #define TIME_STAMP_INT_STAT … #define CP_RINGID2_INT_STAT … #define CP_RINGID1_INT_STAT … #define CP_RINGID0_INT_STAT … #define CP_MEM_SLP_CNTL … #define CP_MEM_LS_EN … #define CP_DEBUG … #define RLC_CNTL … #define RLC_ENABLE … #define RLC_RL_BASE … #define RLC_RL_SIZE … #define RLC_LB_CNTL … #define LOAD_BALANCE_ENABLE … #define RLC_SAVE_AND_RESTORE_BASE … #define RLC_LB_CNTR_MAX … #define RLC_LB_CNTR_INIT … #define RLC_CLEAR_STATE_RESTORE_BASE … #define RLC_UCODE_ADDR … #define RLC_UCODE_DATA … #define RLC_GPU_CLOCK_COUNT_LSB … #define RLC_GPU_CLOCK_COUNT_MSB … #define RLC_CAPTURE_GPU_CLOCK_COUNT … #define RLC_MC_CNTL … #define RLC_UCODE_CNTL … #define RLC_STAT … #define RLC_BUSY_STATUS … #define GFX_POWER_STATUS … #define GFX_CLOCK_STATUS … #define GFX_LS_STATUS … #define RLC_PG_CNTL … #define GFX_PG_ENABLE … #define GFX_PG_SRC … #define RLC_CGTT_MGCG_OVERRIDE … #define RLC_CGCG_CGLS_CTRL … #define CGCG_EN … #define CGLS_EN … #define RLC_TTOP_D … #define RLC_PUD(x) … #define RLC_PUD_MASK … #define RLC_PDD(x) … #define RLC_PDD_MASK … #define RLC_TTPD(x) … #define RLC_TTPD_MASK … #define RLC_MSD(x) … #define RLC_MSD_MASK … #define RLC_LB_INIT_CU_MASK … #define RLC_PG_AO_CU_MASK … #define RLC_MAX_PG_CU … #define MAX_PU_CU(x) … #define MAX_PU_CU_MASK … #define RLC_AUTO_PG_CTRL … #define AUTO_PG_EN … #define GRBM_REG_SGIT(x) … #define GRBM_REG_SGIT_MASK … #define PG_AFTER_GRBM_REG_ST(x) … #define PG_AFTER_GRBM_REG_ST_MASK … #define RLC_SERDES_WR_MASTER_MASK_0 … #define RLC_SERDES_WR_MASTER_MASK_1 … #define RLC_SERDES_WR_CTRL … #define RLC_SERDES_MASTER_BUSY_0 … #define RLC_SERDES_MASTER_BUSY_1 … #define RLC_GCPM_GENERAL_3 … #define DB_RENDER_CONTROL … #define DB_DEPTH_INFO … #define PA_SC_RASTER_CONFIG … #define RB_MAP_PKR0(x) … #define RB_MAP_PKR0_MASK … #define RB_MAP_PKR1(x) … #define RB_MAP_PKR1_MASK … #define RASTER_CONFIG_RB_MAP_0 … #define RASTER_CONFIG_RB_MAP_1 … #define RASTER_CONFIG_RB_MAP_2 … #define RASTER_CONFIG_RB_MAP_3 … #define RB_XSEL2(x) … #define RB_XSEL2_MASK … #define RB_XSEL … #define RB_YSEL … #define PKR_MAP(x) … #define PKR_MAP_MASK … #define RASTER_CONFIG_PKR_MAP_0 … #define RASTER_CONFIG_PKR_MAP_1 … #define RASTER_CONFIG_PKR_MAP_2 … #define RASTER_CONFIG_PKR_MAP_3 … #define PKR_XSEL(x) … #define PKR_XSEL_MASK … #define PKR_YSEL(x) … #define PKR_YSEL_MASK … #define SC_MAP(x) … #define SC_MAP_MASK … #define SC_XSEL(x) … #define SC_XSEL_MASK … #define SC_YSEL(x) … #define SC_YSEL_MASK … #define SE_MAP(x) … #define SE_MAP_MASK … #define RASTER_CONFIG_SE_MAP_0 … #define RASTER_CONFIG_SE_MAP_1 … #define RASTER_CONFIG_SE_MAP_2 … #define RASTER_CONFIG_SE_MAP_3 … #define SE_XSEL(x) … #define SE_XSEL_MASK … #define SE_YSEL(x) … #define SE_YSEL_MASK … #define VGT_EVENT_INITIATOR … #define SAMPLE_STREAMOUTSTATS1 … #define SAMPLE_STREAMOUTSTATS2 … #define SAMPLE_STREAMOUTSTATS3 … #define CACHE_FLUSH_TS … #define CACHE_FLUSH … #define CS_PARTIAL_FLUSH … #define VGT_STREAMOUT_RESET … #define END_OF_PIPE_INCR_DE … #define END_OF_PIPE_IB_END … #define RST_PIX_CNT … #define VS_PARTIAL_FLUSH … #define PS_PARTIAL_FLUSH … #define CACHE_FLUSH_AND_INV_TS_EVENT … #define ZPASS_DONE … #define CACHE_FLUSH_AND_INV_EVENT … #define PERFCOUNTER_START … #define PERFCOUNTER_STOP … #define PIPELINESTAT_START … #define PIPELINESTAT_STOP … #define PERFCOUNTER_SAMPLE … #define SAMPLE_PIPELINESTAT … #define SAMPLE_STREAMOUTSTATS … #define RESET_VTX_CNT … #define VGT_FLUSH … #define BOTTOM_OF_PIPE_TS … #define DB_CACHE_FLUSH_AND_INV … #define FLUSH_AND_INV_DB_DATA_TS … #define FLUSH_AND_INV_DB_META … #define FLUSH_AND_INV_CB_DATA_TS … #define FLUSH_AND_INV_CB_META … #define CS_DONE … #define PS_DONE … #define FLUSH_AND_INV_CB_PIXEL_DATA … #define THREAD_TRACE_START … #define THREAD_TRACE_STOP … #define THREAD_TRACE_FLUSH … #define THREAD_TRACE_FINISH … /* PIF PHY0 registers idx/data 0x8/0xc */ #define PB0_PIF_CNTL … #define LS2_EXIT_TIME(x) … #define LS2_EXIT_TIME_MASK … #define LS2_EXIT_TIME_SHIFT … #define PB0_PIF_PAIRING … #define MULTI_PIF … #define PB0_PIF_PWRDOWN_0 … #define PLL_POWER_STATE_IN_TXS2_0(x) … #define PLL_POWER_STATE_IN_TXS2_0_MASK … #define PLL_POWER_STATE_IN_TXS2_0_SHIFT … #define PLL_POWER_STATE_IN_OFF_0(x) … #define PLL_POWER_STATE_IN_OFF_0_MASK … #define PLL_POWER_STATE_IN_OFF_0_SHIFT … #define PLL_RAMP_UP_TIME_0(x) … #define PLL_RAMP_UP_TIME_0_MASK … #define PLL_RAMP_UP_TIME_0_SHIFT … #define PB0_PIF_PWRDOWN_1 … #define PLL_POWER_STATE_IN_TXS2_1(x) … #define PLL_POWER_STATE_IN_TXS2_1_MASK … #define PLL_POWER_STATE_IN_TXS2_1_SHIFT … #define PLL_POWER_STATE_IN_OFF_1(x) … #define PLL_POWER_STATE_IN_OFF_1_MASK … #define PLL_POWER_STATE_IN_OFF_1_SHIFT … #define PLL_RAMP_UP_TIME_1(x) … #define PLL_RAMP_UP_TIME_1_MASK … #define PLL_RAMP_UP_TIME_1_SHIFT … #define PB0_PIF_PWRDOWN_2 … #define PLL_POWER_STATE_IN_TXS2_2(x) … #define PLL_POWER_STATE_IN_TXS2_2_MASK … #define PLL_POWER_STATE_IN_TXS2_2_SHIFT … #define PLL_POWER_STATE_IN_OFF_2(x) … #define PLL_POWER_STATE_IN_OFF_2_MASK … #define PLL_POWER_STATE_IN_OFF_2_SHIFT … #define PLL_RAMP_UP_TIME_2(x) … #define PLL_RAMP_UP_TIME_2_MASK … #define PLL_RAMP_UP_TIME_2_SHIFT … #define PB0_PIF_PWRDOWN_3 … #define PLL_POWER_STATE_IN_TXS2_3(x) … #define PLL_POWER_STATE_IN_TXS2_3_MASK … #define PLL_POWER_STATE_IN_TXS2_3_SHIFT … #define PLL_POWER_STATE_IN_OFF_3(x) … #define PLL_POWER_STATE_IN_OFF_3_MASK … #define PLL_POWER_STATE_IN_OFF_3_SHIFT … #define PLL_RAMP_UP_TIME_3(x) … #define PLL_RAMP_UP_TIME_3_MASK … #define PLL_RAMP_UP_TIME_3_SHIFT … /* PIF PHY1 registers idx/data 0x10/0x14 */ #define PB1_PIF_CNTL … #define PB1_PIF_PAIRING … #define PB1_PIF_PWRDOWN_0 … #define PB1_PIF_PWRDOWN_1 … #define PB1_PIF_PWRDOWN_2 … #define PB1_PIF_PWRDOWN_3 … /* PCIE registers idx/data 0x30/0x34 */ #define PCIE_CNTL2 … #define SLV_MEM_LS_EN … #define SLV_MEM_AGGRESSIVE_LS_EN … #define MST_MEM_LS_EN … #define REPLAY_MEM_LS_EN … #define PCIE_LC_STATUS1 … #define LC_REVERSE_RCVR … #define LC_REVERSE_XMIT … #define LC_OPERATING_LINK_WIDTH_MASK … #define LC_OPERATING_LINK_WIDTH_SHIFT … #define LC_DETECTED_LINK_WIDTH_MASK … #define LC_DETECTED_LINK_WIDTH_SHIFT … #define PCIE_P_CNTL … #define P_IGNORE_EDB_ERR … /* PCIE PORT registers idx/data 0x38/0x3c */ #define PCIE_LC_CNTL … #define LC_L0S_INACTIVITY(x) … #define LC_L0S_INACTIVITY_MASK … #define LC_L0S_INACTIVITY_SHIFT … #define LC_L1_INACTIVITY(x) … #define LC_L1_INACTIVITY_MASK … #define LC_L1_INACTIVITY_SHIFT … #define LC_PMI_TO_L1_DIS … #define LC_ASPM_TO_L1_DIS … #define PCIE_LC_LINK_WIDTH_CNTL … #define LC_LINK_WIDTH_SHIFT … #define LC_LINK_WIDTH_MASK … #define LC_LINK_WIDTH_X0 … #define LC_LINK_WIDTH_X1 … #define LC_LINK_WIDTH_X2 … #define LC_LINK_WIDTH_X4 … #define LC_LINK_WIDTH_X8 … #define LC_LINK_WIDTH_X16 … #define LC_LINK_WIDTH_RD_SHIFT … #define LC_LINK_WIDTH_RD_MASK … #define LC_RECONFIG_ARC_MISSING_ESCAPE … #define LC_RECONFIG_NOW … #define LC_RENEGOTIATION_SUPPORT … #define LC_RENEGOTIATE_EN … #define LC_SHORT_RECONFIG_EN … #define LC_UPCONFIGURE_SUPPORT … #define LC_UPCONFIGURE_DIS … #define LC_DYN_LANES_PWR_STATE(x) … #define LC_DYN_LANES_PWR_STATE_MASK … #define LC_DYN_LANES_PWR_STATE_SHIFT … #define PCIE_LC_N_FTS_CNTL … #define LC_XMIT_N_FTS(x) … #define LC_XMIT_N_FTS_MASK … #define LC_XMIT_N_FTS_SHIFT … #define LC_XMIT_N_FTS_OVERRIDE_EN … #define LC_N_FTS_MASK … #define PCIE_LC_SPEED_CNTL … #define LC_GEN2_EN_STRAP … #define LC_GEN3_EN_STRAP … #define LC_TARGET_LINK_SPEED_OVERRIDE_EN … #define LC_TARGET_LINK_SPEED_OVERRIDE_MASK … #define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT … #define LC_FORCE_EN_SW_SPEED_CHANGE … #define LC_FORCE_DIS_SW_SPEED_CHANGE … #define LC_FORCE_EN_HW_SPEED_CHANGE … #define LC_FORCE_DIS_HW_SPEED_CHANGE … #define LC_INITIATE_LINK_SPEED_CHANGE … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT … #define LC_CURRENT_DATA_RATE_MASK … #define LC_CURRENT_DATA_RATE_SHIFT … #define LC_CLR_FAILED_SPD_CHANGE_CNT … #define LC_OTHER_SIDE_EVER_SENT_GEN2 … #define LC_OTHER_SIDE_SUPPORTS_GEN2 … #define LC_OTHER_SIDE_EVER_SENT_GEN3 … #define LC_OTHER_SIDE_SUPPORTS_GEN3 … #define PCIE_LC_CNTL2 … #define LC_ALLOW_PDWN_IN_L1 … #define LC_ALLOW_PDWN_IN_L23 … #define PCIE_LC_CNTL3 … #define LC_GO_TO_RECOVERY … #define PCIE_LC_CNTL4 … #define LC_REDO_EQ … #define LC_SET_QUIESCE … /* * UVD */ #define UVD_UDEC_ADDR_CONFIG … #define UVD_UDEC_DB_ADDR_CONFIG … #define UVD_UDEC_DBW_ADDR_CONFIG … #define UVD_RBC_RB_RPTR … #define UVD_RBC_RB_WPTR … #define UVD_STATUS … #define UVD_CGC_CTRL … #define DCM … #define CG_DT(x) … #define CG_DT_MASK … #define CLK_OD(x) … #define CLK_OD_MASK … /* UVD CTX indirect */ #define UVD_CGC_MEM_CTRL … #define UVD_CGC_CTRL2 … #define DYN_OR_EN … #define DYN_RR_EN … #define G_DIV_ID(x) … #define G_DIV_ID_MASK … /* * PM4 */ #define PACKET_TYPE0 … #define PACKET0(reg, n) … #define CP_PACKET2 … #define PACKET2_PAD_SHIFT … #define PACKET2_PAD_MASK … #define PACKET2(v) … #define RADEON_PACKET_TYPE3 … #define PACKET3(op, n) … #define PACKET3_COMPUTE(op, n) … /* Packet 3 types */ #define PACKET3_NOP … #define PACKET3_SET_BASE … #define PACKET3_BASE_INDEX(x) … #define GDS_PARTITION_BASE … #define CE_PARTITION_BASE … #define PACKET3_CLEAR_STATE … #define PACKET3_INDEX_BUFFER_SIZE … #define PACKET3_DISPATCH_DIRECT … #define PACKET3_DISPATCH_INDIRECT … #define PACKET3_ALLOC_GDS … #define PACKET3_WRITE_GDS_RAM … #define PACKET3_ATOMIC_GDS … #define PACKET3_ATOMIC … #define PACKET3_OCCLUSION_QUERY … #define PACKET3_SET_PREDICATION … #define PACKET3_REG_RMW … #define PACKET3_COND_EXEC … #define PACKET3_PRED_EXEC … #define PACKET3_DRAW_INDIRECT … #define PACKET3_DRAW_INDEX_INDIRECT … #define PACKET3_INDEX_BASE … #define PACKET3_DRAW_INDEX_2 … #define PACKET3_CONTEXT_CONTROL … #define PACKET3_INDEX_TYPE … #define PACKET3_DRAW_INDIRECT_MULTI … #define PACKET3_DRAW_INDEX_AUTO … #define PACKET3_DRAW_INDEX_IMMD … #define PACKET3_NUM_INSTANCES … #define PACKET3_DRAW_INDEX_MULTI_AUTO … #define PACKET3_INDIRECT_BUFFER_CONST … #define PACKET3_INDIRECT_BUFFER … #define PACKET3_STRMOUT_BUFFER_UPDATE … #define PACKET3_DRAW_INDEX_OFFSET_2 … #define PACKET3_DRAW_INDEX_MULTI_ELEMENT … #define PACKET3_WRITE_DATA … #define WRITE_DATA_DST_SEL(x) … /* 0 - register * 1 - memory (sync - via GRBM) * 2 - tc/l2 * 3 - gds * 4 - reserved * 5 - memory (async - direct) */ #define WR_ONE_ADDR … #define WR_CONFIRM … #define WRITE_DATA_ENGINE_SEL(x) … /* 0 - me * 1 - pfp * 2 - ce */ #define PACKET3_DRAW_INDEX_INDIRECT_MULTI … #define PACKET3_MEM_SEMAPHORE … #define PACKET3_MPEG_INDEX … #define PACKET3_COPY_DW … #define PACKET3_WAIT_REG_MEM … #define WAIT_REG_MEM_FUNCTION(x) … /* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > */ #define WAIT_REG_MEM_MEM_SPACE(x) … /* 0 - reg * 1 - mem */ #define WAIT_REG_MEM_ENGINE(x) … /* 0 - me * 1 - pfp */ #define PACKET3_MEM_WRITE … #define PACKET3_COPY_DATA … #define PACKET3_CP_DMA … /* 1. header * 2. SRC_ADDR_LO or DATA [31:0] * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | * SRC_ADDR_HI [7:0] * 4. DST_ADDR_LO [31:0] * 5. DST_ADDR_HI [7:0] * 6. COMMAND [30:21] | BYTE_COUNT [20:0] */ #define PACKET3_CP_DMA_DST_SEL(x) … /* 0 - DST_ADDR * 1 - GDS */ #define PACKET3_CP_DMA_ENGINE(x) … /* 0 - ME * 1 - PFP */ #define PACKET3_CP_DMA_SRC_SEL(x) … /* 0 - SRC_ADDR * 1 - GDS * 2 - DATA */ #define PACKET3_CP_DMA_CP_SYNC … /* COMMAND */ #define PACKET3_CP_DMA_DIS_WC … #define PACKET3_CP_DMA_CMD_SRC_SWAP(x) … /* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 */ #define PACKET3_CP_DMA_CMD_DST_SWAP(x) … /* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 */ #define PACKET3_CP_DMA_CMD_SAS … /* 0 - memory * 1 - register */ #define PACKET3_CP_DMA_CMD_DAS … /* 0 - memory * 1 - register */ #define PACKET3_CP_DMA_CMD_SAIC … #define PACKET3_CP_DMA_CMD_DAIC … #define PACKET3_CP_DMA_CMD_RAW_WAIT … #define PACKET3_PFP_SYNC_ME … #define PACKET3_SURFACE_SYNC … #define PACKET3_DEST_BASE_0_ENA … #define PACKET3_DEST_BASE_1_ENA … #define PACKET3_CB0_DEST_BASE_ENA … #define PACKET3_CB1_DEST_BASE_ENA … #define PACKET3_CB2_DEST_BASE_ENA … #define PACKET3_CB3_DEST_BASE_ENA … #define PACKET3_CB4_DEST_BASE_ENA … #define PACKET3_CB5_DEST_BASE_ENA … #define PACKET3_CB6_DEST_BASE_ENA … #define PACKET3_CB7_DEST_BASE_ENA … #define PACKET3_DB_DEST_BASE_ENA … #define PACKET3_DEST_BASE_2_ENA … #define PACKET3_DEST_BASE_3_ENA … #define PACKET3_TCL1_ACTION_ENA … #define PACKET3_TC_ACTION_ENA … #define PACKET3_CB_ACTION_ENA … #define PACKET3_DB_ACTION_ENA … #define PACKET3_SH_KCACHE_ACTION_ENA … #define PACKET3_SH_ICACHE_ACTION_ENA … #define PACKET3_ME_INITIALIZE … #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) … #define PACKET3_COND_WRITE … #define PACKET3_EVENT_WRITE … #define EVENT_TYPE(x) … #define EVENT_INDEX(x) … /* 0 - any non-TS event * 1 - ZPASS_DONE * 2 - SAMPLE_PIPELINESTAT * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH * 5 - EOP events * 6 - EOS events * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT */ #define INV_L2 … /* INV TC L2 cache when EVENT_INDEX = 7 */ #define PACKET3_EVENT_WRITE_EOP … #define DATA_SEL(x) … /* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit counter value */ #define INT_SEL(x) … /* 0 - none * 1 - interrupt only (DATA_SEL = 0) * 2 - interrupt when data write is confirmed */ #define PACKET3_EVENT_WRITE_EOS … #define PACKET3_PREAMBLE_CNTL … #define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE … #define PACKET3_PREAMBLE_END_CLEAR_STATE … #define PACKET3_ONE_REG_WRITE … #define PACKET3_LOAD_CONFIG_REG … #define PACKET3_LOAD_CONTEXT_REG … #define PACKET3_LOAD_SH_REG … #define PACKET3_SET_CONFIG_REG … #define PACKET3_SET_CONFIG_REG_START … #define PACKET3_SET_CONFIG_REG_END … #define PACKET3_SET_CONTEXT_REG … #define PACKET3_SET_CONTEXT_REG_START … #define PACKET3_SET_CONTEXT_REG_END … #define PACKET3_SET_CONTEXT_REG_INDIRECT … #define PACKET3_SET_RESOURCE_INDIRECT … #define PACKET3_SET_SH_REG … #define PACKET3_SET_SH_REG_START … #define PACKET3_SET_SH_REG_END … #define PACKET3_SET_SH_REG_OFFSET … #define PACKET3_ME_WRITE … #define PACKET3_SCRATCH_RAM_WRITE … #define PACKET3_SCRATCH_RAM_READ … #define PACKET3_CE_WRITE … #define PACKET3_LOAD_CONST_RAM … #define PACKET3_WRITE_CONST_RAM … #define PACKET3_WRITE_CONST_RAM_OFFSET … #define PACKET3_DUMP_CONST_RAM … #define PACKET3_INCREMENT_CE_COUNTER … #define PACKET3_INCREMENT_DE_COUNTER … #define PACKET3_WAIT_ON_CE_COUNTER … #define PACKET3_WAIT_ON_DE_COUNTER … #define PACKET3_WAIT_ON_DE_COUNTER_DIFF … #define PACKET3_SET_CE_DE_COUNTERS … #define PACKET3_WAIT_ON_AVAIL_BUFFER … #define PACKET3_SWITCH_BUFFER … /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ #define DMA0_REGISTER_OFFSET … #define DMA1_REGISTER_OFFSET … #define DMA_RB_CNTL … #define DMA_RB_ENABLE … #define DMA_RB_SIZE(x) … #define DMA_RB_SWAP_ENABLE … #define DMA_RPTR_WRITEBACK_ENABLE … #define DMA_RPTR_WRITEBACK_SWAP_ENABLE … #define DMA_RPTR_WRITEBACK_TIMER(x) … #define DMA_RB_BASE … #define DMA_RB_RPTR … #define DMA_RB_WPTR … #define DMA_RB_RPTR_ADDR_HI … #define DMA_RB_RPTR_ADDR_LO … #define DMA_IB_CNTL … #define DMA_IB_ENABLE … #define DMA_IB_SWAP_ENABLE … #define CMD_VMID_FORCE … #define DMA_IB_RPTR … #define DMA_CNTL … #define TRAP_ENABLE … #define SEM_INCOMPLETE_INT_ENABLE … #define SEM_WAIT_INT_ENABLE … #define DATA_SWAP_ENABLE … #define FENCE_SWAP_ENABLE … #define CTXEMPTY_INT_ENABLE … #define DMA_STATUS_REG … #define DMA_IDLE … #define DMA_TILING_CONFIG … #define DMA_POWER_CNTL … #define MEM_POWER_OVERRIDE … #define DMA_CLK_CTRL … #define DMA_PG … #define PG_CNTL_ENABLE … #define DMA_PGFSM_CONFIG … #define DMA_PGFSM_WRITE … #define DMA_PACKET(cmd, b, t, s, n) … #define DMA_IB_PACKET(cmd, vmid, n) … #define DMA_PTE_PDE_PACKET(n) … /* async DMA Packet types */ #define DMA_PACKET_WRITE … #define DMA_PACKET_COPY … #define DMA_PACKET_INDIRECT_BUFFER … #define DMA_PACKET_SEMAPHORE … #define DMA_PACKET_FENCE … #define DMA_PACKET_TRAP … #define DMA_PACKET_SRBM_WRITE … #define DMA_PACKET_CONSTANT_FILL … #define DMA_PACKET_POLL_REG_MEM … #define DMA_PACKET_NOP … #define VCE_STATUS … #define VCE_VCPU_CNTL … #define VCE_CLK_EN … #define VCE_VCPU_CACHE_OFFSET0 … #define VCE_VCPU_CACHE_SIZE0 … #define VCE_VCPU_CACHE_OFFSET1 … #define VCE_VCPU_CACHE_SIZE1 … #define VCE_VCPU_CACHE_OFFSET2 … #define VCE_VCPU_CACHE_SIZE2 … #define VCE_SOFT_RESET … #define VCE_ECPU_SOFT_RESET … #define VCE_FME_SOFT_RESET … #define VCE_RB_BASE_LO2 … #define VCE_RB_BASE_HI2 … #define VCE_RB_SIZE2 … #define VCE_RB_RPTR2 … #define VCE_RB_WPTR2 … #define VCE_RB_BASE_LO … #define VCE_RB_BASE_HI … #define VCE_RB_SIZE … #define VCE_RB_RPTR … #define VCE_RB_WPTR … #define VCE_CLOCK_GATING_A … #define VCE_CLOCK_GATING_B … #define VCE_UENC_CLOCK_GATING … #define VCE_UENC_REG_CLOCK_GATING … #define VCE_FW_REG_STATUS … #define VCE_FW_REG_STATUS_BUSY … #define VCE_FW_REG_STATUS_PASS … #define VCE_FW_REG_STATUS_DONE … #define VCE_LMI_FW_START_KEYSEL … #define VCE_LMI_FW_PERIODIC_CTRL … #define VCE_LMI_CTRL2 … #define VCE_LMI_CTRL … #define VCE_LMI_VM_CTRL … #define VCE_LMI_SWAP_CNTL … #define VCE_LMI_SWAP_CNTL1 … #define VCE_LMI_CACHE_CTRL … #define VCE_CMD_NO_OP … #define VCE_CMD_END … #define VCE_CMD_IB … #define VCE_CMD_FENCE … #define VCE_CMD_TRAP … #define VCE_CMD_IB_AUTO … #define VCE_CMD_SEMAPHORE … //#dce stupp /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ #define SI_CRTC0_REGISTER_OFFSET … #define SI_CRTC1_REGISTER_OFFSET … #define SI_CRTC2_REGISTER_OFFSET … #define SI_CRTC3_REGISTER_OFFSET … #define SI_CRTC4_REGISTER_OFFSET … #define SI_CRTC5_REGISTER_OFFSET … #define CURSOR_WIDTH … #define CURSOR_HEIGHT … #define AMDGPU_MM_INDEX … #define AMDGPU_MM_DATA … #define VERDE_NUM_CRTC … #define BLACKOUT_MODE_MASK … #define VGA_RENDER_CONTROL … #define R_000300_VGA_RENDER_CONTROL … #define C_000300_VGA_VSTATUS_CNTL … #define EVERGREEN_CRTC_STATUS … #define EVERGREEN_CRTC_V_BLANK … #define EVERGREEN_CRTC_STATUS_POSITION … /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ #define EVERGREEN_CRTC_V_BLANK_START_END … #define EVERGREEN_CRTC_CONTROL … #define EVERGREEN_CRTC_MASTER_EN … #define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE … #define EVERGREEN_CRTC_BLANK_CONTROL … #define EVERGREEN_CRTC_BLANK_DATA_EN … #define EVERGREEN_CRTC_V_BLANK … #define EVERGREEN_CRTC_STATUS_HV_COUNT … #define EVERGREEN_CRTC_UPDATE_LOCK … #define EVERGREEN_MASTER_UPDATE_LOCK … #define EVERGREEN_MASTER_UPDATE_MODE … #define EVERGREEN_GRPH_UPDATE_LOCK … #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS … #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS … #define EVERGREEN_GRPH_UPDATE … #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS … #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH … #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING … #define EVERGREEN_DATA_FORMAT … #define EVERGREEN_INTERLEAVE_EN … #define MC_SHARED_CHMAP__NOOFCHAN_MASK … #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT … #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL … #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED … #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 … #define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 … #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK … #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK … #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK … #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK … #define R600_D1GRPH_SWAP_CONTROL … #define R600_D1GRPH_SWAP_ENDIAN_NONE … #define R600_D1GRPH_SWAP_ENDIAN_16BIT … #define R600_D1GRPH_SWAP_ENDIAN_32BIT … #define R600_D1GRPH_SWAP_ENDIAN_64BIT … #define AVIVO_D1VGA_CONTROL … #define AVIVO_DVGA_CONTROL_MODE_ENABLE … #define AVIVO_DVGA_CONTROL_TIMING_SELECT … #define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT … #define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT … #define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN … #define AVIVO_DVGA_CONTROL_ROTATE … #define AVIVO_D2VGA_CONTROL … #define R600_BUS_CNTL … #define R600_BIOS_ROM_DIS … #define R600_ROM_CNTL … #define R600_SCK_OVERWRITE … #define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT … #define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK … #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK … #define FMT_BIT_DEPTH_CONTROL … #define FMT_TRUNCATE_EN … #define FMT_TRUNCATE_DEPTH … #define FMT_SPATIAL_DITHER_EN … #define FMT_SPATIAL_DITHER_MODE(x) … #define FMT_SPATIAL_DITHER_DEPTH … #define FMT_FRAME_RANDOM_ENABLE … #define FMT_RGB_RANDOM_ENABLE … #define FMT_HIGHPASS_RANDOM_ENABLE … #define FMT_TEMPORAL_DITHER_EN … #define FMT_TEMPORAL_DITHER_DEPTH … #define FMT_TEMPORAL_DITHER_OFFSET(x) … #define FMT_TEMPORAL_LEVEL … #define FMT_TEMPORAL_DITHER_RESET … #define FMT_25FRC_SEL(x) … #define FMT_50FRC_SEL(x) … #define FMT_75FRC_SEL(x) … #define EVERGREEN_DC_LUT_CONTROL … #define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE … #define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN … #define EVERGREEN_DC_LUT_BLACK_OFFSET_RED … #define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE … #define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN … #define EVERGREEN_DC_LUT_WHITE_OFFSET_RED … #define EVERGREEN_DC_LUT_30_COLOR … #define EVERGREEN_DC_LUT_RW_INDEX … #define EVERGREEN_DC_LUT_WRITE_EN_MASK … #define EVERGREEN_DC_LUT_RW_MODE … #define EVERGREEN_GRPH_ENABLE … #define EVERGREEN_GRPH_CONTROL … #define EVERGREEN_GRPH_DEPTH(x) … #define EVERGREEN_GRPH_DEPTH_8BPP … #define EVERGREEN_GRPH_DEPTH_16BPP … #define EVERGREEN_GRPH_DEPTH_32BPP … #define EVERGREEN_GRPH_NUM_BANKS(x) … #define EVERGREEN_ADDR_SURF_2_BANK … #define EVERGREEN_ADDR_SURF_4_BANK … #define EVERGREEN_ADDR_SURF_8_BANK … #define EVERGREEN_ADDR_SURF_16_BANK … #define EVERGREEN_GRPH_Z(x) … #define EVERGREEN_GRPH_BANK_WIDTH(x) … #define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 … #define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 … #define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 … #define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 … #define EVERGREEN_GRPH_FORMAT(x) … #define EVERGREEN_GRPH_FORMAT_INDEXED … #define EVERGREEN_GRPH_FORMAT_ARGB1555 … #define EVERGREEN_GRPH_FORMAT_ARGB565 … #define EVERGREEN_GRPH_FORMAT_ARGB4444 … #define EVERGREEN_GRPH_FORMAT_AI88 … #define EVERGREEN_GRPH_FORMAT_MONO16 … #define EVERGREEN_GRPH_FORMAT_BGRA5551 … /* 32 BPP */ #define EVERGREEN_GRPH_FORMAT_ARGB8888 … #define EVERGREEN_GRPH_FORMAT_ARGB2101010 … #define EVERGREEN_GRPH_FORMAT_32BPP_DIG … #define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 … #define EVERGREEN_GRPH_FORMAT_BGRA1010102 … #define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 … #define EVERGREEN_GRPH_FORMAT_RGB111110 … #define EVERGREEN_GRPH_FORMAT_BGR101111 … #define EVERGREEN_GRPH_BANK_HEIGHT(x) … #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 … #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 … #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 … #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 … #define EVERGREEN_GRPH_TILE_SPLIT(x) … #define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B … #define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B … #define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B … #define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B … #define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB … #define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB … #define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB … #define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) … #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 … #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 … #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 … #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 … #define EVERGREEN_GRPH_ARRAY_MODE(x) … #define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL … #define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED … #define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 … #define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 … #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 … #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 … #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 … #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 … #define EVERGREEN_GRPH_SWAP_CONTROL … #define EVERGREEN_GRPH_ENDIAN_SWAP(x) … #define EVERGREEN_GRPH_ENDIAN_NONE … #define EVERGREEN_GRPH_ENDIAN_8IN16 … #define EVERGREEN_GRPH_ENDIAN_8IN32 … #define EVERGREEN_GRPH_ENDIAN_8IN64 … #define EVERGREEN_GRPH_RED_CROSSBAR(x) … #define EVERGREEN_GRPH_RED_SEL_R … #define EVERGREEN_GRPH_RED_SEL_G … #define EVERGREEN_GRPH_RED_SEL_B … #define EVERGREEN_GRPH_RED_SEL_A … #define EVERGREEN_GRPH_GREEN_CROSSBAR(x) … #define EVERGREEN_GRPH_GREEN_SEL_G … #define EVERGREEN_GRPH_GREEN_SEL_B … #define EVERGREEN_GRPH_GREEN_SEL_A … #define EVERGREEN_GRPH_GREEN_SEL_R … #define EVERGREEN_GRPH_BLUE_CROSSBAR(x) … #define EVERGREEN_GRPH_BLUE_SEL_B … #define EVERGREEN_GRPH_BLUE_SEL_A … #define EVERGREEN_GRPH_BLUE_SEL_R … #define EVERGREEN_GRPH_BLUE_SEL_G … #define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) … #define EVERGREEN_GRPH_ALPHA_SEL_A … #define EVERGREEN_GRPH_ALPHA_SEL_R … #define EVERGREEN_GRPH_ALPHA_SEL_G … #define EVERGREEN_GRPH_ALPHA_SEL_B … #define EVERGREEN_D3VGA_CONTROL … #define EVERGREEN_D4VGA_CONTROL … #define EVERGREEN_D5VGA_CONTROL … #define EVERGREEN_D6VGA_CONTROL … #define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK … #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL … #define EVERGREEN_LUT_10BIT_BYPASS_EN … #define EVERGREEN_GRPH_PITCH … #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define EVERGREEN_GRPH_SURFACE_OFFSET_X … #define EVERGREEN_GRPH_SURFACE_OFFSET_Y … #define EVERGREEN_GRPH_X_START … #define EVERGREEN_GRPH_Y_START … #define EVERGREEN_GRPH_X_END … #define EVERGREEN_GRPH_Y_END … #define EVERGREEN_GRPH_UPDATE … #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING … #define EVERGREEN_GRPH_UPDATE_LOCK … #define EVERGREEN_GRPH_FLIP_CONTROL … #define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN … #define EVERGREEN_VIEWPORT_START … #define EVERGREEN_VIEWPORT_SIZE … #define EVERGREEN_DESKTOP_HEIGHT … /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ #define EVERGREEN_CUR_CONTROL … #define EVERGREEN_CURSOR_EN … #define EVERGREEN_CURSOR_MODE(x) … #define EVERGREEN_CURSOR_MONO … #define EVERGREEN_CURSOR_24_1 … #define EVERGREEN_CURSOR_24_8_PRE_MULT … #define EVERGREEN_CURSOR_24_8_UNPRE_MULT … #define EVERGREEN_CURSOR_2X_MAGNIFY … #define EVERGREEN_CURSOR_FORCE_MC_ON … #define EVERGREEN_CURSOR_URGENT_CONTROL(x) … #define EVERGREEN_CURSOR_URGENT_ALWAYS … #define EVERGREEN_CURSOR_URGENT_1_8 … #define EVERGREEN_CURSOR_URGENT_1_4 … #define EVERGREEN_CURSOR_URGENT_3_8 … #define EVERGREEN_CURSOR_URGENT_1_2 … #define EVERGREEN_CUR_SURFACE_ADDRESS … #define EVERGREEN_CUR_SURFACE_ADDRESS_MASK … #define EVERGREEN_CUR_SIZE … #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH … #define EVERGREEN_CUR_POSITION … #define EVERGREEN_CUR_HOT_SPOT … #define EVERGREEN_CUR_COLOR1 … #define EVERGREEN_CUR_COLOR2 … #define EVERGREEN_CUR_UPDATE … #define EVERGREEN_CURSOR_UPDATE_PENDING … #define EVERGREEN_CURSOR_UPDATE_TAKEN … #define EVERGREEN_CURSOR_UPDATE_LOCK … #define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE … #define NI_INPUT_CSC_CONTROL … #define NI_INPUT_CSC_GRPH_MODE(x) … #define NI_INPUT_CSC_BYPASS … #define NI_INPUT_CSC_PROG_COEFF … #define NI_INPUT_CSC_PROG_SHARED_MATRIXA … #define NI_INPUT_CSC_OVL_MODE(x) … #define NI_OUTPUT_CSC_CONTROL … #define NI_OUTPUT_CSC_GRPH_MODE(x) … #define NI_OUTPUT_CSC_BYPASS … #define NI_OUTPUT_CSC_TV_RGB … #define NI_OUTPUT_CSC_YCBCR_601 … #define NI_OUTPUT_CSC_YCBCR_709 … #define NI_OUTPUT_CSC_PROG_COEFF … #define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB … #define NI_OUTPUT_CSC_OVL_MODE(x) … #define NI_DEGAMMA_CONTROL … #define NI_GRPH_DEGAMMA_MODE(x) … #define NI_DEGAMMA_BYPASS … #define NI_DEGAMMA_SRGB_24 … #define NI_DEGAMMA_XVYCC_222 … #define NI_OVL_DEGAMMA_MODE(x) … #define NI_ICON_DEGAMMA_MODE(x) … #define NI_CURSOR_DEGAMMA_MODE(x) … #define NI_GAMUT_REMAP_CONTROL … #define NI_GRPH_GAMUT_REMAP_MODE(x) … #define NI_GAMUT_REMAP_BYPASS … #define NI_GAMUT_REMAP_PROG_COEFF … #define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA … #define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB … #define NI_OVL_GAMUT_REMAP_MODE(x) … #define NI_REGAMMA_CONTROL … #define NI_GRPH_REGAMMA_MODE(x) … #define NI_REGAMMA_BYPASS … #define NI_REGAMMA_SRGB_24 … #define NI_REGAMMA_XVYCC_222 … #define NI_REGAMMA_PROG_A … #define NI_REGAMMA_PROG_B … #define NI_OVL_REGAMMA_MODE(x) … #define NI_PRESCALE_GRPH_CONTROL … #define NI_GRPH_PRESCALE_BYPASS … #define NI_PRESCALE_OVL_CONTROL … #define NI_OVL_PRESCALE_BYPASS … #define NI_INPUT_GAMMA_CONTROL … #define NI_GRPH_INPUT_GAMMA_MODE(x) … #define NI_INPUT_GAMMA_USE_LUT … #define NI_INPUT_GAMMA_BYPASS … #define NI_INPUT_GAMMA_SRGB_24 … #define NI_INPUT_GAMMA_XVYCC_222 … #define NI_OVL_INPUT_GAMMA_MODE(x) … #define BLACKOUT_MODE_MASK … #define VGA_RENDER_CONTROL … #define R_000300_VGA_RENDER_CONTROL … #define C_000300_VGA_VSTATUS_CNTL … #define EVERGREEN_CRTC_STATUS … #define EVERGREEN_CRTC_V_BLANK … #define EVERGREEN_CRTC_STATUS_POSITION … /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ #define EVERGREEN_CRTC_V_BLANK_START_END … #define EVERGREEN_CRTC_CONTROL … #define EVERGREEN_CRTC_MASTER_EN … #define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE … #define EVERGREEN_CRTC_BLANK_CONTROL … #define EVERGREEN_CRTC_BLANK_DATA_EN … #define EVERGREEN_CRTC_V_BLANK … #define EVERGREEN_CRTC_STATUS_HV_COUNT … #define EVERGREEN_CRTC_UPDATE_LOCK … #define EVERGREEN_MASTER_UPDATE_LOCK … #define EVERGREEN_MASTER_UPDATE_MODE … #define EVERGREEN_GRPH_UPDATE_LOCK … #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS … #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS … #define EVERGREEN_GRPH_UPDATE … #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS … #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH … #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING … #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT … #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK … #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT … #define mmBIF_FB_EN__xxFB_READ_EN_MASK … #define mmBIF_FB_EN__xxFB_READ_EN__SHIFT … #define mmBIF_FB_EN__xxFB_WRITE_EN_MASK … #define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT … #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK … #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT … #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK … #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT … #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MC_SEQ_MISC0__MT__MASK … #define MC_SEQ_MISC0__MT__GDDR1 … #define MC_SEQ_MISC0__MT__DDR2 … #define MC_SEQ_MISC0__MT__GDDR3 … #define MC_SEQ_MISC0__MT__GDDR4 … #define MC_SEQ_MISC0__MT__GDDR5 … #define MC_SEQ_MISC0__MT__HBM … #define MC_SEQ_MISC0__MT__DDR3 … #define GRBM_STATUS__GUI_ACTIVE_MASK … #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … #define PACKET3_SEM_WAIT_ON_SIGNAL … #define PACKET3_SEM_SEL_SIGNAL … #define PACKET3_SEM_SEL_WAIT … #define CONFIG_CNTL … #define CC_DRM_ID_STRAPS … #define AMDGPU_PCIE_INDEX … #define AMDGPU_PCIE_DATA … #define DMA_SEM_INCOMPLETE_TIMER_CNTL … #define DMA_SEM_WAIT_FAIL_TIMER_CNTL … #define DMA_MODE … #define DMA_RB_RPTR_ADDR_HI … #define DMA_RB_RPTR_ADDR_LO … #define DMA_BUSY_MASK … #define DMA1_BUSY_MASK … #define SDMA_MAX_INSTANCE … #define PCIE_BUS_CLK … #define TCLK … #define PCIE_PORT_INDEX … #define PCIE_PORT_DATA … #define EVERGREEN_PIF_PHY0_INDEX … #define EVERGREEN_PIF_PHY0_DATA … #define EVERGREEN_PIF_PHY1_INDEX … #define EVERGREEN_PIF_PHY1_DATA … #define MC_VM_FB_OFFSET … /* Discrete VCE clocks */ #define CG_VCEPLL_FUNC_CNTL … #define VCEPLL_RESET_MASK … #define VCEPLL_SLEEP_MASK … #define VCEPLL_BYPASS_EN_MASK … #define VCEPLL_CTLREQ_MASK … #define VCEPLL_VCO_MODE_MASK … #define VCEPLL_REF_DIV_MASK … #define VCEPLL_CTLACK_MASK … #define VCEPLL_CTLACK2_MASK … #define CG_VCEPLL_FUNC_CNTL_2 … #define VCEPLL_PDIV_A(x) … #define VCEPLL_PDIV_A_MASK … #define VCEPLL_PDIV_B(x) … #define VCEPLL_PDIV_B_MASK … #define EVCLK_SRC_SEL(x) … #define EVCLK_SRC_SEL_MASK … #define ECCLK_SRC_SEL(x) … #define ECCLK_SRC_SEL_MASK … #define CG_VCEPLL_FUNC_CNTL_3 … #define VCEPLL_FB_DIV(x) … #define VCEPLL_FB_DIV_MASK … #define CG_VCEPLL_FUNC_CNTL_4 … #define CG_VCEPLL_FUNC_CNTL_5 … #define CG_VCEPLL_SPREAD_SPECTRUM … #define VCEPLL_SSEN_MASK … #endif
Codebase Browser
linux