/* * Copyright 2013 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Christian König <[email protected]> */ #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_uvd.h" #include "cikd.h" #include "uvd/uvd_4_2_d.h" #include "uvd/uvd_4_2_sh_mask.h" #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" #include "bif/bif_4_1_d.h" #include "smu/smu_7_0_1_d.h" #include "smu/smu_7_0_1_sh_mask.h" static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v4_2_start(struct amdgpu_device *adev); static void uvd_v4_2_stop(struct amdgpu_device *adev); static int uvd_v4_2_set_clockgating_state(void *handle, enum amd_clockgating_state state); static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, bool sw_mode); /** * uvd_v4_2_ring_get_rptr - get read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware read pointer */ static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * uvd_v4_2_ring_get_wptr - get write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware write pointer */ static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * uvd_v4_2_ring_set_wptr - set write pointer * * @ring: amdgpu_ring pointer * * Commits the write pointer to the hardware */ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) { … } static int uvd_v4_2_early_init(void *handle) { … } static int uvd_v4_2_sw_init(void *handle) { … } static int uvd_v4_2_sw_fini(void *handle) { … } static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, bool enable); /** * uvd_v4_2_hw_init - start and test UVD block * * @handle: handle used to pass amdgpu_device pointer * * Initialize the hardware, boot up the VCPU and do some testing */ static int uvd_v4_2_hw_init(void *handle) { … } /** * uvd_v4_2_hw_fini - stop the hardware block * * @handle: handle used to pass amdgpu_device pointer * * Stop the UVD block, mark ring as not ready any more */ static int uvd_v4_2_hw_fini(void *handle) { … } static int uvd_v4_2_prepare_suspend(void *handle) { … } static int uvd_v4_2_suspend(void *handle) { … } static int uvd_v4_2_resume(void *handle) { … } /** * uvd_v4_2_start - start UVD block * * @adev: amdgpu_device pointer * * Setup and start the UVD block */ static int uvd_v4_2_start(struct amdgpu_device *adev) { … } /** * uvd_v4_2_stop - stop UVD block * * @adev: amdgpu_device pointer * * stop the UVD block */ static void uvd_v4_2_stop(struct amdgpu_device *adev) { … } /** * uvd_v4_2_ring_emit_fence - emit an fence & trap command * * @ring: amdgpu_ring pointer * @addr: address * @seq: sequence number * @flags: fence related flags * * Write a fence and a trap command to the ring. */ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } /** * uvd_v4_2_ring_test_ring - register write test * * @ring: amdgpu_ring pointer * * Test if we can successfully write to the context register */ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) { … } /** * uvd_v4_2_ring_emit_ib - execute indirect buffer * * @ring: amdgpu_ring pointer * @job: iob associated with the indirect buffer * @ib: indirect buffer to execute * @flags: flags associated with the indirect buffer * * Write ring commands to execute the indirect buffer */ static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) { … } /** * uvd_v4_2_mc_resume - memory controller programming * * @adev: amdgpu_device pointer * * Let the UVD memory controller know it's offsets */ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) { … } static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, bool enable) { … } static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, bool sw_mode) { … } static bool uvd_v4_2_is_idle(void *handle) { … } static int uvd_v4_2_wait_for_idle(void *handle) { … } static int uvd_v4_2_soft_reset(void *handle) { … } static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static int uvd_v4_2_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int uvd_v4_2_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static const struct amd_ip_funcs uvd_v4_2_ip_funcs = …; static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = …; static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) { … } static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = …; static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) { … } const struct amdgpu_ip_block_version uvd_v4_2_ip_block = …;
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