linux/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * Authors: Christian König <[email protected]>
 */

#include <linux/firmware.h>

#include "amdgpu.h"
#include "amdgpu_vce.h"
#include "cikd.h"
#include "vce/vce_2_0_d.h"
#include "vce/vce_2_0_sh_mask.h"
#include "smu/smu_7_0_1_d.h"
#include "smu/smu_7_0_1_sh_mask.h"
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"

#define VCE_V2_0_FW_SIZE …
#define VCE_V2_0_STACK_SIZE …
#define VCE_V2_0_DATA_SIZE …
#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK …

static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);

/**
 * vce_v2_0_ring_get_rptr - get read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware read pointer
 */
static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
{ … }

/**
 * vce_v2_0_ring_get_wptr - get write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware write pointer
 */
static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
{ … }

/**
 * vce_v2_0_ring_set_wptr - set write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the write pointer to the hardware
 */
static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
{ … }

static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
{ … }

static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
{ … }

static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
{ … }

static void vce_v2_0_init_cg(struct amdgpu_device *adev)
{ … }

static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
{ … }

static bool vce_v2_0_is_idle(void *handle)
{ … }

static int vce_v2_0_wait_for_idle(void *handle)
{ … }

/**
 * vce_v2_0_start - start VCE block
 *
 * @adev: amdgpu_device pointer
 *
 * Setup and start the VCE block
 */
static int vce_v2_0_start(struct amdgpu_device *adev)
{ … }

static int vce_v2_0_stop(struct amdgpu_device *adev)
{ … }

static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
{ … }

static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
{ … }

static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
								bool sw_cg)
{ … }

static int vce_v2_0_early_init(void *handle)
{ … }

static int vce_v2_0_sw_init(void *handle)
{ … }

static int vce_v2_0_sw_fini(void *handle)
{ … }

static int vce_v2_0_hw_init(void *handle)
{ … }

static int vce_v2_0_hw_fini(void *handle)
{ … }

static int vce_v2_0_suspend(void *handle)
{ … }

static int vce_v2_0_resume(void *handle)
{ … }

static int vce_v2_0_soft_reset(void *handle)
{ … }

static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
					struct amdgpu_irq_src *source,
					unsigned type,
					enum amdgpu_interrupt_state state)
{ … }

static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
				      struct amdgpu_irq_src *source,
				      struct amdgpu_iv_entry *entry)
{ … }

static int vce_v2_0_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{ … }

static int vce_v2_0_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{ … }

static const struct amd_ip_funcs vce_v2_0_ip_funcs = …;

static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = …;

static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
{ … }

static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = …;

static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
{
	adev->vce.irq.num_types = 1;
	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
};

const struct amdgpu_ip_block_version vce_v2_0_ip_block = …;