/* * * Copyright (C) 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef GFX_6_0_SH_MASK_H #define GFX_6_0_SH_MASK_H #define BCI_DEBUG_READ__DATA_MASK … #define BCI_DEBUG_READ__DATA__SHIFT … #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK … #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT … #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK … #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT … #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK … #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT … #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK … #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT … #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK … #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT … #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK … #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT … #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK … #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT … #define CB_BLEND0_CONTROL__ENABLE_MASK … #define CB_BLEND0_CONTROL__ENABLE__SHIFT … #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK … #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT … #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK … #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT … #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK … #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT … #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK … #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT … #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK … #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT … #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK … #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT … #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK … #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT … #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK … #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT … #define CB_BLEND1_CONTROL__ENABLE_MASK … #define CB_BLEND1_CONTROL__ENABLE__SHIFT … #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK … #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT … #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK … #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT … #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK … #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT … #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK … #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT … #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK … #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT … #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK … #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT … #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK … #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT … #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK … #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT … #define CB_BLEND2_CONTROL__ENABLE_MASK … #define CB_BLEND2_CONTROL__ENABLE__SHIFT … #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK … #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT … #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK … #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT … #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK … #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT … #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK … #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT … #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK … #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT … #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK … #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT … #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK … #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT … #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK … #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT … #define CB_BLEND3_CONTROL__ENABLE_MASK … #define CB_BLEND3_CONTROL__ENABLE__SHIFT … #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK … #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT … #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK … #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT … #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK … #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT … #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK … #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT … #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK … #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT … #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK … #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT … #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK … #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT … #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK … #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT … #define CB_BLEND4_CONTROL__ENABLE_MASK … #define CB_BLEND4_CONTROL__ENABLE__SHIFT … #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK … #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT … #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK … #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT … #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK … #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT … #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK … #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT … #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK … #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT … #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK … #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT … #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK … #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT … #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK … #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT … #define CB_BLEND5_CONTROL__ENABLE_MASK … #define CB_BLEND5_CONTROL__ENABLE__SHIFT … #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK … #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT … #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK … #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT … #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK … #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT … #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK … #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT … #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK … #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT … #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK … #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT … #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK … #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT … #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK … #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT … #define CB_BLEND6_CONTROL__ENABLE_MASK … #define CB_BLEND6_CONTROL__ENABLE__SHIFT … #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK … #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT … #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK … #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT … #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK … #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT … #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK … #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT … #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK … #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT … #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK … #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT … #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK … #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT … #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK … #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT … #define CB_BLEND7_CONTROL__ENABLE_MASK … #define CB_BLEND7_CONTROL__ENABLE__SHIFT … #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK … #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT … #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK … #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT … #define CB_BLEND_BLUE__BLEND_BLUE_MASK … #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT … #define CB_BLEND_GREEN__BLEND_GREEN_MASK … #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT … #define CB_BLEND_RED__BLEND_RED_MASK … #define CB_BLEND_RED__BLEND_RED__SHIFT … #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK … #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK … #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK … #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK … #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT … #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK … #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT … #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK … #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT … #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK … #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT … #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK … #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT … #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK … #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT … #define CB_COLOR0_BASE__BASE_256B_MASK … #define CB_COLOR0_BASE__BASE_256B__SHIFT … #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK … #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT … #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK … #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT … #define CB_COLOR0_CMASK__BASE_256B_MASK … #define CB_COLOR0_CMASK__BASE_256B__SHIFT … #define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR0_FMASK__BASE_256B_MASK … #define CB_COLOR0_FMASK__BASE_256B__SHIFT … #define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR0_INFO__BLEND_BYPASS_MASK … #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT … #define CB_COLOR0_INFO__BLEND_CLAMP_MASK … #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT … #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK … #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK … #define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT … #define CB_COLOR0_INFO__COMPRESSION_MASK … #define CB_COLOR0_INFO__COMPRESSION__SHIFT … #define CB_COLOR0_INFO__COMP_SWAP_MASK … #define CB_COLOR0_INFO__COMP_SWAP__SHIFT … #define CB_COLOR0_INFO__ENDIAN_MASK … #define CB_COLOR0_INFO__ENDIAN__SHIFT … #define CB_COLOR0_INFO__FAST_CLEAR_MASK … #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT … #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK … #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT … #define CB_COLOR0_INFO__FORMAT_MASK … #define CB_COLOR0_INFO__FORMAT__SHIFT … #define CB_COLOR0_INFO__LINEAR_GENERAL_MASK … #define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT … #define CB_COLOR0_INFO__NUMBER_TYPE_MASK … #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT … #define CB_COLOR0_INFO__ROUND_MODE_MASK … #define CB_COLOR0_INFO__ROUND_MODE__SHIFT … #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK … #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT … #define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK … #define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT … #define CB_COLOR0_PITCH__TILE_MAX_MASK … #define CB_COLOR0_PITCH__TILE_MAX__SHIFT … #define CB_COLOR0_SLICE__TILE_MAX_MASK … #define CB_COLOR0_SLICE__TILE_MAX__SHIFT … #define CB_COLOR0_VIEW__SLICE_MAX_MASK … #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT … #define CB_COLOR0_VIEW__SLICE_START_MASK … #define CB_COLOR0_VIEW__SLICE_START__SHIFT … #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK … #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT … #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK … #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT … #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK … #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT … #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK … #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT … #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK … #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT … #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK … #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT … #define CB_COLOR1_BASE__BASE_256B_MASK … #define CB_COLOR1_BASE__BASE_256B__SHIFT … #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK … #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT … #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK … #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT … #define CB_COLOR1_CMASK__BASE_256B_MASK … #define CB_COLOR1_CMASK__BASE_256B__SHIFT … #define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR1_FMASK__BASE_256B_MASK … #define CB_COLOR1_FMASK__BASE_256B__SHIFT … #define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR1_INFO__BLEND_BYPASS_MASK … #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT … #define CB_COLOR1_INFO__BLEND_CLAMP_MASK … #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT … #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK … #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK … #define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT … #define CB_COLOR1_INFO__COMPRESSION_MASK … #define CB_COLOR1_INFO__COMPRESSION__SHIFT … #define CB_COLOR1_INFO__COMP_SWAP_MASK … #define CB_COLOR1_INFO__COMP_SWAP__SHIFT … #define CB_COLOR1_INFO__ENDIAN_MASK … #define CB_COLOR1_INFO__ENDIAN__SHIFT … #define CB_COLOR1_INFO__FAST_CLEAR_MASK … #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT … #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK … #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT … #define CB_COLOR1_INFO__FORMAT_MASK … #define CB_COLOR1_INFO__FORMAT__SHIFT … #define CB_COLOR1_INFO__LINEAR_GENERAL_MASK … #define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT … #define CB_COLOR1_INFO__NUMBER_TYPE_MASK … #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT … #define CB_COLOR1_INFO__ROUND_MODE_MASK … #define CB_COLOR1_INFO__ROUND_MODE__SHIFT … #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK … #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT … #define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK … #define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT … #define CB_COLOR1_PITCH__TILE_MAX_MASK … #define CB_COLOR1_PITCH__TILE_MAX__SHIFT … #define CB_COLOR1_SLICE__TILE_MAX_MASK … #define CB_COLOR1_SLICE__TILE_MAX__SHIFT … #define CB_COLOR1_VIEW__SLICE_MAX_MASK … #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT … #define CB_COLOR1_VIEW__SLICE_START_MASK … #define CB_COLOR1_VIEW__SLICE_START__SHIFT … #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK … #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT … #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK … #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT … #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK … #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT … #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK … #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT … #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK … #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT … #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK … #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT … #define CB_COLOR2_BASE__BASE_256B_MASK … #define CB_COLOR2_BASE__BASE_256B__SHIFT … #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK … #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT … #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK … #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT … #define CB_COLOR2_CMASK__BASE_256B_MASK … #define CB_COLOR2_CMASK__BASE_256B__SHIFT … #define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR2_FMASK__BASE_256B_MASK … #define CB_COLOR2_FMASK__BASE_256B__SHIFT … #define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR2_INFO__BLEND_BYPASS_MASK … #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT … #define CB_COLOR2_INFO__BLEND_CLAMP_MASK … #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT … #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK … #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK … #define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT … #define CB_COLOR2_INFO__COMPRESSION_MASK … #define CB_COLOR2_INFO__COMPRESSION__SHIFT … #define CB_COLOR2_INFO__COMP_SWAP_MASK … #define CB_COLOR2_INFO__COMP_SWAP__SHIFT … #define CB_COLOR2_INFO__ENDIAN_MASK … #define CB_COLOR2_INFO__ENDIAN__SHIFT … #define CB_COLOR2_INFO__FAST_CLEAR_MASK … #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT … #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK … #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT … #define CB_COLOR2_INFO__FORMAT_MASK … #define CB_COLOR2_INFO__FORMAT__SHIFT … #define CB_COLOR2_INFO__LINEAR_GENERAL_MASK … #define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT … #define CB_COLOR2_INFO__NUMBER_TYPE_MASK … #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT … #define CB_COLOR2_INFO__ROUND_MODE_MASK … #define CB_COLOR2_INFO__ROUND_MODE__SHIFT … #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK … #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT … #define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK … #define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT … #define CB_COLOR2_PITCH__TILE_MAX_MASK … #define CB_COLOR2_PITCH__TILE_MAX__SHIFT … #define CB_COLOR2_SLICE__TILE_MAX_MASK … #define CB_COLOR2_SLICE__TILE_MAX__SHIFT … #define CB_COLOR2_VIEW__SLICE_MAX_MASK … #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT … #define CB_COLOR2_VIEW__SLICE_START_MASK … #define CB_COLOR2_VIEW__SLICE_START__SHIFT … #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK … #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT … #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK … #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT … #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK … #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT … #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK … #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT … #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK … #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT … #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK … #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT … #define CB_COLOR3_BASE__BASE_256B_MASK … #define CB_COLOR3_BASE__BASE_256B__SHIFT … #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK … #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT … #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK … #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT … #define CB_COLOR3_CMASK__BASE_256B_MASK … #define CB_COLOR3_CMASK__BASE_256B__SHIFT … #define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR3_FMASK__BASE_256B_MASK … #define CB_COLOR3_FMASK__BASE_256B__SHIFT … #define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR3_INFO__BLEND_BYPASS_MASK … #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT … #define CB_COLOR3_INFO__BLEND_CLAMP_MASK … #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT … #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK … #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK … #define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT … #define CB_COLOR3_INFO__COMPRESSION_MASK … #define CB_COLOR3_INFO__COMPRESSION__SHIFT … #define CB_COLOR3_INFO__COMP_SWAP_MASK … #define CB_COLOR3_INFO__COMP_SWAP__SHIFT … #define CB_COLOR3_INFO__ENDIAN_MASK … #define CB_COLOR3_INFO__ENDIAN__SHIFT … #define CB_COLOR3_INFO__FAST_CLEAR_MASK … #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT … #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK … #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT … #define CB_COLOR3_INFO__FORMAT_MASK … #define CB_COLOR3_INFO__FORMAT__SHIFT … #define CB_COLOR3_INFO__LINEAR_GENERAL_MASK … #define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT … #define CB_COLOR3_INFO__NUMBER_TYPE_MASK … #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT … #define CB_COLOR3_INFO__ROUND_MODE_MASK … #define CB_COLOR3_INFO__ROUND_MODE__SHIFT … #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK … #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT … #define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK … #define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT … #define CB_COLOR3_PITCH__TILE_MAX_MASK … #define CB_COLOR3_PITCH__TILE_MAX__SHIFT … #define CB_COLOR3_SLICE__TILE_MAX_MASK … #define CB_COLOR3_SLICE__TILE_MAX__SHIFT … #define CB_COLOR3_VIEW__SLICE_MAX_MASK … #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT … #define CB_COLOR3_VIEW__SLICE_START_MASK … #define CB_COLOR3_VIEW__SLICE_START__SHIFT … #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK … #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT … #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK … #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT … #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK … #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT … #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK … #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT … #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK … #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT … #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK … #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT … #define CB_COLOR4_BASE__BASE_256B_MASK … #define CB_COLOR4_BASE__BASE_256B__SHIFT … #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK … #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT … #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK … #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT … #define CB_COLOR4_CMASK__BASE_256B_MASK … #define CB_COLOR4_CMASK__BASE_256B__SHIFT … #define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR4_FMASK__BASE_256B_MASK … #define CB_COLOR4_FMASK__BASE_256B__SHIFT … #define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR4_INFO__BLEND_BYPASS_MASK … #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT … #define CB_COLOR4_INFO__BLEND_CLAMP_MASK … #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT … #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK … #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK … #define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT … #define CB_COLOR4_INFO__COMPRESSION_MASK … #define CB_COLOR4_INFO__COMPRESSION__SHIFT … #define CB_COLOR4_INFO__COMP_SWAP_MASK … #define CB_COLOR4_INFO__COMP_SWAP__SHIFT … #define CB_COLOR4_INFO__ENDIAN_MASK … #define CB_COLOR4_INFO__ENDIAN__SHIFT … #define CB_COLOR4_INFO__FAST_CLEAR_MASK … #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT … #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK … #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT … #define CB_COLOR4_INFO__FORMAT_MASK … #define CB_COLOR4_INFO__FORMAT__SHIFT … #define CB_COLOR4_INFO__LINEAR_GENERAL_MASK … #define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT … #define CB_COLOR4_INFO__NUMBER_TYPE_MASK … #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT … #define CB_COLOR4_INFO__ROUND_MODE_MASK … #define CB_COLOR4_INFO__ROUND_MODE__SHIFT … #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK … #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT … #define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK … #define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT … #define CB_COLOR4_PITCH__TILE_MAX_MASK … #define CB_COLOR4_PITCH__TILE_MAX__SHIFT … #define CB_COLOR4_SLICE__TILE_MAX_MASK … #define CB_COLOR4_SLICE__TILE_MAX__SHIFT … #define CB_COLOR4_VIEW__SLICE_MAX_MASK … #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT … #define CB_COLOR4_VIEW__SLICE_START_MASK … #define CB_COLOR4_VIEW__SLICE_START__SHIFT … #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK … #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT … #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK … #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT … #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK … #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT … #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK … #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT … #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK … #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT … #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK … #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT … #define CB_COLOR5_BASE__BASE_256B_MASK … #define CB_COLOR5_BASE__BASE_256B__SHIFT … #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK … #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT … #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK … #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT … #define CB_COLOR5_CMASK__BASE_256B_MASK … #define CB_COLOR5_CMASK__BASE_256B__SHIFT … #define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR5_FMASK__BASE_256B_MASK … #define CB_COLOR5_FMASK__BASE_256B__SHIFT … #define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR5_INFO__BLEND_BYPASS_MASK … #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT … #define CB_COLOR5_INFO__BLEND_CLAMP_MASK … #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT … #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK … #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK … #define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT … #define CB_COLOR5_INFO__COMPRESSION_MASK … #define CB_COLOR5_INFO__COMPRESSION__SHIFT … #define CB_COLOR5_INFO__COMP_SWAP_MASK … #define CB_COLOR5_INFO__COMP_SWAP__SHIFT … #define CB_COLOR5_INFO__ENDIAN_MASK … #define CB_COLOR5_INFO__ENDIAN__SHIFT … #define CB_COLOR5_INFO__FAST_CLEAR_MASK … #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT … #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK … #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT … #define CB_COLOR5_INFO__FORMAT_MASK … #define CB_COLOR5_INFO__FORMAT__SHIFT … #define CB_COLOR5_INFO__LINEAR_GENERAL_MASK … #define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT … #define CB_COLOR5_INFO__NUMBER_TYPE_MASK … #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT … #define CB_COLOR5_INFO__ROUND_MODE_MASK … #define CB_COLOR5_INFO__ROUND_MODE__SHIFT … #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK … #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT … #define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK … #define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT … #define CB_COLOR5_PITCH__TILE_MAX_MASK … #define CB_COLOR5_PITCH__TILE_MAX__SHIFT … #define CB_COLOR5_SLICE__TILE_MAX_MASK … #define CB_COLOR5_SLICE__TILE_MAX__SHIFT … #define CB_COLOR5_VIEW__SLICE_MAX_MASK … #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT … #define CB_COLOR5_VIEW__SLICE_START_MASK … #define CB_COLOR5_VIEW__SLICE_START__SHIFT … #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK … #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT … #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK … #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT … #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK … #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT … #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK … #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT … #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK … #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT … #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK … #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT … #define CB_COLOR6_BASE__BASE_256B_MASK … #define CB_COLOR6_BASE__BASE_256B__SHIFT … #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK … #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT … #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK … #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT … #define CB_COLOR6_CMASK__BASE_256B_MASK … #define CB_COLOR6_CMASK__BASE_256B__SHIFT … #define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR6_FMASK__BASE_256B_MASK … #define CB_COLOR6_FMASK__BASE_256B__SHIFT … #define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR6_INFO__BLEND_BYPASS_MASK … #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT … #define CB_COLOR6_INFO__BLEND_CLAMP_MASK … #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT … #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK … #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK … #define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT … #define CB_COLOR6_INFO__COMPRESSION_MASK … #define CB_COLOR6_INFO__COMPRESSION__SHIFT … #define CB_COLOR6_INFO__COMP_SWAP_MASK … #define CB_COLOR6_INFO__COMP_SWAP__SHIFT … #define CB_COLOR6_INFO__ENDIAN_MASK … #define CB_COLOR6_INFO__ENDIAN__SHIFT … #define CB_COLOR6_INFO__FAST_CLEAR_MASK … #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT … #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK … #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT … #define CB_COLOR6_INFO__FORMAT_MASK … #define CB_COLOR6_INFO__FORMAT__SHIFT … #define CB_COLOR6_INFO__LINEAR_GENERAL_MASK … #define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT … #define CB_COLOR6_INFO__NUMBER_TYPE_MASK … #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT … #define CB_COLOR6_INFO__ROUND_MODE_MASK … #define CB_COLOR6_INFO__ROUND_MODE__SHIFT … #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK … #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT … #define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK … #define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT … #define CB_COLOR6_PITCH__TILE_MAX_MASK … #define CB_COLOR6_PITCH__TILE_MAX__SHIFT … #define CB_COLOR6_SLICE__TILE_MAX_MASK … #define CB_COLOR6_SLICE__TILE_MAX__SHIFT … #define CB_COLOR6_VIEW__SLICE_MAX_MASK … #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT … #define CB_COLOR6_VIEW__SLICE_START_MASK … #define CB_COLOR6_VIEW__SLICE_START__SHIFT … #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK … #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT … #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK … #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT … #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK … #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT … #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK … #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT … #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK … #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT … #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK … #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT … #define CB_COLOR7_BASE__BASE_256B_MASK … #define CB_COLOR7_BASE__BASE_256B__SHIFT … #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK … #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT … #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK … #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT … #define CB_COLOR7_CMASK__BASE_256B_MASK … #define CB_COLOR7_CMASK__BASE_256B__SHIFT … #define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR7_FMASK__BASE_256B_MASK … #define CB_COLOR7_FMASK__BASE_256B__SHIFT … #define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK … #define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT … #define CB_COLOR7_INFO__BLEND_BYPASS_MASK … #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT … #define CB_COLOR7_INFO__BLEND_CLAMP_MASK … #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT … #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK … #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK … #define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT … #define CB_COLOR7_INFO__COMPRESSION_MASK … #define CB_COLOR7_INFO__COMPRESSION__SHIFT … #define CB_COLOR7_INFO__COMP_SWAP_MASK … #define CB_COLOR7_INFO__COMP_SWAP__SHIFT … #define CB_COLOR7_INFO__ENDIAN_MASK … #define CB_COLOR7_INFO__ENDIAN__SHIFT … #define CB_COLOR7_INFO__FAST_CLEAR_MASK … #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT … #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK … #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT … #define CB_COLOR7_INFO__FORMAT_MASK … #define CB_COLOR7_INFO__FORMAT__SHIFT … #define CB_COLOR7_INFO__LINEAR_GENERAL_MASK … #define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT … #define CB_COLOR7_INFO__NUMBER_TYPE_MASK … #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT … #define CB_COLOR7_INFO__ROUND_MODE_MASK … #define CB_COLOR7_INFO__ROUND_MODE__SHIFT … #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK … #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT … #define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK … #define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT … #define CB_COLOR7_PITCH__TILE_MAX_MASK … #define CB_COLOR7_PITCH__TILE_MAX__SHIFT … #define CB_COLOR7_SLICE__TILE_MAX_MASK … #define CB_COLOR7_SLICE__TILE_MAX__SHIFT … #define CB_COLOR7_VIEW__SLICE_MAX_MASK … #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT … #define CB_COLOR7_VIEW__SLICE_START_MASK … #define CB_COLOR7_VIEW__SLICE_START__SHIFT … #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK … #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT … #define CB_COLOR_CONTROL__MODE_MASK … #define CB_COLOR_CONTROL__MODE__SHIFT … #define CB_COLOR_CONTROL__ROP3_MASK … #define CB_COLOR_CONTROL__ROP3__SHIFT … #define CB_DEBUG_BUS_13__AC_BUSY_MASK … #define CB_DEBUG_BUS_13__AC_BUSY__SHIFT … #define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK … #define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT … #define CB_DEBUG_BUS_13__CRW_BUSY_MASK … #define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT … #define CB_DEBUG_BUS_13__EVICT_PENDING_MASK … #define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT … #define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK … #define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT … #define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK … #define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT … #define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK … #define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT … #define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK … #define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT … #define CB_DEBUG_BUS_13__MU_BUSY_MASK … #define CB_DEBUG_BUS_13__MU_BUSY__SHIFT … #define CB_DEBUG_BUS_13__MU_STATE_MASK … #define CB_DEBUG_BUS_13__MU_STATE__SHIFT … #define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK … #define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT … #define CB_DEBUG_BUS_13__TQ_BUSY_MASK … #define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT … #define CB_DEBUG_BUS_14__ADDR_BUSY_MASK … #define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT … #define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK … #define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT … #define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK … #define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT … #define CB_DEBUG_BUS_14__FOP_BUSY_MASK … #define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT … #define CB_DEBUG_BUS_14__LAT_BUSY_MASK … #define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT … #define CB_DEBUG_BUS_14__MERGE_BUSY_MASK … #define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT … #define CB_DEBUG_BUS_14__QUAD_BUSY_MASK … #define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT … #define CB_DEBUG_BUS_14__TILE_BUSY_MASK … #define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT … #define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK … #define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT … #define CB_DEBUG_BUS_15__CS_BUSY_MASK … #define CB_DEBUG_BUS_15__CS_BUSY__SHIFT … #define CB_DEBUG_BUS_15__DS_BUSY_MASK … #define CB_DEBUG_BUS_15__DS_BUSY__SHIFT … #define CB_DEBUG_BUS_15__IB_BUSY_MASK … #define CB_DEBUG_BUS_15__IB_BUSY__SHIFT … #define CB_DEBUG_BUS_15__RB_BUSY_MASK … #define CB_DEBUG_BUS_15__RB_BUSY__SHIFT … #define CB_DEBUG_BUS_15__SF_BUSY_MASK … #define CB_DEBUG_BUS_15__SF_BUSY__SHIFT … #define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK … #define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT … #define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK … #define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT … #define CB_DEBUG_BUS_15__TB_BUSY_MASK … #define CB_DEBUG_BUS_15__TB_BUSY__SHIFT … #define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK … #define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT … #define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK … #define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT … #define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK … #define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT … #define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK … #define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT … #define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK … #define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT … #define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK … #define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT … #define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK … #define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT … #define CB_DEBUG_BUS_17__BB_BUSY_MASK … #define CB_DEBUG_BUS_17__BB_BUSY__SHIFT … #define CB_DEBUG_BUS_17__CC_BUSY_MASK … #define CB_DEBUG_BUS_17__CC_BUSY__SHIFT … #define CB_DEBUG_BUS_17__CM_BUSY_MASK … #define CB_DEBUG_BUS_17__CM_BUSY__SHIFT … #define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK … #define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT … #define CB_DEBUG_BUS_17__FC_BUSY_MASK … #define CB_DEBUG_BUS_17__FC_BUSY__SHIFT … #define CB_DEBUG_BUS_17__MA_BUSY_MASK … #define CB_DEBUG_BUS_17__MA_BUSY__SHIFT … #define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK … #define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT … #define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK … #define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT … #define CB_DEBUG_BUS_18__NOT_USED_MASK … #define CB_DEBUG_BUS_18__NOT_USED__SHIFT … #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK … #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT … #define CB_HW_CONTROL_1__CHICKEN_BITS_MASK … #define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT … #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK … #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT … #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK … #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT … #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK … #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT … #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK … #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT … #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK … #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT … #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK … #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT … #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK … #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT … #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK … #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT … #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK … #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT … #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK … #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT … #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK … #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK … #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT … #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK … #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT … #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK … #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT … #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK … #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT … #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK … #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT … #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK … #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT … #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK … #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT … #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK … #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT … #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK … #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT … #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK … #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT … #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK … #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT … #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK … #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT … #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK … #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT … #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK … #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT … #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK … #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT … #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK … #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT … #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK … #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT … #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK … #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT … #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK … #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT … #define CB_TARGET_MASK__TARGET0_ENABLE_MASK … #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT … #define CB_TARGET_MASK__TARGET1_ENABLE_MASK … #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT … #define CB_TARGET_MASK__TARGET2_ENABLE_MASK … #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT … #define CB_TARGET_MASK__TARGET3_ENABLE_MASK … #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT … #define CB_TARGET_MASK__TARGET4_ENABLE_MASK … #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT … #define CB_TARGET_MASK__TARGET5_ENABLE_MASK … #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT … #define CB_TARGET_MASK__TARGET6_ENABLE_MASK … #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT … #define CB_TARGET_MASK__TARGET7_ENABLE_MASK … #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT … #define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK … #define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT … #define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK … #define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT … #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK … #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT … #define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK … #define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT … #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK … #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT … #define CC_RB_DAISY_CHAIN__RB_0_MASK … #define CC_RB_DAISY_CHAIN__RB_0__SHIFT … #define CC_RB_DAISY_CHAIN__RB_1_MASK … #define CC_RB_DAISY_CHAIN__RB_1__SHIFT … #define CC_RB_DAISY_CHAIN__RB_2_MASK … #define CC_RB_DAISY_CHAIN__RB_2__SHIFT … #define CC_RB_DAISY_CHAIN__RB_3_MASK … #define CC_RB_DAISY_CHAIN__RB_3__SHIFT … #define CC_RB_DAISY_CHAIN__RB_4_MASK … #define CC_RB_DAISY_CHAIN__RB_4__SHIFT … #define CC_RB_DAISY_CHAIN__RB_5_MASK … #define CC_RB_DAISY_CHAIN__RB_5__SHIFT … #define CC_RB_DAISY_CHAIN__RB_6_MASK … #define CC_RB_DAISY_CHAIN__RB_6__SHIFT … #define CC_RB_DAISY_CHAIN__RB_7_MASK … #define CC_RB_DAISY_CHAIN__RB_7__SHIFT … #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK … #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT … #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK … #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT … #define CC_RB_REDUNDANCY__FAILED_RB0_MASK … #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT … #define CC_RB_REDUNDANCY__FAILED_RB1_MASK … #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT … #define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK … #define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT … #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK … #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT … #define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK … #define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT … #define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK … #define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT … #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK … #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT … #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK … #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT … #define CGTS_RD_REG__READ_DATA_MASK … #define CGTS_RD_REG__READ_DATA__SHIFT … #define CGTS_SM_CTRL_REG__BASE_MODE_MASK … #define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT … #define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK … #define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT … #define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK … #define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT … #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK … #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT … #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK … #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT … #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK … #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT … #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK … #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT … #define CGTS_SM_CTRL_REG__OVERRIDE_MASK … #define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT … #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK … #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT … #define CGTS_SM_CTRL_REG__SM_MODE_MASK … #define CGTS_SM_CTRL_REG__SM_MODE__SHIFT … #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK … #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT … #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK … #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT … #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK … #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT … #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK … #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT … #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK … #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT … #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK … #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT … #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK … #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT … #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK … #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT … #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK … #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT … #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK … #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK … #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT … #define CGTT_BCI_CLK_CTRL__RESERVED_MASK … #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT … #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK … #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK … #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT … #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK … #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT … #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK … #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK … #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK … #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT … #define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK … #define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT … #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK … #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK … #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT … #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK … #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT … #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK … #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT … #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK … #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK … #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK … #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK … #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT … #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK … #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK … #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK … #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK … #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT … #define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK … #define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT … #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK … #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT … #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK … #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT … #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK … #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT … #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK … #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT … #define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK … #define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT … #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK … #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT … #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK … #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT … #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK … #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK … #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT … #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK … #define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK … #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT … #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK … #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT … #define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_SC_CLK_CTRL__ON_DELAY_MASK … #define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK … #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK … #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT … #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK … #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT … #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK … #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT … #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK … #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT … #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK … #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT … #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK … #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT … #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK … #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT … #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK … #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK … #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT … #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK … #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT … #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK … #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK … #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT … #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK … #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT … #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK … #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK … #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT … #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK … #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT … #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK … #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT … #define CGTT_SX_CLK_CTRL0__RESERVED_MASK … #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK … #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT … #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK … #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT … #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK … #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT … #define CGTT_SX_CLK_CTRL1__RESERVED_MASK … #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK … #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT … #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK … #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT … #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK … #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT … #define CGTT_SX_CLK_CTRL2__RESERVED_MASK … #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK … #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT … #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK … #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT … #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK … #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT … #define CGTT_SX_CLK_CTRL3__RESERVED_MASK … #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK … #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT … #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK … #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT … #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK … #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT … #define CGTT_SX_CLK_CTRL4__RESERVED_MASK … #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK … #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT … #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK … #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK … #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK … #define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK … #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK … #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT … #define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK … #define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT … #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK … #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT … #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK … #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT … #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK … #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT … #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK … #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT … #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK … #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK … #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK … #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK … #define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT … #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK … #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK … #define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK … #define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK … #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK … #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK … #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK … #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK … #define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT … #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK … #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK … #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK … #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK … #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK … #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK … #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK … #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK … #define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT … #define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK … #define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT … #define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK … #define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK … #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK … #define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT … #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK … #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK … #define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT … #define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK … #define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT … #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK … #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT … #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK … #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK … #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT … #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK … #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT … #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK … #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT … #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK … #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT … #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK … #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT … #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK … #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT … #define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK … #define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT … #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK … #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK … #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK … #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK … #define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK … #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK … #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT … #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK … #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT … #define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK … #define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK … #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK … #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK … #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK … #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK … #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK … #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK … #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK … #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK … #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK … #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK … #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK … #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK … #define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK … #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK … #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK … #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK … #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK … #define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK … #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK … #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK … #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK … #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK … #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK … #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK … #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK … #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK … #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK … #define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT … #define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK … #define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT … #define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK … #define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT … #define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK … #define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT … #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK … #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT … #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK … #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT … #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK … #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT … #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK … #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK … #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK … #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK … #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK … #define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK … #define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT … #define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK … #define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK … #define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT … #define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK … #define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT … #define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK … #define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT … #define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK … #define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT … #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK … #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT … #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK … #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT … #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK … #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK … #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT … #define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK … #define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT … #define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK … #define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT … #define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK … #define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT … #define CLIPPER_DEBUG_REG13__prim_back_valid_MASK … #define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT … #define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK … #define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT … #define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK … #define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT … #define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK … #define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT … #define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK … #define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT … #define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK … #define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT … #define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK … #define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT … #define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK … #define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT … #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK … #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT … #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK … #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT … #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK … #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT … #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK … #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT … #define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK … #define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT … #define CLIPPER_DEBUG_REG14__prim_back_valid_MASK … #define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT … #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK … #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT … #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK … #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT … #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK … #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT … #define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK … #define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT … #define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK … #define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK … #define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK … #define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK … #define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_current_state_MASK … #define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK … #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK … #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK … #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK … #define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK … #define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK … #define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT … #define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK … #define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK … #define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK … #define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK … #define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_current_state_MASK … #define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK … #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK … #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK … #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK … #define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK … #define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK … #define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT … #define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK … #define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK … #define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK … #define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK … #define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_current_state_MASK … #define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK … #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK … #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK … #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK … #define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK … #define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK … #define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT … #define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK … #define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK … #define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK … #define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK … #define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK … #define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_current_state_MASK … #define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK … #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK … #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK … #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK … #define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK … #define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK … #define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT … #define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK … #define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT … #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK … #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT … #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK … #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT … #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK … #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT … #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK … #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT … #define COMPUTE_DIM_X__SIZE_MASK … #define COMPUTE_DIM_X__SIZE__SHIFT … #define COMPUTE_DIM_Y__SIZE_MASK … #define COMPUTE_DIM_Y__SIZE__SHIFT … #define COMPUTE_DIM_Z__SIZE_MASK … #define COMPUTE_DIM_Z__SIZE__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK … #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK … #define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK … #define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK … #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK … #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK … #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK … #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK … #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK … #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK … #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK … #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT … #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK … #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT … #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK … #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT … #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK … #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT … #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK … #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT … #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK … #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT … #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK … #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT … #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK … #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT … #define COMPUTE_PGM_HI__DATA_MASK … #define COMPUTE_PGM_HI__DATA__SHIFT … #define COMPUTE_PGM_HI__INST_ATC_MASK … #define COMPUTE_PGM_HI__INST_ATC__SHIFT … #define COMPUTE_PGM_LO__DATA_MASK … #define COMPUTE_PGM_LO__DATA__SHIFT … #define COMPUTE_PGM_RSRC1__BULKY_MASK … #define COMPUTE_PGM_RSRC1__BULKY__SHIFT … #define COMPUTE_PGM_RSRC1__CDBG_USER_MASK … #define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT … #define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK … #define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT … #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK … #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT … #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK … #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT … #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK … #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT … #define COMPUTE_PGM_RSRC1__PRIORITY_MASK … #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT … #define COMPUTE_PGM_RSRC1__PRIV_MASK … #define COMPUTE_PGM_RSRC1__PRIV__SHIFT … #define COMPUTE_PGM_RSRC1__SGPRS_MASK … #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT … #define COMPUTE_PGM_RSRC1__VGPRS_MASK … #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT … #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK … #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK … #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT … #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT … #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK … #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT … #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK … #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT … #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK … #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT … #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK … #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT … #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK … #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT … #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK … #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT … #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK … #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT … #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK … #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT … #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK … #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT … #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK … #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT … #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK … #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT … #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK … #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT … #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK … #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT … #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK … #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT … #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK … #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT … #define COMPUTE_START_X__START_MASK … #define COMPUTE_START_X__START__SHIFT … #define COMPUTE_START_Y__START_MASK … #define COMPUTE_START_Y__START__SHIFT … #define COMPUTE_START_Z__START_MASK … #define COMPUTE_START_Z__START__SHIFT … #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK … #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT … #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK … #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT … #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK … #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT … #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK … #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT … #define COMPUTE_TBA_HI__DATA_MASK … #define COMPUTE_TBA_HI__DATA__SHIFT … #define COMPUTE_TBA_LO__DATA_MASK … #define COMPUTE_TBA_LO__DATA__SHIFT … #define COMPUTE_TMA_HI__DATA_MASK … #define COMPUTE_TMA_HI__DATA__SHIFT … #define COMPUTE_TMA_LO__DATA_MASK … #define COMPUTE_TMA_LO__DATA__SHIFT … #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK … #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT … #define COMPUTE_TMPRING_SIZE__WAVES_MASK … #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT … #define COMPUTE_USER_DATA_0__DATA_MASK … #define COMPUTE_USER_DATA_0__DATA__SHIFT … #define COMPUTE_USER_DATA_10__DATA_MASK … #define COMPUTE_USER_DATA_10__DATA__SHIFT … #define COMPUTE_USER_DATA_11__DATA_MASK … #define COMPUTE_USER_DATA_11__DATA__SHIFT … #define COMPUTE_USER_DATA_12__DATA_MASK … #define COMPUTE_USER_DATA_12__DATA__SHIFT … #define COMPUTE_USER_DATA_13__DATA_MASK … #define COMPUTE_USER_DATA_13__DATA__SHIFT … #define COMPUTE_USER_DATA_14__DATA_MASK … #define COMPUTE_USER_DATA_14__DATA__SHIFT … #define COMPUTE_USER_DATA_15__DATA_MASK … #define COMPUTE_USER_DATA_15__DATA__SHIFT … #define COMPUTE_USER_DATA_1__DATA_MASK … #define COMPUTE_USER_DATA_1__DATA__SHIFT … #define COMPUTE_USER_DATA_2__DATA_MASK … #define COMPUTE_USER_DATA_2__DATA__SHIFT … #define COMPUTE_USER_DATA_3__DATA_MASK … #define COMPUTE_USER_DATA_3__DATA__SHIFT … #define COMPUTE_USER_DATA_4__DATA_MASK … #define COMPUTE_USER_DATA_4__DATA__SHIFT … #define COMPUTE_USER_DATA_5__DATA_MASK … #define COMPUTE_USER_DATA_5__DATA__SHIFT … #define COMPUTE_USER_DATA_6__DATA_MASK … #define COMPUTE_USER_DATA_6__DATA__SHIFT … #define COMPUTE_USER_DATA_7__DATA_MASK … #define COMPUTE_USER_DATA_7__DATA__SHIFT … #define COMPUTE_USER_DATA_8__DATA_MASK … #define COMPUTE_USER_DATA_8__DATA__SHIFT … #define COMPUTE_USER_DATA_9__DATA_MASK … #define COMPUTE_USER_DATA_9__DATA__SHIFT … #define COMPUTE_VMID__DATA_MASK … #define COMPUTE_VMID__DATA__SHIFT … #define CP_APPEND_ADDR_HI__COMMAND_MASK … #define CP_APPEND_ADDR_HI__COMMAND__SHIFT … #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK … #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT … #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK … #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT … #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK … #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT … #define CP_APPEND_DATA__DATA_MASK … #define CP_APPEND_DATA__DATA__SHIFT … #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK … #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT … #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK … #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT … #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK … #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT … #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK … #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT … #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK … #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT … #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK … #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT … #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK … #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT … #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK … #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT … #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK … #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT … #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK … #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT … #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK … #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT … #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK … #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT … #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK … #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT … #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK … #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT … #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK … #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT … #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK … #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT … #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK … #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT … #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK … #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT … #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK … #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT … #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK … #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT … #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK … #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT … #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK … #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT … #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK … #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT … #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK … #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT … #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK … #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT … #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK … #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT … #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK … #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT … #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK … #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT … #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK … #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT … #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK … #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT … #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK … #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT … #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK … #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT … #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK … #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT … #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK … #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT … #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK … #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT … #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK … #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT … #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK … #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT … #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK … #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT … #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT … #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK … #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT … #define CP_CE_UCODE_DATA__UCODE_DATA_MASK … #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT … #define CP_CMD_DATA__CMD_DATA_MASK … #define CP_CMD_DATA__CMD_DATA__SHIFT … #define CP_CMD_INDEX__CMD_INDEX_MASK … #define CP_CMD_INDEX__CMD_INDEX__SHIFT … #define CP_CMD_INDEX__CMD_ME_SEL_MASK … #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT … #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK … #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT … #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK … #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT … #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK … #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT … #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK … #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT … #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK … #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT … #define CP_COHER_BASE__COHER_BASE_256B_MASK … #define CP_COHER_BASE__COHER_BASE_256B__SHIFT … #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK … #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT … #define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__CB_ACTION_ENA_MASK … #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__DB_ACTION_ENA_MASK … #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK … #define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT … #define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK … #define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT … #define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK … #define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT … #define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK … #define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT … #define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK … #define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT … #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK … #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK … #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK … #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__TC_ACTION_ENA_MASK … #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK … #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK … #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK … #define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT … #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK … #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT … #define CP_COHER_SIZE__COHER_SIZE_256B_MASK … #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT … #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK … #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT … #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK … #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT … #define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK … #define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT … #define CP_COHER_STATUS__MEID_MASK … #define CP_COHER_STATUS__MEID__SHIFT … #define CP_COHER_STATUS__PHASE1_STATUS_MASK … #define CP_COHER_STATUS__PHASE1_STATUS__SHIFT … #define CP_COHER_STATUS__STATUS_MASK … #define CP_COHER_STATUS__STATUS__SHIFT … #define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK … #define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT … #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK … #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT … #define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK … #define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT … #define CP_DMA_CNTL__BUFFER_DEPTH_MASK … #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT … #define CP_DMA_CNTL__MIN_AVAILSZ_MASK … #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT … #define CP_DMA_CNTL__PIO_COUNT_MASK … #define CP_DMA_CNTL__PIO_COUNT__SHIFT … #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK … #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT … #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK … #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT … #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK … #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT … #define CP_DMA_ME_COMMAND__DAIC_MASK … #define CP_DMA_ME_COMMAND__DAIC__SHIFT … #define CP_DMA_ME_COMMAND__DAS_MASK … #define CP_DMA_ME_COMMAND__DAS__SHIFT … #define CP_DMA_ME_COMMAND__DIS_WC_MASK … #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT … #define CP_DMA_ME_COMMAND__DST_SWAP_MASK … #define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT … #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK … #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT … #define CP_DMA_ME_COMMAND__SAIC_MASK … #define CP_DMA_ME_COMMAND__SAIC__SHIFT … #define CP_DMA_ME_COMMAND__SAS_MASK … #define CP_DMA_ME_COMMAND__SAS__SHIFT … #define CP_DMA_ME_COMMAND__SRC_SWAP_MASK … #define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT … #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK … #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT … #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK … #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT … #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK … #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT … #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK … #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT … #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK … #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT … #define CP_DMA_PFP_COMMAND__DAIC_MASK … #define CP_DMA_PFP_COMMAND__DAIC__SHIFT … #define CP_DMA_PFP_COMMAND__DAS_MASK … #define CP_DMA_PFP_COMMAND__DAS__SHIFT … #define CP_DMA_PFP_COMMAND__DIS_WC_MASK … #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT … #define CP_DMA_PFP_COMMAND__DST_SWAP_MASK … #define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT … #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK … #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT … #define CP_DMA_PFP_COMMAND__SAIC_MASK … #define CP_DMA_PFP_COMMAND__SAIC__SHIFT … #define CP_DMA_PFP_COMMAND__SAS_MASK … #define CP_DMA_PFP_COMMAND__SAS__SHIFT … #define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK … #define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT … #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK … #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT … #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK … #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT … #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK … #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT … #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK … #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT … #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK … #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT … #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK … #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT … #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK … #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT … #define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK … #define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT … #define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK … #define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT … #define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK … #define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT … #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK … #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT … #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK … #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT … #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK … #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT … #define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK … #define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT … #define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK … #define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT … #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK … #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT … #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK … #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT … #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK … #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT … #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK … #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT … #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK … #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT … #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK … #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT … #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK … #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT … #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK … #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT … #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK … #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT … #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK … #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT … #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK … #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT … #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK … #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT … #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK … #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK … #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT … #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT … #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK … #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT … #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK … #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT … #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK … #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT … #define CP_IB1_OFFSET__IB1_OFFSET_MASK … #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT … #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK … #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT … #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK … #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT … #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK … #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT … #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK … #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT … #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK … #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT … #define CP_IB2_OFFSET__IB2_OFFSET_MASK … #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT … #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK … #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT … #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK … #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT … #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK … #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT … #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK … #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT … #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK … #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT … #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK … #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT … #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT … #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT … #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK … #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK … #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT … #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK … #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT … #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK … #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT … #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK … #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT … #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT … #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK … #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT … #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK … #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT … #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK … #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT … #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK … #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK … #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT … #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK … #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT … #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK … #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT … #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK … #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK … #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT … #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT … #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK … #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK … #define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK … #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK … #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK … #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK … #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK … #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK … #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK … #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT … #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK … #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK … #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK … #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK … #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK … #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK … #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK … #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK … #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK … #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT … #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK … #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK … #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK … #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK … #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK … #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK … #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK … #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK … #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK … #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK … #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT … #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK … #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT … #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK … #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT … #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK … #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT … #define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK … #define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT … #define CP_ME_CNTL__CE_HALT_MASK … #define CP_ME_CNTL__CE_HALT__SHIFT … #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK … #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT … #define CP_ME_CNTL__CE_STEP_MASK … #define CP_ME_CNTL__CE_STEP__SHIFT … #define CP_ME_CNTL__ME_HALT_MASK … #define CP_ME_CNTL__ME_HALT__SHIFT … #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK … #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT … #define CP_ME_CNTL__ME_STEP_MASK … #define CP_ME_CNTL__ME_STEP__SHIFT … #define CP_ME_CNTL__PFP_HALT_MASK … #define CP_ME_CNTL__PFP_HALT__SHIFT … #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK … #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT … #define CP_ME_CNTL__PFP_STEP_MASK … #define CP_ME_CNTL__PFP_STEP__SHIFT … #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK … #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT … #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK … #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT … #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK … #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT … #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK … #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT … #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK … #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT … #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK … #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT … #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK … #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT … #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK … #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT … #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK … #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT … #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK … #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT … #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT … #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK … #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT … #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK … #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT … #define CP_MEM_SLP_CNTL__RESERVED1_MASK … #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT … #define CP_MEM_SLP_CNTL__RESERVED_MASK … #define CP_MEM_SLP_CNTL__RESERVED__SHIFT … #define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK … #define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT … #define CP_MEQ_AVAIL__MEQ_CNT_MASK … #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT … #define CP_MEQ_STAT__MEQ_RPTR_MASK … #define CP_MEQ_STAT__MEQ_RPTR__SHIFT … #define CP_MEQ_STAT__MEQ_WPTR_MASK … #define CP_MEQ_STAT__MEQ_WPTR__SHIFT … #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK … #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT … #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK … #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT … #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK … #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT … #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK … #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT … #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK … #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT … #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK … #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT … #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK … #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT … #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK … #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT … #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK … #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT … #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK … #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT … #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK … #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT … #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK … #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT … #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK … #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT … #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK … #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT … #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK … #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT … #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK … #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT … #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK … #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT … #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK … #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT … #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK … #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT … #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK … #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT … #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK … #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT … #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK … #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT … #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK … #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT … #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK … #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT … #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK … #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT … #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK … #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT … #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK … #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … #define CP_PERFMON_CNTL__PERFMON_STATE_MASK … #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT … #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK … #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT … #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK … #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT … #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK … #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT … #define CP_PFP_IB_CONTROL__IB_EN_MASK … #define CP_PFP_IB_CONTROL__IB_EN__SHIFT … #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK … #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT … #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK … #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT … #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK … #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT … #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK … #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT … #define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK … #define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT … #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK … #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT … #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK … #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT … #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK … #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT … #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK … #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT … #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK … #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT … #define CP_PWR_CNTL__GFX_CLK_HALT_MASK … #define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT … #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK … #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT … #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK … #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT … #define CP_RB0_BASE_HI__RB_BASE_HI_MASK … #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT … #define CP_RB0_BASE__RB_BASE_MASK … #define CP_RB0_BASE__RB_BASE__SHIFT … #define CP_RB0_CNTL__BUF_SWAP_MASK … #define CP_RB0_CNTL__BUF_SWAP__SHIFT … #define CP_RB0_CNTL__CACHE_POLICY_MASK … #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … #define CP_RB0_CNTL__MIN_AVAILSZ_MASK … #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT … #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK … #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT … #define CP_RB0_CNTL__RB_BLKSZ_MASK … #define CP_RB0_CNTL__RB_BLKSZ__SHIFT … #define CP_RB0_CNTL__RB_BUFSZ_MASK … #define CP_RB0_CNTL__RB_BUFSZ__SHIFT … #define CP_RB0_CNTL__RB_NO_UPDATE_MASK … #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT … #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT … #define CP_RB0_CNTL__RB_VOLATILE_MASK … #define CP_RB0_CNTL__RB_VOLATILE__SHIFT … #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK … #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT … #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK … #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT … #define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK … #define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT … #define CP_RB0_RPTR__RB_RPTR_MASK … #define CP_RB0_RPTR__RB_RPTR__SHIFT … #define CP_RB0_WPTR__RB_WPTR_MASK … #define CP_RB0_WPTR__RB_WPTR__SHIFT … #define CP_RB1_BASE_HI__RB_BASE_HI_MASK … #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT … #define CP_RB1_BASE__RB_BASE_MASK … #define CP_RB1_BASE__RB_BASE__SHIFT … #define CP_RB1_CNTL__CACHE_POLICY_MASK … #define CP_RB1_CNTL__CACHE_POLICY__SHIFT … #define CP_RB1_CNTL__MIN_AVAILSZ_MASK … #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT … #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK … #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT … #define CP_RB1_CNTL__RB_BLKSZ_MASK … #define CP_RB1_CNTL__RB_BLKSZ__SHIFT … #define CP_RB1_CNTL__RB_BUFSZ_MASK … #define CP_RB1_CNTL__RB_BUFSZ__SHIFT … #define CP_RB1_CNTL__RB_NO_UPDATE_MASK … #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT … #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT … #define CP_RB1_CNTL__RB_VOLATILE_MASK … #define CP_RB1_CNTL__RB_VOLATILE__SHIFT … #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK … #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT … #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK … #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT … #define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK … #define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT … #define CP_RB1_RPTR__RB_RPTR_MASK … #define CP_RB1_RPTR__RB_RPTR__SHIFT … #define CP_RB1_WPTR__RB_WPTR_MASK … #define CP_RB1_WPTR__RB_WPTR__SHIFT … #define CP_RB2_BASE__RB_BASE_MASK … #define CP_RB2_BASE__RB_BASE__SHIFT … #define CP_RB2_CNTL__CACHE_POLICY_MASK … #define CP_RB2_CNTL__CACHE_POLICY__SHIFT … #define CP_RB2_CNTL__MIN_AVAILSZ_MASK … #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT … #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK … #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT … #define CP_RB2_CNTL__RB_BLKSZ_MASK … #define CP_RB2_CNTL__RB_BLKSZ__SHIFT … #define CP_RB2_CNTL__RB_BUFSZ_MASK … #define CP_RB2_CNTL__RB_BUFSZ__SHIFT … #define CP_RB2_CNTL__RB_NO_UPDATE_MASK … #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT … #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK … #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT … #define CP_RB2_CNTL__RB_VOLATILE_MASK … #define CP_RB2_CNTL__RB_VOLATILE__SHIFT … #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK … #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT … #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK … #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT … #define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK … #define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT … #define CP_RB2_RPTR__RB_RPTR_MASK … #define CP_RB2_RPTR__RB_RPTR__SHIFT … #define CP_RB2_WPTR__RB_WPTR_MASK … #define CP_RB2_WPTR__RB_WPTR__SHIFT … #define CP_RB_BASE__RB_BASE_MASK … #define CP_RB_BASE__RB_BASE__SHIFT … #define CP_RB_CNTL__BUF_SWAP_MASK … #define CP_RB_CNTL__BUF_SWAP__SHIFT … #define CP_RB_CNTL__CACHE_POLICY_MASK … #define CP_RB_CNTL__CACHE_POLICY__SHIFT … #define CP_RB_CNTL__MIN_AVAILSZ_MASK … #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT … #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK … #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT … #define CP_RB_CNTL__RB_BLKSZ_MASK … #define CP_RB_CNTL__RB_BLKSZ__SHIFT … #define CP_RB_CNTL__RB_BUFSZ_MASK … #define CP_RB_CNTL__RB_BUFSZ__SHIFT … #define CP_RB_CNTL__RB_NO_UPDATE_MASK … #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT … #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK … #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT … #define CP_RB_CNTL__RB_VOLATILE_MASK … #define CP_RB_CNTL__RB_VOLATILE__SHIFT … #define CP_RB_OFFSET__RB_OFFSET_MASK … #define CP_RB_OFFSET__RB_OFFSET__SHIFT … #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK … #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT … #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK … #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT … #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK … #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT … #define CP_RB_RPTR__RB_RPTR_MASK … #define CP_RB_RPTR__RB_RPTR__SHIFT … #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK … #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT … #define CP_RB_VMID__RB0_VMID_MASK … #define CP_RB_VMID__RB0_VMID__SHIFT … #define CP_RB_VMID__RB1_VMID_MASK … #define CP_RB_VMID__RB1_VMID__SHIFT … #define CP_RB_VMID__RB2_VMID_MASK … #define CP_RB_VMID__RB2_VMID__SHIFT … #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK … #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT … #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK … #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT … #define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK … #define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT … #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK … #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT … #define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK … #define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT … #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK … #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT … #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK … #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT … #define CP_RB_WPTR__RB_WPTR_MASK … #define CP_RB_WPTR__RB_WPTR__SHIFT … #define CP_RING0_PRIORITY__PRIORITY_MASK … #define CP_RING0_PRIORITY__PRIORITY__SHIFT … #define CP_RING1_PRIORITY__PRIORITY_MASK … #define CP_RING1_PRIORITY__PRIORITY__SHIFT … #define CP_RING2_PRIORITY__PRIORITY_MASK … #define CP_RING2_PRIORITY__PRIORITY__SHIFT … #define CP_RINGID__RINGID_MASK … #define CP_RINGID__RINGID__SHIFT … #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK … #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT … #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK … #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT … #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK … #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT … #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK … #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT … #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK … #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK … #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT … #define CP_ROQ1_THRESHOLDS__RB1_START_MASK … #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT … #define CP_ROQ1_THRESHOLDS__RB2_START_MASK … #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT … #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK … #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT … #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK … #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT … #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK … #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT … #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK … #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT … #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK … #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT … #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK … #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT … #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK … #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT … #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK … #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT … #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK … #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT … #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK … #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT … #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK … #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT … #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK … #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT … #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK … #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT … #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK … #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT … #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK … #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT … #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK … #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT … #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK … #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT … #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK … #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT … #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK … #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT … #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK … #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT … #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK … #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT … #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK … #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT … #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK … #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK … #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT … #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK … #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT … #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK … #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT … #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK … #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT … #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK … #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT … #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK … #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT … #define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK … #define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT … #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK … #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT … #define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK … #define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT … #define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK … #define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT … #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK … #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT … #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK … #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT … #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK … #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT … #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK … #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT … #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK … #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT … #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK … #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT … #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK … #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT … #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK … #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT … #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK … #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT … #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK … #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT … #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK … #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT … #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK … #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT … #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK … #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT … #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK … #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT … #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK … #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT … #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK … #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT … #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK … #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT … #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK … #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT … #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK … #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT … #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK … #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT … #define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK … #define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT … #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK … #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT … #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK … #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT … #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK … #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT … #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK … #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT … #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK … #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT … #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK … #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT … #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK … #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT … #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK … #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT … #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK … #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT … #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK … #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT … #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK … #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT … #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK … #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT … #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK … #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT … #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK … #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT … #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK … #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT … #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK … #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT … #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK … #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT … #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK … #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT … #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK … #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT … #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK … #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT … #define CP_STAT__CE_BUSY_MASK … #define CP_STAT__CE_BUSY__SHIFT … #define CP_STAT__CP_BUSY_MASK … #define CP_STAT__CP_BUSY__SHIFT … #define CP_STAT__CPC_CPG_BUSY_MASK … #define CP_STAT__CPC_CPG_BUSY__SHIFT … #define CP_STAT__DC_BUSY_MASK … #define CP_STAT__DC_BUSY__SHIFT … #define CP_STAT__DMA_BUSY_MASK … #define CP_STAT__DMA_BUSY__SHIFT … #define CP_STAT__INTERRUPT_BUSY_MASK … #define CP_STAT__INTERRUPT_BUSY__SHIFT … #define CP_STAT__ME_BUSY_MASK … #define CP_STAT__ME_BUSY__SHIFT … #define CP_STAT__MEQ_BUSY_MASK … #define CP_STAT__MEQ_BUSY__SHIFT … #define CP_STAT__MIU_RDREQ_BUSY_MASK … #define CP_STAT__MIU_RDREQ_BUSY__SHIFT … #define CP_STAT__MIU_WRREQ_BUSY_MASK … #define CP_STAT__MIU_WRREQ_BUSY__SHIFT … #define CP_STAT__PFP_BUSY_MASK … #define CP_STAT__PFP_BUSY__SHIFT … #define CP_STAT__QUERY_BUSY_MASK … #define CP_STAT__QUERY_BUSY__SHIFT … #define CP_STAT__RCIU_BUSY_MASK … #define CP_STAT__RCIU_BUSY__SHIFT … #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK … #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT … #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK … #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT … #define CP_STAT__ROQ_CE_RING_BUSY_MASK … #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT … #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK … #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT … #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK … #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT … #define CP_STAT__ROQ_RING_BUSY_MASK … #define CP_STAT__ROQ_RING_BUSY__SHIFT … #define CP_STAT__ROQ_STATE_BUSY_MASK … #define CP_STAT__ROQ_STATE_BUSY__SHIFT … #define CP_STAT__SCRATCH_RAM_BUSY_MASK … #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT … #define CP_STAT__SEMAPHORE_BUSY_MASK … #define CP_STAT__SEMAPHORE_BUSY__SHIFT … #define CP_STAT__SURFACE_SYNC_BUSY_MASK … #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT … #define CP_STAT__TCIU_BUSY_MASK … #define CP_STAT__TCIU_BUSY__SHIFT … #define CP_ST_BASE_HI__ST_BASE_HI_MASK … #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT … #define CP_ST_BASE_LO__ST_BASE_LO_MASK … #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT … #define CP_ST_BUFSZ__ST_BUFSZ_MASK … #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT … #define CP_STQ_AVAIL__STQ_CNT_MASK … #define CP_STQ_AVAIL__STQ_CNT__SHIFT … #define CP_STQ_STAT__STQ_RPTR_MASK … #define CP_STQ_STAT__STQ_RPTR__SHIFT … #define CP_STQ_THRESHOLDS__STQ0_START_MASK … #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT … #define CP_STQ_THRESHOLDS__STQ1_START_MASK … #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT … #define CP_STQ_THRESHOLDS__STQ2_START_MASK … #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT … #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK … #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT … #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK … #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT … #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK … #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT … #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK … #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT … #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK … #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT … #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK … #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT … #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK … #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT … #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK … #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT … #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK … #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT … #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK … #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT … #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK … #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT … #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK … #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT … #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK … #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT … #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK … #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT … #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK … #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT … #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK … #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT … #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK … #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT … #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK … #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT … #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK … #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT … #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK … #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT … #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK … #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT … #define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK … #define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT … #define CP_VMID_RESET__RESET_REQUEST_MASK … #define CP_VMID_RESET__RESET_REQUEST__SHIFT … #define CP_VMID_RESET__RESET_STATUS_MASK … #define CP_VMID_RESET__RESET_STATUS__SHIFT … #define CP_VMID__VMID_MASK … #define CP_VMID__VMID__SHIFT … #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK … #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT … #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK … #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT … #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK … #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT … #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK … #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK … #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT … #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK … #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT … #define CS_COPY_STATE__SRC_STATE_ID_MASK … #define CS_COPY_STATE__SRC_STATE_ID__SHIFT … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK … #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT … #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK … #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT … #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK … #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT … #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK … #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT … #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK … #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK … #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT … #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK … #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT … #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK … #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT … #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK … #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT … #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT … #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK … #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT … #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK … #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT … #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT … #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK … #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT … #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK … #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT … #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK … #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT … #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK … #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT … #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK … #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT … #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK … #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT … #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK … #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT … #define DB_DEBUG2__CLK_OFF_DELAY_MASK … #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT … #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK … #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT … #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK … #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT … #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK … #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT … #define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK … #define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT … #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK … #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK … #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT … #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT … #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK … #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT … #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK … #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT … #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK … #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT … #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK … #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT … #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK … #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT … #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK … #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT … #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK … #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT … #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK … #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT … #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK … #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT … #define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK … #define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT … #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK … #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT … #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK … #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT … #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK … #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT … #define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK … #define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT … #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK … #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT … #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK … #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT … #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK … #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT … #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK … #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT … #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK … #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT … #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK … #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT … #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK … #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT … #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK … #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT … #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK … #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT … #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK … #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT … #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK … #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT … #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK … #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT … #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK … #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT … #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK … #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT … #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK … #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT … #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK … #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT … #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK … #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT … #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK … #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT … #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK … #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT … #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK … #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT … #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK … #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT … #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK … #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT … #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK … #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT … #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK … #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT … #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK … #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT … #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK … #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT … #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK … #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT … #define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK … #define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT … #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK … #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT … #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK … #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT … #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK … #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT … #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK … #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT … #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK … #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT … #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK … #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT … #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK … #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT … #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK … #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT … #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK … #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT … #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK … #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT … #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK … #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT … #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK … #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT … #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK … #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT … #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK … #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT … #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK … #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT … #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK … #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT … #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK … #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT … #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK … #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT … #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK … #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT … #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK … #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT … #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK … #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT … #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK … #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT … #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK … #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT … #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK … #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT … #define DB_DEBUG__FORCE_Z_MODE_MASK … #define DB_DEBUG__FORCE_Z_MODE__SHIFT … #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK … #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT … #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK … #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT … #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK … #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT … #define DB_DEPTH_BOUNDS_MAX__MAX_MASK … #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT … #define DB_DEPTH_BOUNDS_MIN__MIN_MASK … #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT … #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK … #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT … #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK … #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT … #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK … #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT … #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK … #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT … #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK … #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT … #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK … #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT … #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK … #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT … #define DB_DEPTH_CONTROL__STENCILFUNC_MASK … #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT … #define DB_DEPTH_CONTROL__Z_ENABLE_MASK … #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT … #define DB_DEPTH_CONTROL__ZFUNC_MASK … #define DB_DEPTH_CONTROL__ZFUNC__SHIFT … #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK … #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT … #define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK … #define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT … #define DB_DEPTH_INFO__ARRAY_MODE_MASK … #define DB_DEPTH_INFO__ARRAY_MODE__SHIFT … #define DB_DEPTH_INFO__BANK_HEIGHT_MASK … #define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT … #define DB_DEPTH_INFO__BANK_WIDTH_MASK … #define DB_DEPTH_INFO__BANK_WIDTH__SHIFT … #define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK … #define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT … #define DB_DEPTH_INFO__NUM_BANKS_MASK … #define DB_DEPTH_INFO__NUM_BANKS__SHIFT … #define DB_DEPTH_INFO__PIPE_CONFIG_MASK … #define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT … #define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK … #define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT … #define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK … #define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT … #define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK … #define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT … #define DB_DEPTH_VIEW__SLICE_MAX_MASK … #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT … #define DB_DEPTH_VIEW__SLICE_START_MASK … #define DB_DEPTH_VIEW__SLICE_START__SHIFT … #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK … #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT … #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK … #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT … #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK … #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT … #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK … #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT … #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK … #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT … #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK … #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT … #define DB_EQAA__INCOHERENT_EQAA_READS_MASK … #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT … #define DB_EQAA__INTERPOLATE_COMP_Z_MASK … #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT … #define DB_EQAA__INTERPOLATE_SRC_Z_MASK … #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT … #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK … #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT … #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK … #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT … #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK … #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT … #define DB_EQAA__PS_ITER_SAMPLES_MASK … #define DB_EQAA__PS_ITER_SAMPLES__SHIFT … #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK … #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT … #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK … #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT … #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK … #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT … #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK … #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT … #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK … #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT … #define DB_FIFO_DEPTH1__QC_DEPTH_MASK … #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT … #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK … #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT … #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK … #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT … #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK … #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT … #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK … #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT … #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK … #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT … #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK … #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT … #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK … #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT … #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK … #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT … #define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK … #define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT … #define DB_HTILE_DATA_BASE__BASE_256B_MASK … #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT … #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK … #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT … #define DB_HTILE_SURFACE__FULL_CACHE_MASK … #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT … #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK … #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT … #define DB_HTILE_SURFACE__LINEAR_MASK … #define DB_HTILE_SURFACE__LINEAR__SHIFT … #define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK … #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT … #define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK … #define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT … #define DB_HTILE_SURFACE__PRELOAD_MASK … #define DB_HTILE_SURFACE__PRELOAD__SHIFT … #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK … #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT … #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK … #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT … #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK … #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT … #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK … #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT … #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK … #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK … #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT … #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK … #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT … #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK … #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT … #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK … #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT … #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK … #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT … #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK … #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT … #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK … #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT … #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK … #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT … #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK … #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT … #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK … #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT … #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK … #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT … #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define DB_PRELOAD_CONTROL__MAX_X_MASK … #define DB_PRELOAD_CONTROL__MAX_X__SHIFT … #define DB_PRELOAD_CONTROL__MAX_Y_MASK … #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT … #define DB_PRELOAD_CONTROL__START_X_MASK … #define DB_PRELOAD_CONTROL__START_X__SHIFT … #define DB_PRELOAD_CONTROL__START_Y_MASK … #define DB_PRELOAD_CONTROL__START_Y__SHIFT … #define DB_READ_DEBUG_0__BUSY_DATA0_MASK … #define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT … #define DB_READ_DEBUG_1__BUSY_DATA1_MASK … #define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT … #define DB_READ_DEBUG_2__BUSY_DATA2_MASK … #define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT … #define DB_READ_DEBUG_3__DEBUG_DATA_MASK … #define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_4__DEBUG_DATA_MASK … #define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_5__DEBUG_DATA_MASK … #define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_6__DEBUG_DATA_MASK … #define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_7__DEBUG_DATA_MASK … #define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_8__DEBUG_DATA_MASK … #define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_9__DEBUG_DATA_MASK … #define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_A__DEBUG_DATA_MASK … #define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_B__DEBUG_DATA_MASK … #define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_C__DEBUG_DATA_MASK … #define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_D__DEBUG_DATA_MASK … #define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_E__DEBUG_DATA_MASK … #define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT … #define DB_READ_DEBUG_F__DEBUG_DATA_MASK … #define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT … #define DB_RENDER_CONTROL__COPY_CENTROID_MASK … #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT … #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK … #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT … #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK … #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT … #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK … #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT … #define DB_RENDER_CONTROL__DEPTH_COPY_MASK … #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT … #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK … #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT … #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK … #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT … #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK … #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT … #define DB_RENDER_CONTROL__STENCIL_COPY_MASK … #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT … #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK … #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT … #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK … #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT … #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK … #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT … #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK … #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT … #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK … #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT … #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK … #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT … #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK … #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT … #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK … #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT … #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK … #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT … #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK … #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT … #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK … #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT … #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK … #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT … #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK … #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT … #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK … #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT … #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK … #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT … #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK … #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT … #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK … #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT … #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK … #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT … #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK … #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT … #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK … #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK … #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK … #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK … #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK … #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK … #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK … #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK … #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK … #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK … #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK … #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK … #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK … #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK … #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT … #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK … #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT … #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK … #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT … #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK … #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT … #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK … #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT … #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK … #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT … #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK … #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT … #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK … #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT … #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK … #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT … #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK … #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT … #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK … #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT … #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK … #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT … #define DB_SHADER_CONTROL__KILL_ENABLE_MASK … #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT … #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK … #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT … #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK … #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT … #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK … #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT … #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK … #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT … #define DB_SHADER_CONTROL__Z_ORDER_MASK … #define DB_SHADER_CONTROL__Z_ORDER__SHIFT … #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK … #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT … #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK … #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT … #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK … #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT … #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK … #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT … #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK … #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT … #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK … #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT … #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK … #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT … #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK … #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT … #define DB_STENCIL_CLEAR__CLEAR_MASK … #define DB_STENCIL_CLEAR__CLEAR__SHIFT … #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK … #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT … #define DB_STENCIL_CONTROL__STENCILFAIL_MASK … #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT … #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK … #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT … #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK … #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT … #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK … #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT … #define DB_STENCIL_CONTROL__STENCILZPASS_MASK … #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT … #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK … #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT … #define DB_STENCIL_INFO__FORMAT_MASK … #define DB_STENCIL_INFO__FORMAT__SHIFT … #define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK … #define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT … #define DB_STENCIL_INFO__TILE_SPLIT_MASK … #define DB_STENCIL_INFO__TILE_SPLIT__SHIFT … #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK … #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT … #define DB_STENCIL_READ_BASE__BASE_256B_MASK … #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT … #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK … #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT … #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK … #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT … #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK … #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT … #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK … #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT … #define DB_STENCILREFMASK__STENCILMASK_MASK … #define DB_STENCILREFMASK__STENCILMASK__SHIFT … #define DB_STENCILREFMASK__STENCILOPVAL_MASK … #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT … #define DB_STENCILREFMASK__STENCILTESTVAL_MASK … #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT … #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK … #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT … #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK … #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT … #define DB_SUBTILE_CONTROL__MSAA16_X_MASK … #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT … #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK … #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT … #define DB_SUBTILE_CONTROL__MSAA1_X_MASK … #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT … #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK … #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT … #define DB_SUBTILE_CONTROL__MSAA2_X_MASK … #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT … #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK … #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT … #define DB_SUBTILE_CONTROL__MSAA4_X_MASK … #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT … #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK … #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT … #define DB_SUBTILE_CONTROL__MSAA8_X_MASK … #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT … #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK … #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT … #define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK … #define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT … #define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK … #define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT … #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK … #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT … #define DB_WATERMARKS__DEPTH_FLUSH_MASK … #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT … #define DB_WATERMARKS__DEPTH_FREE_MASK … #define DB_WATERMARKS__DEPTH_FREE__SHIFT … #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK … #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT … #define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK … #define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT … #define DB_WATERMARKS__FORCE_SUMMARIZE_MASK … #define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT … #define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK … #define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT … #define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK … #define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT … #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK … #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT … #define DB_Z_INFO__FORMAT_MASK … #define DB_Z_INFO__FORMAT__SHIFT … #define DB_Z_INFO__NUM_SAMPLES_MASK … #define DB_Z_INFO__NUM_SAMPLES__SHIFT … #define DB_Z_INFO__READ_SIZE_MASK … #define DB_Z_INFO__READ_SIZE__SHIFT … #define DB_Z_INFO__TILE_MODE_INDEX_MASK … #define DB_Z_INFO__TILE_MODE_INDEX__SHIFT … #define DB_Z_INFO__TILE_SPLIT_MASK … #define DB_Z_INFO__TILE_SPLIT__SHIFT … #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK … #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT … #define DB_Z_INFO__ZRANGE_PRECISION_MASK … #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT … #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK … #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT … #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK … #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT … #define DB_Z_READ_BASE__BASE_256B_MASK … #define DB_Z_READ_BASE__BASE_256B__SHIFT … #define DB_Z_WRITE_BASE__BASE_256B_MASK … #define DB_Z_WRITE_BASE__BASE_256B__SHIFT … #define DEBUG_DATA__DEBUG_DATA_MASK … #define DEBUG_DATA__DEBUG_DATA__SHIFT … #define DEBUG_INDEX__DEBUG_INDEX_MASK … #define DEBUG_INDEX__DEBUG_INDEX__SHIFT … #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK … #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT … #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK … #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT … #define GB_ADDR_CONFIG__NUM_GPUS_MASK … #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT … #define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK … #define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT … #define GB_ADDR_CONFIG__NUM_PIPES_MASK … #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT … #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK … #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT … #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK … #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT … #define GB_ADDR_CONFIG__ROW_SIZE_MASK … #define GB_ADDR_CONFIG__ROW_SIZE__SHIFT … #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK … #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT … #define GB_BACKEND_MAP__BACKEND_MAP_MASK … #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT … #define GB_EDC_MODE__BYPASS_MASK … #define GB_EDC_MODE__BYPASS__SHIFT … #define GB_EDC_MODE__DED_MODE_MASK … #define GB_EDC_MODE__DED_MODE__SHIFT … #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK … #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT … #define GB_EDC_MODE__PROP_FED_MASK … #define GB_EDC_MODE__PROP_FED__SHIFT … #define GB_GPU_ID__GPU_ID_MASK … #define GB_GPU_ID__GPU_ID__SHIFT … #define GB_TILE_MODE0__ARRAY_MODE_MASK … #define GB_TILE_MODE0__ARRAY_MODE__SHIFT … #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE0__PIPE_CONFIG_MASK … #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE0__TILE_SPLIT_MASK … #define GB_TILE_MODE0__TILE_SPLIT__SHIFT … #define GB_TILE_MODE10__ARRAY_MODE_MASK … #define GB_TILE_MODE10__ARRAY_MODE__SHIFT … #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE10__PIPE_CONFIG_MASK … #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE10__TILE_SPLIT_MASK … #define GB_TILE_MODE10__TILE_SPLIT__SHIFT … #define GB_TILE_MODE11__ARRAY_MODE_MASK … #define GB_TILE_MODE11__ARRAY_MODE__SHIFT … #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE11__PIPE_CONFIG_MASK … #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE11__TILE_SPLIT_MASK … #define GB_TILE_MODE11__TILE_SPLIT__SHIFT … #define GB_TILE_MODE12__ARRAY_MODE_MASK … #define GB_TILE_MODE12__ARRAY_MODE__SHIFT … #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE12__PIPE_CONFIG_MASK … #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE12__TILE_SPLIT_MASK … #define GB_TILE_MODE12__TILE_SPLIT__SHIFT … #define GB_TILE_MODE13__ARRAY_MODE_MASK … #define GB_TILE_MODE13__ARRAY_MODE__SHIFT … #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE13__PIPE_CONFIG_MASK … #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE13__TILE_SPLIT_MASK … #define GB_TILE_MODE13__TILE_SPLIT__SHIFT … #define GB_TILE_MODE14__ARRAY_MODE_MASK … #define GB_TILE_MODE14__ARRAY_MODE__SHIFT … #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE14__PIPE_CONFIG_MASK … #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE14__TILE_SPLIT_MASK … #define GB_TILE_MODE14__TILE_SPLIT__SHIFT … #define GB_TILE_MODE15__ARRAY_MODE_MASK … #define GB_TILE_MODE15__ARRAY_MODE__SHIFT … #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE15__PIPE_CONFIG_MASK … #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE15__TILE_SPLIT_MASK … #define GB_TILE_MODE15__TILE_SPLIT__SHIFT … #define GB_TILE_MODE16__ARRAY_MODE_MASK … #define GB_TILE_MODE16__ARRAY_MODE__SHIFT … #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE16__PIPE_CONFIG_MASK … #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE16__TILE_SPLIT_MASK … #define GB_TILE_MODE16__TILE_SPLIT__SHIFT … #define GB_TILE_MODE17__ARRAY_MODE_MASK … #define GB_TILE_MODE17__ARRAY_MODE__SHIFT … #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE17__PIPE_CONFIG_MASK … #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE17__TILE_SPLIT_MASK … #define GB_TILE_MODE17__TILE_SPLIT__SHIFT … #define GB_TILE_MODE18__ARRAY_MODE_MASK … #define GB_TILE_MODE18__ARRAY_MODE__SHIFT … #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE18__PIPE_CONFIG_MASK … #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE18__TILE_SPLIT_MASK … #define GB_TILE_MODE18__TILE_SPLIT__SHIFT … #define GB_TILE_MODE19__ARRAY_MODE_MASK … #define GB_TILE_MODE19__ARRAY_MODE__SHIFT … #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE19__PIPE_CONFIG_MASK … #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE19__TILE_SPLIT_MASK … #define GB_TILE_MODE19__TILE_SPLIT__SHIFT … #define GB_TILE_MODE1__ARRAY_MODE_MASK … #define GB_TILE_MODE1__ARRAY_MODE__SHIFT … #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE1__PIPE_CONFIG_MASK … #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE1__TILE_SPLIT_MASK … #define GB_TILE_MODE1__TILE_SPLIT__SHIFT … #define GB_TILE_MODE20__ARRAY_MODE_MASK … #define GB_TILE_MODE20__ARRAY_MODE__SHIFT … #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE20__PIPE_CONFIG_MASK … #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE20__TILE_SPLIT_MASK … #define GB_TILE_MODE20__TILE_SPLIT__SHIFT … #define GB_TILE_MODE21__ARRAY_MODE_MASK … #define GB_TILE_MODE21__ARRAY_MODE__SHIFT … #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE21__PIPE_CONFIG_MASK … #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE21__TILE_SPLIT_MASK … #define GB_TILE_MODE21__TILE_SPLIT__SHIFT … #define GB_TILE_MODE22__ARRAY_MODE_MASK … #define GB_TILE_MODE22__ARRAY_MODE__SHIFT … #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE22__PIPE_CONFIG_MASK … #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE22__TILE_SPLIT_MASK … #define GB_TILE_MODE22__TILE_SPLIT__SHIFT … #define GB_TILE_MODE23__ARRAY_MODE_MASK … #define GB_TILE_MODE23__ARRAY_MODE__SHIFT … #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE23__PIPE_CONFIG_MASK … #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE23__TILE_SPLIT_MASK … #define GB_TILE_MODE23__TILE_SPLIT__SHIFT … #define GB_TILE_MODE24__ARRAY_MODE_MASK … #define GB_TILE_MODE24__ARRAY_MODE__SHIFT … #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE24__PIPE_CONFIG_MASK … #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE24__TILE_SPLIT_MASK … #define GB_TILE_MODE24__TILE_SPLIT__SHIFT … #define GB_TILE_MODE25__ARRAY_MODE_MASK … #define GB_TILE_MODE25__ARRAY_MODE__SHIFT … #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE25__PIPE_CONFIG_MASK … #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE25__TILE_SPLIT_MASK … #define GB_TILE_MODE25__TILE_SPLIT__SHIFT … #define GB_TILE_MODE26__ARRAY_MODE_MASK … #define GB_TILE_MODE26__ARRAY_MODE__SHIFT … #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE26__PIPE_CONFIG_MASK … #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE26__TILE_SPLIT_MASK … #define GB_TILE_MODE26__TILE_SPLIT__SHIFT … #define GB_TILE_MODE27__ARRAY_MODE_MASK … #define GB_TILE_MODE27__ARRAY_MODE__SHIFT … #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE27__PIPE_CONFIG_MASK … #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE27__TILE_SPLIT_MASK … #define GB_TILE_MODE27__TILE_SPLIT__SHIFT … #define GB_TILE_MODE28__ARRAY_MODE_MASK … #define GB_TILE_MODE28__ARRAY_MODE__SHIFT … #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE28__PIPE_CONFIG_MASK … #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE28__TILE_SPLIT_MASK … #define GB_TILE_MODE28__TILE_SPLIT__SHIFT … #define GB_TILE_MODE29__ARRAY_MODE_MASK … #define GB_TILE_MODE29__ARRAY_MODE__SHIFT … #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE29__PIPE_CONFIG_MASK … #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE29__TILE_SPLIT_MASK … #define GB_TILE_MODE29__TILE_SPLIT__SHIFT … #define GB_TILE_MODE2__ARRAY_MODE_MASK … #define GB_TILE_MODE2__ARRAY_MODE__SHIFT … #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE2__PIPE_CONFIG_MASK … #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE2__TILE_SPLIT_MASK … #define GB_TILE_MODE2__TILE_SPLIT__SHIFT … #define GB_TILE_MODE30__ARRAY_MODE_MASK … #define GB_TILE_MODE30__ARRAY_MODE__SHIFT … #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE30__PIPE_CONFIG_MASK … #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE30__TILE_SPLIT_MASK … #define GB_TILE_MODE30__TILE_SPLIT__SHIFT … #define GB_TILE_MODE31__ARRAY_MODE_MASK … #define GB_TILE_MODE31__ARRAY_MODE__SHIFT … #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE31__PIPE_CONFIG_MASK … #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE31__TILE_SPLIT_MASK … #define GB_TILE_MODE31__TILE_SPLIT__SHIFT … #define GB_TILE_MODE3__ARRAY_MODE_MASK … #define GB_TILE_MODE3__ARRAY_MODE__SHIFT … #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE3__PIPE_CONFIG_MASK … #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE3__TILE_SPLIT_MASK … #define GB_TILE_MODE3__TILE_SPLIT__SHIFT … #define GB_TILE_MODE4__ARRAY_MODE_MASK … #define GB_TILE_MODE4__ARRAY_MODE__SHIFT … #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE4__PIPE_CONFIG_MASK … #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE4__TILE_SPLIT_MASK … #define GB_TILE_MODE4__TILE_SPLIT__SHIFT … #define GB_TILE_MODE5__ARRAY_MODE_MASK … #define GB_TILE_MODE5__ARRAY_MODE__SHIFT … #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE5__PIPE_CONFIG_MASK … #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE5__TILE_SPLIT_MASK … #define GB_TILE_MODE5__TILE_SPLIT__SHIFT … #define GB_TILE_MODE6__ARRAY_MODE_MASK … #define GB_TILE_MODE6__ARRAY_MODE__SHIFT … #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE6__PIPE_CONFIG_MASK … #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE6__TILE_SPLIT_MASK … #define GB_TILE_MODE6__TILE_SPLIT__SHIFT … #define GB_TILE_MODE7__ARRAY_MODE_MASK … #define GB_TILE_MODE7__ARRAY_MODE__SHIFT … #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE7__PIPE_CONFIG_MASK … #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE7__TILE_SPLIT_MASK … #define GB_TILE_MODE7__TILE_SPLIT__SHIFT … #define GB_TILE_MODE8__ARRAY_MODE_MASK … #define GB_TILE_MODE8__ARRAY_MODE__SHIFT … #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE8__PIPE_CONFIG_MASK … #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE8__TILE_SPLIT_MASK … #define GB_TILE_MODE8__TILE_SPLIT__SHIFT … #define GB_TILE_MODE9__ARRAY_MODE_MASK … #define GB_TILE_MODE9__ARRAY_MODE__SHIFT … #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK … #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT … #define GB_TILE_MODE9__PIPE_CONFIG_MASK … #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT … #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK … #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT … #define GB_TILE_MODE9__TILE_SPLIT_MASK … #define GB_TILE_MODE9__TILE_SPLIT__SHIFT … #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK … #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT … #define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK … #define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT … #define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK … #define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT … #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK … #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT … #define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK … #define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT … #define GDS_ATOM_BASE__BASE_MASK … #define GDS_ATOM_BASE__BASE__SHIFT … #define GDS_ATOM_BASE__UNUSED_MASK … #define GDS_ATOM_BASE__UNUSED__SHIFT … #define GDS_ATOM_CNTL__AINC_MASK … #define GDS_ATOM_CNTL__AINC__SHIFT … #define GDS_ATOM_CNTL__DMODE_MASK … #define GDS_ATOM_CNTL__DMODE__SHIFT … #define GDS_ATOM_CNTL__UNUSED1_MASK … #define GDS_ATOM_CNTL__UNUSED1__SHIFT … #define GDS_ATOM_CNTL__UNUSED2_MASK … #define GDS_ATOM_CNTL__UNUSED2__SHIFT … #define GDS_ATOM_COMPLETE__COMPLETE_MASK … #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT … #define GDS_ATOM_COMPLETE__UNUSED_MASK … #define GDS_ATOM_COMPLETE__UNUSED__SHIFT … #define GDS_ATOM_DST__DST_MASK … #define GDS_ATOM_DST__DST__SHIFT … #define GDS_ATOM_OFFSET0__OFFSET0_MASK … #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT … #define GDS_ATOM_OFFSET0__UNUSED_MASK … #define GDS_ATOM_OFFSET0__UNUSED__SHIFT … #define GDS_ATOM_OFFSET1__OFFSET1_MASK … #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT … #define GDS_ATOM_OFFSET1__UNUSED_MASK … #define GDS_ATOM_OFFSET1__UNUSED__SHIFT … #define GDS_ATOM_OP__OP_MASK … #define GDS_ATOM_OP__OP__SHIFT … #define GDS_ATOM_OP__UNUSED_MASK … #define GDS_ATOM_OP__UNUSED__SHIFT … #define GDS_ATOM_READ0__DATA_MASK … #define GDS_ATOM_READ0__DATA__SHIFT … #define GDS_ATOM_READ0_U__DATA_MASK … #define GDS_ATOM_READ0_U__DATA__SHIFT … #define GDS_ATOM_READ1__DATA_MASK … #define GDS_ATOM_READ1__DATA__SHIFT … #define GDS_ATOM_READ1_U__DATA_MASK … #define GDS_ATOM_READ1_U__DATA__SHIFT … #define GDS_ATOM_SIZE__SIZE_MASK … #define GDS_ATOM_SIZE__SIZE__SHIFT … #define GDS_ATOM_SIZE__UNUSED_MASK … #define GDS_ATOM_SIZE__UNUSED__SHIFT … #define GDS_ATOM_SRC0__DATA_MASK … #define GDS_ATOM_SRC0__DATA__SHIFT … #define GDS_ATOM_SRC0_U__DATA_MASK … #define GDS_ATOM_SRC0_U__DATA__SHIFT … #define GDS_ATOM_SRC1__DATA_MASK … #define GDS_ATOM_SRC1__DATA__SHIFT … #define GDS_ATOM_SRC1_U__DATA_MASK … #define GDS_ATOM_SRC1_U__DATA__SHIFT … #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK … #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT … #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK … #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT … #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK … #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT … #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK … #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT … #define GDS_CNTL_STATUS__GDS_BUSY_MASK … #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT … #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK … #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT … #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK … #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT … #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK … #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT … #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK … #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT … #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK … #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT … #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK … #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT … #define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK … #define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT … #define GDS_DEBUG_CNTL__UNUSED_MASK … #define GDS_DEBUG_CNTL__UNUSED__SHIFT … #define GDS_DEBUG_DATA__DATA_MASK … #define GDS_DEBUG_DATA__DATA__SHIFT … #define GDS_DEBUG_REG0__buff_write_MASK … #define GDS_DEBUG_REG0__buff_write__SHIFT … #define GDS_DEBUG_REG0__cstate_MASK … #define GDS_DEBUG_REG0__cstate__SHIFT … #define GDS_DEBUG_REG0__flush_request_MASK … #define GDS_DEBUG_REG0__flush_request__SHIFT … #define GDS_DEBUG_REG0__last_pixel_ptr_MASK … #define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT … #define GDS_DEBUG_REG0__spare1_MASK … #define GDS_DEBUG_REG0__spare1__SHIFT … #define GDS_DEBUG_REG0__spare_MASK … #define GDS_DEBUG_REG0__spare__SHIFT … #define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK … #define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT … #define GDS_DEBUG_REG0__wbuf_fifo_full_MASK … #define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT … #define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK … #define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT … #define GDS_DEBUG_REG0__write_buff_valid_MASK … #define GDS_DEBUG_REG0__write_buff_valid__SHIFT … #define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK … #define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT … #define GDS_DEBUG_REG1__addr_fifo_empty_MASK … #define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT … #define GDS_DEBUG_REG1__addr_fifo_full_MASK … #define GDS_DEBUG_REG1__addr_fifo_full__SHIFT … #define GDS_DEBUG_REG1__awaiting_data_MASK … #define GDS_DEBUG_REG1__awaiting_data__SHIFT … #define GDS_DEBUG_REG1__buffer_invalid_MASK … #define GDS_DEBUG_REG1__buffer_invalid__SHIFT … #define GDS_DEBUG_REG1__buffer_loaded_MASK … #define GDS_DEBUG_REG1__buffer_loaded__SHIFT … #define GDS_DEBUG_REG1__data_ready_MASK … #define GDS_DEBUG_REG1__data_ready__SHIFT … #define GDS_DEBUG_REG1__pixel_addr_MASK … #define GDS_DEBUG_REG1__pixel_addr__SHIFT … #define GDS_DEBUG_REG1__pixel_vld_MASK … #define GDS_DEBUG_REG1__pixel_vld__SHIFT … #define GDS_DEBUG_REG1__spare_MASK … #define GDS_DEBUG_REG1__spare__SHIFT … #define GDS_DEBUG_REG1__tag_hit_MASK … #define GDS_DEBUG_REG1__tag_hit__SHIFT … #define GDS_DEBUG_REG1__tag_miss_MASK … #define GDS_DEBUG_REG1__tag_miss__SHIFT … #define GDS_DEBUG_REG2__app_sel_MASK … #define GDS_DEBUG_REG2__app_sel__SHIFT … #define GDS_DEBUG_REG2__cmd_write_MASK … #define GDS_DEBUG_REG2__cmd_write__SHIFT … #define GDS_DEBUG_REG2__ds_credit_avail_MASK … #define GDS_DEBUG_REG2__ds_credit_avail__SHIFT … #define GDS_DEBUG_REG2__ds_full_MASK … #define GDS_DEBUG_REG2__ds_full__SHIFT … #define GDS_DEBUG_REG2__ord_idx_free_MASK … #define GDS_DEBUG_REG2__ord_idx_free__SHIFT … #define GDS_DEBUG_REG2__req_MASK … #define GDS_DEBUG_REG2__req__SHIFT … #define GDS_DEBUG_REG2__spare_MASK … #define GDS_DEBUG_REG2__spare__SHIFT … #define GDS_DEBUG_REG3__pipe0_busy_num_MASK … #define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT … #define GDS_DEBUG_REG3__pipe_num_busy_MASK … #define GDS_DEBUG_REG3__pipe_num_busy__SHIFT … #define GDS_DEBUG_REG3__spare_MASK … #define GDS_DEBUG_REG3__spare__SHIFT … #define GDS_DEBUG_REG4__cmd_write_MASK … #define GDS_DEBUG_REG4__cmd_write__SHIFT … #define GDS_DEBUG_REG4__credit_cnt_gt0_MASK … #define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT … #define GDS_DEBUG_REG4__cur_reso_barrier_MASK … #define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT … #define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK … #define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT … #define GDS_DEBUG_REG4__cur_reso_fed_MASK … #define GDS_DEBUG_REG4__cur_reso_fed__SHIFT … #define GDS_DEBUG_REG4__cur_reso_flag_MASK … #define GDS_DEBUG_REG4__cur_reso_flag__SHIFT … #define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK … #define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT … #define GDS_DEBUG_REG4__cur_reso_head_flag_MASK … #define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT … #define GDS_DEBUG_REG4__cur_reso_head_valid_MASK … #define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT … #define GDS_DEBUG_REG4__cur_reso_MASK … #define GDS_DEBUG_REG4__cur_reso__SHIFT … #define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK … #define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT … #define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK … #define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT … #define GDS_DEBUG_REG4__gws_bulkfree_MASK … #define GDS_DEBUG_REG4__gws_bulkfree__SHIFT … #define GDS_DEBUG_REG4__gws_busy_MASK … #define GDS_DEBUG_REG4__gws_busy__SHIFT … #define GDS_DEBUG_REG4__gws_out_stall_MASK … #define GDS_DEBUG_REG4__gws_out_stall__SHIFT … #define GDS_DEBUG_REG4__gws_req_MASK … #define GDS_DEBUG_REG4__gws_req__SHIFT … #define GDS_DEBUG_REG4__ram_gws_re_MASK … #define GDS_DEBUG_REG4__ram_gws_re__SHIFT … #define GDS_DEBUG_REG4__ram_gws_we_MASK … #define GDS_DEBUG_REG4__ram_gws_we__SHIFT … #define GDS_DEBUG_REG4__ram_read_busy_MASK … #define GDS_DEBUG_REG4__ram_read_busy__SHIFT … #define GDS_DEBUG_REG4__spare_MASK … #define GDS_DEBUG_REG4__spare__SHIFT … #define GDS_DEBUG_REG5__alloc_opco_error_MASK … #define GDS_DEBUG_REG5__alloc_opco_error__SHIFT … #define GDS_DEBUG_REG5__dealloc_opco_error_MASK … #define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT … #define GDS_DEBUG_REG5__dec_error_MASK … #define GDS_DEBUG_REG5__dec_error__SHIFT … #define GDS_DEBUG_REG5__error_ds_address_MASK … #define GDS_DEBUG_REG5__error_ds_address__SHIFT … #define GDS_DEBUG_REG5__spare1_MASK … #define GDS_DEBUG_REG5__spare1__SHIFT … #define GDS_DEBUG_REG5__spare_MASK … #define GDS_DEBUG_REG5__spare__SHIFT … #define GDS_DEBUG_REG5__wrap_opco_error_MASK … #define GDS_DEBUG_REG5__wrap_opco_error__SHIFT … #define GDS_DEBUG_REG5__write_dis_MASK … #define GDS_DEBUG_REG5__write_dis__SHIFT … #define GDS_DEBUG_REG6__counters_busy_MASK … #define GDS_DEBUG_REG6__counters_busy__SHIFT … #define GDS_DEBUG_REG6__counters_enabled_MASK … #define GDS_DEBUG_REG6__counters_enabled__SHIFT … #define GDS_DEBUG_REG6__oa_busy_MASK … #define GDS_DEBUG_REG6__oa_busy__SHIFT … #define GDS_DEBUG_REG6__spare_MASK … #define GDS_DEBUG_REG6__spare__SHIFT … #define GDS_ENHANCE__AUTO_INC_INDEX_MASK … #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT … #define GDS_ENHANCE__MISC_MASK … #define GDS_ENHANCE__MISC__SHIFT … #define GDS_ENHANCE__UNUSED_MASK … #define GDS_ENHANCE__UNUSED__SHIFT … #define GDS_GRBM_SECDED_CNT__DED_MASK … #define GDS_GRBM_SECDED_CNT__DED__SHIFT … #define GDS_GRBM_SECDED_CNT__SEC_MASK … #define GDS_GRBM_SECDED_CNT__SEC__SHIFT … #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK … #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT … #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK … #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT … #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK … #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT … #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK … #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT … #define GDS_GWS_RESOURCE__COUNTER_MASK … #define GDS_GWS_RESOURCE__COUNTER__SHIFT … #define GDS_GWS_RESOURCE__DED_MASK … #define GDS_GWS_RESOURCE__DED__SHIFT … #define GDS_GWS_RESOURCE__FLAG_MASK … #define GDS_GWS_RESOURCE__FLAG__SHIFT … #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK … #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT … #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK … #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT … #define GDS_GWS_RESOURCE__HEAD_VALID_MASK … #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT … #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK … #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT … #define GDS_GWS_RESOURCE_RESET__RESET_MASK … #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT … #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK … #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT … #define GDS_GWS_RESOURCE__TYPE_MASK … #define GDS_GWS_RESOURCE__TYPE__SHIFT … #define GDS_GWS_RESOURCE__UNUSED1_MASK … #define GDS_GWS_RESOURCE__UNUSED1__SHIFT … #define GDS_OA_DED__ME0_CS_DED_MASK … #define GDS_OA_DED__ME0_CS_DED__SHIFT … #define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK … #define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT … #define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK … #define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT … #define GDS_OA_DED__ME1_PIPE0_DED_MASK … #define GDS_OA_DED__ME1_PIPE0_DED__SHIFT … #define GDS_OA_DED__ME1_PIPE1_DED_MASK … #define GDS_OA_DED__ME1_PIPE1_DED__SHIFT … #define GDS_OA_DED__ME1_PIPE2_DED_MASK … #define GDS_OA_DED__ME1_PIPE2_DED__SHIFT … #define GDS_OA_DED__ME1_PIPE3_DED_MASK … #define GDS_OA_DED__ME1_PIPE3_DED__SHIFT … #define GDS_OA_DED__ME2_PIPE0_DED_MASK … #define GDS_OA_DED__ME2_PIPE0_DED__SHIFT … #define GDS_OA_DED__ME2_PIPE1_DED_MASK … #define GDS_OA_DED__ME2_PIPE1_DED__SHIFT … #define GDS_OA_DED__ME2_PIPE2_DED_MASK … #define GDS_OA_DED__ME2_PIPE2_DED__SHIFT … #define GDS_OA_DED__ME2_PIPE3_DED_MASK … #define GDS_OA_DED__ME2_PIPE3_DED__SHIFT … #define GDS_OA_DED__UNUSED0_MASK … #define GDS_OA_DED__UNUSED0__SHIFT … #define GDS_OA_DED__UNUSED1_MASK … #define GDS_OA_DED__UNUSED1__SHIFT … #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK … #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT … #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK … #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT … #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK … #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT … #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK … #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT … #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK … #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT … #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK … #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT … #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK … #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT … #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK … #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT … #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK … #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT … #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK … #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT … #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK … #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT … #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK … #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT … #define GDS_RD_ADDR__READ_ADDR_MASK … #define GDS_RD_ADDR__READ_ADDR__SHIFT … #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK … #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT … #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK … #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT … #define GDS_RD_BURST_DATA__BURST_DATA_MASK … #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT … #define GDS_RD_DATA__READ_DATA_MASK … #define GDS_RD_DATA__READ_DATA__SHIFT … #define GDS_SECDED_CNT__DED_MASK … #define GDS_SECDED_CNT__DED__SHIFT … #define GDS_SECDED_CNT__SEC_MASK … #define GDS_SECDED_CNT__SEC__SHIFT … #define GDS_WR_ADDR__WRITE_ADDR_MASK … #define GDS_WR_ADDR__WRITE_ADDR__SHIFT … #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK … #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT … #define GDS_WR_BURST_DATA__WRITE_DATA_MASK … #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT … #define GDS_WR_DATA__WRITE_DATA_MASK … #define GDS_WR_DATA__WRITE_DATA__SHIFT … #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK … #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT … #define GFX_COPY_STATE__SRC_STATE_ID_MASK … #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT … #define GRBM_CAM_DATA__CAM_ADDR_MASK … #define GRBM_CAM_DATA__CAM_ADDR__SHIFT … #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK … #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT … #define GRBM_CAM_INDEX__CAM_INDEX_MASK … #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT … #define GRBM_CNTL__READ_TIMEOUT_MASK … #define GRBM_CNTL__READ_TIMEOUT__SHIFT … #define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK … #define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT … #define GRBM_DEBUG_DATA__DATA_MASK … #define GRBM_DEBUG_DATA__DATA__SHIFT … #define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK … #define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT … #define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK … #define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT … #define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK … #define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT … #define GRBM_DEBUG__IGNORE_FAO_MASK … #define GRBM_DEBUG__IGNORE_FAO__SHIFT … #define GRBM_DEBUG__IGNORE_RDY_MASK … #define GRBM_DEBUG__IGNORE_RDY__SHIFT … #define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK … #define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT … #define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK … #define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT … #define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK … #define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT … #define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK … #define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK … #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK … #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK … #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK … #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK … #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK … #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK … #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK … #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK … #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK … #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK … #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK … #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK … #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK … #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK … #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK … #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT … #define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK … #define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT … #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK … #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT … #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK … #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT … #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK … #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT … #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK … #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT … #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK … #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT … #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK … #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT … #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK … #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT … #define GRBM_GFX_INDEX__SE_INDEX_MASK … #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK … #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT … #define GRBM_GFX_INDEX__SH_INDEX_MASK … #define GRBM_GFX_INDEX__SH_INDEX__SHIFT … #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK … #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT … #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK … #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT … #define GRBM_NOWHERE__DATA_MASK … #define GRBM_NOWHERE__DATA__SHIFT … #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_PWR_CNTL__REQ_TYPE_MASK … #define GRBM_PWR_CNTL__REQ_TYPE__SHIFT … #define GRBM_PWR_CNTL__RSP_TYPE_MASK … #define GRBM_PWR_CNTL__RSP_TYPE__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT … #define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK … #define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT … #define GRBM_READ_ERROR__READ_ADDRESS_MASK … #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT … #define GRBM_READ_ERROR__READ_ERROR_MASK … #define GRBM_READ_ERROR__READ_ERROR__SHIFT … #define GRBM_READ_ERROR__READ_MEID_MASK … #define GRBM_READ_ERROR__READ_MEID__SHIFT … #define GRBM_READ_ERROR__READ_PIPEID_MASK … #define GRBM_READ_ERROR__READ_PIPEID__SHIFT … #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK … #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT … #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK … #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT … #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK … #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT … #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK … #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT … #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK … #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT … #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK … #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT … #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK … #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT … #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK … #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT … #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK … #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT … #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK … #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK … #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT … #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK … #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK … #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT … #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK … #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT … #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK … #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT … #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK … #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT … #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK … #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT … #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK … #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT … #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK … #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT … #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK … #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT … #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK … #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT … #define GRBM_STATUS2__CPC_BUSY_MASK … #define GRBM_STATUS2__CPC_BUSY__SHIFT … #define GRBM_STATUS2__CPF_BUSY_MASK … #define GRBM_STATUS2__CPF_BUSY__SHIFT … #define GRBM_STATUS2__CPG_BUSY_MASK … #define GRBM_STATUS2__CPG_BUSY__SHIFT … #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK … #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK … #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT … #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK … #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK … #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK … #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK … #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK … #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK … #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK … #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK … #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT … #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK … #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT … #define GRBM_STATUS2__RLC_BUSY_MASK … #define GRBM_STATUS2__RLC_BUSY__SHIFT … #define GRBM_STATUS2__RLC_RQ_PENDING_MASK … #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT … #define GRBM_STATUS2__TC_BUSY_MASK … #define GRBM_STATUS2__TC_BUSY__SHIFT … #define GRBM_STATUS__BCI_BUSY_MASK … #define GRBM_STATUS__BCI_BUSY__SHIFT … #define GRBM_STATUS__CB_BUSY_MASK … #define GRBM_STATUS__CB_BUSY__SHIFT … #define GRBM_STATUS__CB_CLEAN_MASK … #define GRBM_STATUS__CB_CLEAN__SHIFT … #define GRBM_STATUS__CP_BUSY_MASK … #define GRBM_STATUS__CP_BUSY__SHIFT … #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK … #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT … #define GRBM_STATUS__DB_BUSY_MASK … #define GRBM_STATUS__DB_BUSY__SHIFT … #define GRBM_STATUS__DB_CLEAN_MASK … #define GRBM_STATUS__DB_CLEAN__SHIFT … #define GRBM_STATUS__GDS_BUSY_MASK … #define GRBM_STATUS__GDS_BUSY__SHIFT … #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK … #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT … #define GRBM_STATUS__GUI_ACTIVE_MASK … #define GRBM_STATUS__GUI_ACTIVE__SHIFT … #define GRBM_STATUS__IA_BUSY_MASK … #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK … #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT … #define GRBM_STATUS__IA_BUSY__SHIFT … #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK … #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT … #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK … #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT … #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK … #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT … #define GRBM_STATUS__PA_BUSY_MASK … #define GRBM_STATUS__PA_BUSY__SHIFT … #define GRBM_STATUS__SC_BUSY_MASK … #define GRBM_STATUS__SC_BUSY__SHIFT … #define GRBM_STATUS_SE0__BCI_BUSY_MASK … #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT … #define GRBM_STATUS_SE0__CB_BUSY_MASK … #define GRBM_STATUS_SE0__CB_BUSY__SHIFT … #define GRBM_STATUS_SE0__CB_CLEAN_MASK … #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT … #define GRBM_STATUS_SE0__DB_BUSY_MASK … #define GRBM_STATUS_SE0__DB_BUSY__SHIFT … #define GRBM_STATUS_SE0__DB_CLEAN_MASK … #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT … #define GRBM_STATUS_SE0__PA_BUSY_MASK … #define GRBM_STATUS_SE0__PA_BUSY__SHIFT … #define GRBM_STATUS_SE0__SC_BUSY_MASK … #define GRBM_STATUS_SE0__SC_BUSY__SHIFT … #define GRBM_STATUS_SE0__SPI_BUSY_MASK … #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT … #define GRBM_STATUS_SE0__SX_BUSY_MASK … #define GRBM_STATUS_SE0__SX_BUSY__SHIFT … #define GRBM_STATUS_SE0__TA_BUSY_MASK … #define GRBM_STATUS_SE0__TA_BUSY__SHIFT … #define GRBM_STATUS_SE0__VGT_BUSY_MASK … #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT … #define GRBM_STATUS_SE1__BCI_BUSY_MASK … #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT … #define GRBM_STATUS_SE1__CB_BUSY_MASK … #define GRBM_STATUS_SE1__CB_BUSY__SHIFT … #define GRBM_STATUS_SE1__CB_CLEAN_MASK … #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT … #define GRBM_STATUS_SE1__DB_BUSY_MASK … #define GRBM_STATUS_SE1__DB_BUSY__SHIFT … #define GRBM_STATUS_SE1__DB_CLEAN_MASK … #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT … #define GRBM_STATUS_SE1__PA_BUSY_MASK … #define GRBM_STATUS_SE1__PA_BUSY__SHIFT … #define GRBM_STATUS_SE1__SC_BUSY_MASK … #define GRBM_STATUS_SE1__SC_BUSY__SHIFT … #define GRBM_STATUS_SE1__SPI_BUSY_MASK … #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT … #define GRBM_STATUS_SE1__SX_BUSY_MASK … #define GRBM_STATUS_SE1__SX_BUSY__SHIFT … #define GRBM_STATUS_SE1__TA_BUSY_MASK … #define GRBM_STATUS_SE1__TA_BUSY__SHIFT … #define GRBM_STATUS_SE1__VGT_BUSY_MASK … #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT … #define GRBM_STATUS_SE2__BCI_BUSY_MASK … #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT … #define GRBM_STATUS_SE2__CB_BUSY_MASK … #define GRBM_STATUS_SE2__CB_BUSY__SHIFT … #define GRBM_STATUS_SE2__CB_CLEAN_MASK … #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT … #define GRBM_STATUS_SE2__DB_BUSY_MASK … #define GRBM_STATUS_SE2__DB_BUSY__SHIFT … #define GRBM_STATUS_SE2__DB_CLEAN_MASK … #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT … #define GRBM_STATUS_SE2__PA_BUSY_MASK … #define GRBM_STATUS_SE2__PA_BUSY__SHIFT … #define GRBM_STATUS_SE2__SC_BUSY_MASK … #define GRBM_STATUS_SE2__SC_BUSY__SHIFT … #define GRBM_STATUS_SE2__SPI_BUSY_MASK … #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT … #define GRBM_STATUS_SE2__SX_BUSY_MASK … #define GRBM_STATUS_SE2__SX_BUSY__SHIFT … #define GRBM_STATUS_SE2__TA_BUSY_MASK … #define GRBM_STATUS_SE2__TA_BUSY__SHIFT … #define GRBM_STATUS_SE2__VGT_BUSY_MASK … #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT … #define GRBM_STATUS_SE3__BCI_BUSY_MASK … #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT … #define GRBM_STATUS_SE3__CB_BUSY_MASK … #define GRBM_STATUS_SE3__CB_BUSY__SHIFT … #define GRBM_STATUS_SE3__CB_CLEAN_MASK … #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT … #define GRBM_STATUS_SE3__DB_BUSY_MASK … #define GRBM_STATUS_SE3__DB_BUSY__SHIFT … #define GRBM_STATUS_SE3__DB_CLEAN_MASK … #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT … #define GRBM_STATUS_SE3__PA_BUSY_MASK … #define GRBM_STATUS_SE3__PA_BUSY__SHIFT … #define GRBM_STATUS_SE3__SC_BUSY_MASK … #define GRBM_STATUS_SE3__SC_BUSY__SHIFT … #define GRBM_STATUS_SE3__SPI_BUSY_MASK … #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT … #define GRBM_STATUS_SE3__SX_BUSY_MASK … #define GRBM_STATUS_SE3__SX_BUSY__SHIFT … #define GRBM_STATUS_SE3__TA_BUSY_MASK … #define GRBM_STATUS_SE3__TA_BUSY__SHIFT … #define GRBM_STATUS_SE3__VGT_BUSY_MASK … #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT … #define GRBM_STATUS__SPI_BUSY_MASK … #define GRBM_STATUS__SPI_BUSY__SHIFT … #define GRBM_STATUS__SRBM_RQ_PENDING_MASK … #define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT … #define GRBM_STATUS__SX_BUSY_MASK … #define GRBM_STATUS__SX_BUSY__SHIFT … #define GRBM_STATUS__TA_BUSY_MASK … #define GRBM_STATUS__TA_BUSY__SHIFT … #define GRBM_STATUS__VGT_BUSY_MASK … #define GRBM_STATUS__VGT_BUSY__SHIFT … #define GRBM_STATUS__WD_BUSY_MASK … #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK … #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT … #define GRBM_STATUS__WD_BUSY__SHIFT … #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK … #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT … #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK … #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT … #define IA_CNTL_STATUS__IA_BUSY_MASK … #define IA_CNTL_STATUS__IA_BUSY__SHIFT … #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK … #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT … #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK … #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT … #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK … #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT … #define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK … #define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT … #define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK … #define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT … #define IA_DEBUG_DATA__DATA_MASK … #define IA_DEBUG_DATA__DATA__SHIFT … #define IA_DEBUG_REG0__core_clk_busy_MASK … #define IA_DEBUG_REG0__core_clk_busy__SHIFT … #define IA_DEBUG_REG0__dma_busy_MASK … #define IA_DEBUG_REG0__dma_busy__SHIFT … #define IA_DEBUG_REG0__dma_grp_hp_valid_MASK … #define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT … #define IA_DEBUG_REG0__dma_grp_valid_MASK … #define IA_DEBUG_REG0__dma_grp_valid__SHIFT … #define IA_DEBUG_REG0__dma_req_busy_MASK … #define IA_DEBUG_REG0__dma_req_busy__SHIFT … #define IA_DEBUG_REG0__grp_busy_MASK … #define IA_DEBUG_REG0__grp_busy__SHIFT … #define IA_DEBUG_REG0__grp_dma_hp_read_MASK … #define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT … #define IA_DEBUG_REG0__grp_dma_read_MASK … #define IA_DEBUG_REG0__grp_dma_read__SHIFT … #define IA_DEBUG_REG0__ia_busy_extended_MASK … #define IA_DEBUG_REG0__ia_busy_extended__SHIFT … #define IA_DEBUG_REG0__ia_busy_MASK … #define IA_DEBUG_REG0__ia_busy__SHIFT … #define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK … #define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT … #define IA_DEBUG_REG0__ia_nodma_busy_MASK … #define IA_DEBUG_REG0__ia_nodma_busy__SHIFT … #define IA_DEBUG_REG0__mc_xl8r_busy_MASK … #define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT … #define IA_DEBUG_REG0__reg_clk_busy_MASK … #define IA_DEBUG_REG0__reg_clk_busy__SHIFT … #define IA_DEBUG_REG0__sclk_core_vld_MASK … #define IA_DEBUG_REG0__sclk_core_vld__SHIFT … #define IA_DEBUG_REG0__sclk_reg_vld_MASK … #define IA_DEBUG_REG0__sclk_reg_vld__SHIFT … #define IA_DEBUG_REG0__SPARE0_MASK … #define IA_DEBUG_REG0__SPARE0__SHIFT … #define IA_DEBUG_REG0__SPARE1_MASK … #define IA_DEBUG_REG0__SPARE1__SHIFT … #define IA_DEBUG_REG0__SPARE2_MASK … #define IA_DEBUG_REG0__SPARE2__SHIFT … #define IA_DEBUG_REG0__SPARE3_MASK … #define IA_DEBUG_REG0__SPARE3__SHIFT … #define IA_DEBUG_REG0__SPARE4_MASK … #define IA_DEBUG_REG0__SPARE4__SHIFT … #define IA_DEBUG_REG0__SPARE5_MASK … #define IA_DEBUG_REG0__SPARE5__SHIFT … #define IA_DEBUG_REG0__SPARE6_MASK … #define IA_DEBUG_REG0__SPARE6__SHIFT … #define IA_DEBUG_REG1__current_data_valid_MASK … #define IA_DEBUG_REG1__current_data_valid__SHIFT … #define IA_DEBUG_REG1__discard_1st_chunk_MASK … #define IA_DEBUG_REG1__discard_1st_chunk__SHIFT … #define IA_DEBUG_REG1__discard_2nd_chunk_MASK … #define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT … #define IA_DEBUG_REG1__dma_buf_type_q_MASK … #define IA_DEBUG_REG1__dma_buf_type_q__SHIFT … #define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK … #define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT … #define IA_DEBUG_REG1__dma_data_fifo_full_MASK … #define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT … #define IA_DEBUG_REG1__dma_grp_valid_MASK … #define IA_DEBUG_REG1__dma_grp_valid__SHIFT … #define IA_DEBUG_REG1__dma_input_fifo_empty_MASK … #define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT … #define IA_DEBUG_REG1__dma_input_fifo_full_MASK … #define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT … #define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK … #define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT … #define IA_DEBUG_REG1__dma_mask_fifo_we_MASK … #define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT … #define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK … #define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT … #define IA_DEBUG_REG1__dma_req_fifo_empty_MASK … #define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT … #define IA_DEBUG_REG1__dma_req_fifo_full_MASK … #define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT … #define IA_DEBUG_REG1__dma_req_path_q_MASK … #define IA_DEBUG_REG1__dma_req_path_q__SHIFT … #define IA_DEBUG_REG1__dma_ret_data_we_q_MASK … #define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT … #define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK … #define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT … #define IA_DEBUG_REG1__dma_skid_fifo_full_MASK … #define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT … #define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK … #define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT … #define IA_DEBUG_REG1__dma_zero_indices_q_MASK … #define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT … #define IA_DEBUG_REG1__grp_dma_read_MASK … #define IA_DEBUG_REG1__grp_dma_read__SHIFT … #define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK … #define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT … #define IA_DEBUG_REG1__out_of_range_r2_q_MASK … #define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT … #define IA_DEBUG_REG1__second_tc_ret_data_q_MASK … #define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT … #define IA_DEBUG_REG1__stage2_dr_MASK … #define IA_DEBUG_REG1__stage2_dr__SHIFT … #define IA_DEBUG_REG1__stage2_rtr_MASK … #define IA_DEBUG_REG1__stage2_rtr__SHIFT … #define IA_DEBUG_REG1__stage3_dr_MASK … #define IA_DEBUG_REG1__stage3_dr__SHIFT … #define IA_DEBUG_REG1__stage3_rtr_MASK … #define IA_DEBUG_REG1__stage3_rtr__SHIFT … #define IA_DEBUG_REG1__stage4_dr_MASK … #define IA_DEBUG_REG1__stage4_dr__SHIFT … #define IA_DEBUG_REG1__stage4_rtr_MASK … #define IA_DEBUG_REG1__stage4_rtr__SHIFT … #define IA_DEBUG_REG1__start_new_packet_MASK … #define IA_DEBUG_REG1__start_new_packet__SHIFT … #define IA_DEBUG_REG2__hp_current_data_valid_MASK … #define IA_DEBUG_REG2__hp_current_data_valid__SHIFT … #define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK … #define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT … #define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK … #define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT … #define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK … #define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT … #define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK … #define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT … #define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK … #define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT … #define IA_DEBUG_REG2__hp_dma_grp_valid_MASK … #define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT … #define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK … #define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT … #define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK … #define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT … #define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK … #define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT … #define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK … #define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT … #define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK … #define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT … #define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK … #define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT … #define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK … #define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT … #define IA_DEBUG_REG2__hp_dma_req_path_q_MASK … #define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT … #define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK … #define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT … #define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK … #define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT … #define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK … #define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT … #define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK … #define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT … #define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK … #define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT … #define IA_DEBUG_REG2__hp_grp_dma_read_MASK … #define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT … #define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK … #define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT … #define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK … #define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT … #define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK … #define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT … #define IA_DEBUG_REG2__hp_stage2_dr_MASK … #define IA_DEBUG_REG2__hp_stage2_dr__SHIFT … #define IA_DEBUG_REG2__hp_stage2_rtr_MASK … #define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT … #define IA_DEBUG_REG2__hp_stage3_dr_MASK … #define IA_DEBUG_REG2__hp_stage3_dr__SHIFT … #define IA_DEBUG_REG2__hp_stage3_rtr_MASK … #define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT … #define IA_DEBUG_REG2__hp_stage4_dr_MASK … #define IA_DEBUG_REG2__hp_stage4_dr__SHIFT … #define IA_DEBUG_REG2__hp_stage4_rtr_MASK … #define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT … #define IA_DEBUG_REG2__hp_start_new_packet_MASK … #define IA_DEBUG_REG2__hp_start_new_packet__SHIFT … #define IA_DEBUG_REG3__discard_1st_chunk_MASK … #define IA_DEBUG_REG3__discard_1st_chunk__SHIFT … #define IA_DEBUG_REG3__discard_2nd_chunk_MASK … #define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT … #define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK … #define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT … #define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK … #define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT … #define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK … #define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT … #define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK … #define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT … #define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK … #define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT … #define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK … #define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT … #define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK … #define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT … #define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK … #define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT … #define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK … #define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT … #define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK … #define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT … #define IA_DEBUG_REG3__dma_rdreq_send_out_MASK … #define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT … #define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK … #define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT … #define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK … #define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT … #define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK … #define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT … #define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK … #define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT … #define IA_DEBUG_REG3__last_tc_req_p1_MASK … #define IA_DEBUG_REG3__last_tc_req_p1__SHIFT … #define IA_DEBUG_REG3__mc_out_rtr_MASK … #define IA_DEBUG_REG3__mc_out_rtr__SHIFT … #define IA_DEBUG_REG3__must_service_pipe0_req_MASK … #define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT … #define IA_DEBUG_REG3__pair0_valid_p1_MASK … #define IA_DEBUG_REG3__pair0_valid_p1__SHIFT … #define IA_DEBUG_REG3__pair1_valid_p1_MASK … #define IA_DEBUG_REG3__pair1_valid_p1__SHIFT … #define IA_DEBUG_REG3__pair2_valid_p1_MASK … #define IA_DEBUG_REG3__pair2_valid_p1__SHIFT … #define IA_DEBUG_REG3__pair3_valid_p1_MASK … #define IA_DEBUG_REG3__pair3_valid_p1__SHIFT … #define IA_DEBUG_REG3__pipe0_dr_MASK … #define IA_DEBUG_REG3__pipe0_dr__SHIFT … #define IA_DEBUG_REG3__pipe0_rtr_MASK … #define IA_DEBUG_REG3__pipe0_rtr__SHIFT … #define IA_DEBUG_REG3__send_pipe1_req_MASK … #define IA_DEBUG_REG3__send_pipe1_req__SHIFT … #define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK … #define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT … #define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK … #define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT … #define IA_DEBUG_REG3__tc_out_rtr_MASK … #define IA_DEBUG_REG3__tc_out_rtr__SHIFT … #define IA_DEBUG_REG3__tc_req_count_q_MASK … #define IA_DEBUG_REG3__tc_req_count_q__SHIFT … #define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK … #define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT … #define IA_DEBUG_REG4__di_event_flag_p1_q_MASK … #define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT … #define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK … #define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT … #define IA_DEBUG_REG4__di_major_mode_p1_q_MASK … #define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT … #define IA_DEBUG_REG4__di_source_select_p1_q_MASK … #define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT … #define IA_DEBUG_REG4__di_state_sel_p1_q_MASK … #define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT … #define IA_DEBUG_REG4__draw_opaq_active_q_MASK … #define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT … #define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK … #define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT … #define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK … #define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT … #define IA_DEBUG_REG4__grp_se0_fifo_full_MASK … #define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT … #define IA_DEBUG_REG4__gs_mode_p1_q_MASK … #define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT … #define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK … #define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT … #define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK … #define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT … #define IA_DEBUG_REG4__last_shift_of_draw_MASK … #define IA_DEBUG_REG4__last_shift_of_draw__SHIFT … #define IA_DEBUG_REG4__pipe0_dr_MASK … #define IA_DEBUG_REG4__pipe0_dr__SHIFT … #define IA_DEBUG_REG4__pipe0_rtr_MASK … #define IA_DEBUG_REG4__pipe0_rtr__SHIFT … #define IA_DEBUG_REG4__pipe1_dr_MASK … #define IA_DEBUG_REG4__pipe1_dr__SHIFT … #define IA_DEBUG_REG4__pipe1_rtr_MASK … #define IA_DEBUG_REG4__pipe1_rtr__SHIFT … #define IA_DEBUG_REG4__pipe2_dr_MASK … #define IA_DEBUG_REG4__pipe2_dr__SHIFT … #define IA_DEBUG_REG4__pipe2_rtr_MASK … #define IA_DEBUG_REG4__pipe2_rtr__SHIFT … #define IA_DEBUG_REG4__pipe3_dr_MASK … #define IA_DEBUG_REG4__pipe3_dr__SHIFT … #define IA_DEBUG_REG4__pipe3_rtr_MASK … #define IA_DEBUG_REG4__pipe3_rtr__SHIFT … #define IA_DEBUG_REG4__pipe4_dr_MASK … #define IA_DEBUG_REG4__pipe4_dr__SHIFT … #define IA_DEBUG_REG4__pipe4_rtr_MASK … #define IA_DEBUG_REG4__pipe4_rtr__SHIFT … #define IA_DEBUG_REG4__pipe5_dr_MASK … #define IA_DEBUG_REG4__pipe5_dr__SHIFT … #define IA_DEBUG_REG4__pipe5_rtr_MASK … #define IA_DEBUG_REG4__pipe5_rtr__SHIFT … #define IA_DEBUG_REG4__ready_to_read_di_MASK … #define IA_DEBUG_REG4__ready_to_read_di__SHIFT … #define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK … #define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT … #define IA_DEBUG_REG5__draw_input_fifo_empty_MASK … #define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT … #define IA_DEBUG_REG5__draw_input_fifo_full_MASK … #define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT … #define IA_DEBUG_REG5__instanceid_13_0_MASK … #define IA_DEBUG_REG5__instanceid_13_0__SHIFT … #define IA_DEBUG_REG6__after_group_partial_MASK … #define IA_DEBUG_REG6__after_group_partial__SHIFT … #define IA_DEBUG_REG6__current_shift_q_MASK … #define IA_DEBUG_REG6__current_shift_q__SHIFT … #define IA_DEBUG_REG6__current_stride_pre_MASK … #define IA_DEBUG_REG6__current_stride_pre__SHIFT … #define IA_DEBUG_REG6__current_stride_q_MASK … #define IA_DEBUG_REG6__current_stride_q__SHIFT … #define IA_DEBUG_REG6__curr_prim_partial_MASK … #define IA_DEBUG_REG6__curr_prim_partial__SHIFT … #define IA_DEBUG_REG6__extract_group_MASK … #define IA_DEBUG_REG6__extract_group__SHIFT … #define IA_DEBUG_REG6__first_group_partial_MASK … #define IA_DEBUG_REG6__first_group_partial__SHIFT … #define IA_DEBUG_REG6__grp_shift_debug_data_MASK … #define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT … #define IA_DEBUG_REG6__next_group_partial_MASK … #define IA_DEBUG_REG6__next_group_partial__SHIFT … #define IA_DEBUG_REG6__next_stride_q_MASK … #define IA_DEBUG_REG6__next_stride_q__SHIFT … #define IA_DEBUG_REG6__second_group_partial_MASK … #define IA_DEBUG_REG6__second_group_partial__SHIFT … #define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK … #define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT … #define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK … #define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT … #define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK … #define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT … #define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK … #define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT … #define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK … #define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT … #define IA_DEBUG_REG7__reset_indx_state_q_MASK … #define IA_DEBUG_REG7__reset_indx_state_q__SHIFT … #define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK … #define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT … #define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK … #define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT … #define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK … #define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT … #define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK … #define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT … #define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK … #define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT … #define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK … #define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT … #define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK … #define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT … #define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK … #define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT … #define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK … #define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT … #define IA_DEBUG_REG8__di_prim_type_p1_q_MASK … #define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT … #define IA_DEBUG_REG8__grp_components_valid_MASK … #define IA_DEBUG_REG8__grp_components_valid__SHIFT … #define IA_DEBUG_REG8__grp_continued_MASK … #define IA_DEBUG_REG8__grp_continued__SHIFT … #define IA_DEBUG_REG8__grp_eopg_MASK … #define IA_DEBUG_REG8__grp_eopg__SHIFT … #define IA_DEBUG_REG8__grp_eop_MASK … #define IA_DEBUG_REG8__grp_eop__SHIFT … #define IA_DEBUG_REG8__grp_event_flag_MASK … #define IA_DEBUG_REG8__grp_event_flag__SHIFT … #define IA_DEBUG_REG8__grp_null_primitive_MASK … #define IA_DEBUG_REG8__grp_null_primitive__SHIFT … #define IA_DEBUG_REG8__grp_output_path_MASK … #define IA_DEBUG_REG8__grp_output_path__SHIFT … #define IA_DEBUG_REG8__grp_state_sel_MASK … #define IA_DEBUG_REG8__grp_state_sel__SHIFT … #define IA_DEBUG_REG8__grp_sub_prim_type_MASK … #define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT … #define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK … #define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT … #define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK … #define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT … #define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK … #define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT … #define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK … #define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT … #define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK … #define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT … #define IA_DEBUG_REG8__two_prim_input_p1_q_MASK … #define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT … #define IA_DEBUG_REG9__eopg_between_prims_p6_MASK … #define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT … #define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK … #define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT … #define IA_DEBUG_REG9__gfx_se_switch_p6_MASK … #define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT … #define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK … #define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT … #define IA_DEBUG_REG9__grp_se1_fifo_full_MASK … #define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT … #define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK … #define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT … #define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK … #define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT … #define IA_DEBUG_REG9__prim0_eoi_p6_MASK … #define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT … #define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK … #define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT … #define IA_DEBUG_REG9__prim1_eoi_p6_MASK … #define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT … #define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK … #define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT … #define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK … #define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT … #define IA_DEBUG_REG9__prim1_xfer_p6_MASK … #define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT … #define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK … #define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT … #define IA_DEBUG_REG9__prim_counter_q_MASK … #define IA_DEBUG_REG9__prim_counter_q__SHIFT … #define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK … #define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT … #define IA_DEBUG_REG9__send_to_se1_p6_MASK … #define IA_DEBUG_REG9__send_to_se1_p6__SHIFT … #define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK … #define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT … #define IA_DEBUG_REG9__SPARE0_MASK … #define IA_DEBUG_REG9__SPARE0__SHIFT … #define IA_DEBUG_REG9__SPARE1_MASK … #define IA_DEBUG_REG9__SPARE1__SHIFT … #define IA_DEBUG_REG9__two_prim_output_p5_q_MASK … #define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT … #define IA_ENHANCE__MISC_MASK … #define IA_ENHANCE__MISC__SHIFT … #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK … #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT … #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK … #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT … #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK … #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT … #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK … #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT … #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK … #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT … #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK … #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT … #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK … #define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT … #define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK … #define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT … #define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK … #define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT … #define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK … #define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT … #define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define IA_VMID_OVERRIDE__ENABLE_MASK … #define IA_VMID_OVERRIDE__ENABLE__SHIFT … #define IA_VMID_OVERRIDE__VMID_MASK … #define IA_VMID_OVERRIDE__VMID__SHIFT … #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK … #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT … #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK … #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT … #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK … #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT … #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK … #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT … #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK … #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT … #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK … #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT … #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK … #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT … #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK … #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT … #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT … #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK … #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT … #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK … #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT … #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK … #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT … #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK … #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT … #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK … #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT … #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT … #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK … #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT … #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK … #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT … #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK … #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT … #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK … #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT … #define PA_CL_CNTL_STATUS__CL_BUSY_MASK … #define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT … #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK … #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT … #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK … #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT … #define PA_CL_ENHANCE__ECO_SPARE0_MASK … #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT … #define PA_CL_ENHANCE__ECO_SPARE1_MASK … #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT … #define PA_CL_ENHANCE__ECO_SPARE2_MASK … #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT … #define PA_CL_ENHANCE__ECO_SPARE3_MASK … #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT … #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK … #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK … #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT … #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK … #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT … #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK … #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT … #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK … #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT … #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK … #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT … #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK … #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT … #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK … #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT … #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK … #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT … #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK … #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT … #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK … #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT … #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK … #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT … #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK … #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT … #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK … #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT … #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK … #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT … #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK … #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT … #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK … #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT … #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK … #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT … #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK … #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT … #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK … #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT … #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK … #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT … #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK … #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT … #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK … #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT … #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK … #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT … #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK … #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT … #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK … #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT … #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK … #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT … #define PA_CL_UCP_0_W__DATA_REGISTER_MASK … #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … #define PA_CL_UCP_0_X__DATA_REGISTER_MASK … #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT … #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK … #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT … #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK … #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT … #define PA_CL_UCP_1_W__DATA_REGISTER_MASK … #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … #define PA_CL_UCP_1_X__DATA_REGISTER_MASK … #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT … #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK … #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT … #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT … #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT … #define PA_CL_UCP_2_X__DATA_REGISTER_MASK … #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT … #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK … #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT … #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK … #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT … #define PA_CL_UCP_3_W__DATA_REGISTER_MASK … #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT … #define PA_CL_UCP_3_X__DATA_REGISTER_MASK … #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT … #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK … #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT … #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK … #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT … #define PA_CL_UCP_4_W__DATA_REGISTER_MASK … #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT … #define PA_CL_UCP_4_X__DATA_REGISTER_MASK … #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT … #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK … #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT … #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK … #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT … #define PA_CL_UCP_5_W__DATA_REGISTER_MASK … #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT … #define PA_CL_UCP_5_X__DATA_REGISTER_MASK … #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT … #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK … #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT … #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK … #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT … #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK … #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT … #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK … #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT … #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK … #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT … #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK … #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT … #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK … #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT … #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT … #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK … #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK … #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK … #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT … #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK … #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT … #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK … #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT … #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK … #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT … #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK … #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT … #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK … #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT … #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK … #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT … #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK … #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT … #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK … #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT … #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK … #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT … #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK … #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT … #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK … #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT … #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK … #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT … #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK … #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT … #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK … #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT … #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK … #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT … #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK … #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT … #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK … #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT … #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK … #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT … #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK … #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT … #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK … #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT … #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK … #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT … #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK … #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT … #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK … #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT … #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK … #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT … #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK … #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT … #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK … #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT … #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK … #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT … #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK … #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT … #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK … #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK … #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK … #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK … #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT … #define PA_SC_CLIPRECT_0_BR__BR_X_MASK … #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT … #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK … #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT … #define PA_SC_CLIPRECT_0_TL__TL_X_MASK … #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT … #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK … #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT … #define PA_SC_CLIPRECT_1_BR__BR_X_MASK … #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT … #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK … #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT … #define PA_SC_CLIPRECT_1_TL__TL_X_MASK … #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT … #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK … #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT … #define PA_SC_CLIPRECT_2_BR__BR_X_MASK … #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT … #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK … #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT … #define PA_SC_CLIPRECT_2_TL__TL_X_MASK … #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT … #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK … #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT … #define PA_SC_CLIPRECT_3_BR__BR_X_MASK … #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT … #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK … #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT … #define PA_SC_CLIPRECT_3_TL__TL_X_MASK … #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT … #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK … #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT … #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK … #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT … #define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK … #define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT … #define PA_SC_DEBUG_DATA__DATA_MASK … #define PA_SC_DEBUG_DATA__DATA__SHIFT … #define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK … #define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT … #define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK … #define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT … #define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK … #define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT … #define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK … #define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT … #define PA_SC_EDGERULE__ER_LINE_BT_MASK … #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT … #define PA_SC_EDGERULE__ER_LINE_LR_MASK … #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT … #define PA_SC_EDGERULE__ER_LINE_RL_MASK … #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT … #define PA_SC_EDGERULE__ER_LINE_TB_MASK … #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT … #define PA_SC_EDGERULE__ER_POINT_MASK … #define PA_SC_EDGERULE__ER_POINT__SHIFT … #define PA_SC_EDGERULE__ER_RECT_MASK … #define PA_SC_EDGERULE__ER_RECT__SHIFT … #define PA_SC_EDGERULE__ER_TRI_MASK … #define PA_SC_EDGERULE__ER_TRI__SHIFT … #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK … #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT … #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK … #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT … #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK … #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK … #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT … #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK … #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT … #define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK … #define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT … #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK … #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT … #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK … #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT … #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK … #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT … #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK … #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT … #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT … #define PA_SC_ENHANCE__ECO_SPARE0_MASK … #define PA_SC_ENHANCE__ECO_SPARE0__SHIFT … #define PA_SC_ENHANCE__ECO_SPARE1_MASK … #define PA_SC_ENHANCE__ECO_SPARE1__SHIFT … #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK … #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT … #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK … #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT … #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK … #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT … #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK … #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT … #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK … #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT … #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK … #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT … #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT … #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK … #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT … #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK … #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT … #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK … #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT … #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK … #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT … #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK … #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT … #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK … #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT … #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK … #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT … #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK … #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT … #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK … #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT … #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK … #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT … #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK … #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT … #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK … #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT … #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK … #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT … #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK … #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT … #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK … #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT … #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK … #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT … #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK … #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT … #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK … #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT … #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK … #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT … #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK … #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT … #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK … #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT … #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK … #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT … #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK … #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT … #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK … #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT … #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK … #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT … #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK … #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT … #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK … #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK … #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK … #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT … #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK … #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK … #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT … #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK … #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT … #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK … #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT … #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK … #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT … #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK … #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT … #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK … #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT … #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK … #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT … #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK … #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT … #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK … #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT … #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK … #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT … #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK … #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT … #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK … #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT … #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK … #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT … #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK … #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT … #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK … #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT … #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK … #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT … #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK … #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT … #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK … #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT … #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK … #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT … #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK … #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT … #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK … #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT … #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK … #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT … #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK … #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT … #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK … #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT … #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK … #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT … #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK … #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT … #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK … #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT … #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK … #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT … #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK … #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT … #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK … #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT … #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK … #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT … #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK … #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT … #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK … #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT … #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK … #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT … #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK … #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT … #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK … #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT … #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK … #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT … #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK … #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT … #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK … #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT … #define PA_SC_RASTER_CONFIG__SC_MAP_MASK … #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT … #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK … #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT … #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK … #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT … #define PA_SC_RASTER_CONFIG__SE_MAP_MASK … #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT … #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK … #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT … #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK … #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT … #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK … #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT … #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK … #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT … #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK … #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT … #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK … #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK … #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT … #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK … #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK … #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT … #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK … #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT … #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK … #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT … #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT … #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK … #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT … #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK … #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT … #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK … #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT … #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK … #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT … #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK … #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT … #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK … #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT … #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK … #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT … #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK … #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT … #define PA_SU_CNTL_STATUS__SU_BUSY_MASK … #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT … #define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK … #define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT … #define PA_SU_DEBUG_DATA__DATA_MASK … #define PA_SU_DEBUG_DATA__DATA__SHIFT … #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK … #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT … #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK … #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT … #define PA_SU_LINE_CNTL__WIDTH_MASK … #define PA_SU_LINE_CNTL__WIDTH__SHIFT … #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK … #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT … #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK … #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT … #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK … #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT … #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK … #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT … #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK … #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT … #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK … #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT … #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK … #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT … #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK … #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK … #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT … #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK … #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT … #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK … #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT … #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK … #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT … #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK … #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT … #define PA_SU_POINT_SIZE__HEIGHT_MASK … #define PA_SU_POINT_SIZE__HEIGHT__SHIFT … #define PA_SU_POINT_SIZE__WIDTH_MASK … #define PA_SU_POINT_SIZE__WIDTH__SHIFT … #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK … #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT … #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK … #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT … #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK … #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT … #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK … #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT … #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK … #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT … #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK … #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT … #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK … #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK … #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK … #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK … #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK … #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK … #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK … #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK … #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK … #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK … #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK … #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT … #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK … #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT … #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK … #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT … #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK … #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT … #define PA_SU_SC_MODE_CNTL__FACE_MASK … #define PA_SU_SC_MODE_CNTL__FACE__SHIFT … #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK … #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT … #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK … #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT … #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK … #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT … #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK … #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT … #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK … #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT … #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK … #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT … #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK … #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT … #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK … #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT … #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK … #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT … #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK … #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT … #define PA_SU_VTX_CNTL__PIX_CENTER_MASK … #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT … #define PA_SU_VTX_CNTL__QUANT_MODE_MASK … #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT … #define PA_SU_VTX_CNTL__ROUND_MODE_MASK … #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT … #define RAS_BCI_SIGNATURE0__SIGNATURE_MASK … #define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_BCI_SIGNATURE1__SIGNATURE_MASK … #define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT … #define RAS_CB_SIGNATURE0__SIGNATURE_MASK … #define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_DB_SIGNATURE0__SIGNATURE_MASK … #define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_IA_SIGNATURE0__SIGNATURE_MASK … #define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_IA_SIGNATURE1__SIGNATURE_MASK … #define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT … #define RAS_PA_SIGNATURE0__SIGNATURE_MASK … #define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_SC_SIGNATURE0__SIGNATURE_MASK … #define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_SC_SIGNATURE1__SIGNATURE_MASK … #define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT … #define RAS_SC_SIGNATURE2__SIGNATURE_MASK … #define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT … #define RAS_SC_SIGNATURE3__SIGNATURE_MASK … #define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT … #define RAS_SC_SIGNATURE4__SIGNATURE_MASK … #define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT … #define RAS_SC_SIGNATURE5__SIGNATURE_MASK … #define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT … #define RAS_SC_SIGNATURE6__SIGNATURE_MASK … #define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT … #define RAS_SC_SIGNATURE7__SIGNATURE_MASK … #define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT … #define RAS_SIGNATURE_CONTROL__ENABLE_MASK … #define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT … #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK … #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT … #define RAS_SPI_SIGNATURE0__SIGNATURE_MASK … #define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_SPI_SIGNATURE1__SIGNATURE_MASK … #define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT … #define RAS_SQ_SIGNATURE0__SIGNATURE_MASK … #define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_SX_SIGNATURE0__SIGNATURE_MASK … #define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_SX_SIGNATURE1__SIGNATURE_MASK … #define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT … #define RAS_SX_SIGNATURE2__SIGNATURE_MASK … #define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT … #define RAS_SX_SIGNATURE3__SIGNATURE_MASK … #define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT … #define RAS_TA_SIGNATURE0__SIGNATURE_MASK … #define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_TD_SIGNATURE0__SIGNATURE_MASK … #define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT … #define RAS_VGT_SIGNATURE0__SIGNATURE_MASK … #define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT … #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK … #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT … #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK … #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT … #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK … #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT … #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK … #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT … #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK … #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT … #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK … #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT … #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK … #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT … #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK … #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT … #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK … #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT … #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT … #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK … #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT … #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT … #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK … #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT … #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK … #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT … #define RLC_CGCG_CGLS_CTRL__SPARE_MASK … #define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT … #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK … #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT … #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK … #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT … #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK … #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT … #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK … #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT … #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK … #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT … #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK … #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT … #define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK … #define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT … #define RLC_CNTL__FORCE_RETRY_MASK … #define RLC_CNTL__FORCE_RETRY__SHIFT … #define RLC_CNTL__READ_CACHE_DISABLE_MASK … #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT … #define RLC_CNTL__RESERVED_MASK … #define RLC_CNTL__RESERVED__SHIFT … #define RLC_CNTL__RLC_ENABLE_F32_MASK … #define RLC_CNTL__RLC_ENABLE_F32__SHIFT … #define RLC_CNTL__RLC_STEP_F32_MASK … #define RLC_CNTL__RLC_STEP_F32__SHIFT … #define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK … #define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT … #define RLC_CU_STATUS__WORK_PENDING_MASK … #define RLC_CU_STATUS__WORK_PENDING__SHIFT … #define RLC_DEBUG__DATA_MASK … #define RLC_DEBUG__DATA__SHIFT … #define RLC_DEBUG_SELECT__RESERVED_MASK … #define RLC_DEBUG_SELECT__RESERVED__SHIFT … #define RLC_DEBUG_SELECT__SELECT_MASK … #define RLC_DEBUG_SELECT__SELECT__SHIFT … #define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK … #define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT … #define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK … #define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT … #define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK … #define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT … #define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK … #define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT … #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK … #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT … #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK … #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT … #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK … #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT … #define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK … #define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT … #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK … #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT … #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK … #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT … #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK … #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT … #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK … #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT … #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK … #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT … #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK … #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT … #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK … #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT … #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK … #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT … #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK … #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT … #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK … #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT … #define RLC_LB_CNTL__RESERVED_MASK … #define RLC_LB_CNTL__RESERVED__SHIFT … #define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK … #define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT … #define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK … #define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT … #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK … #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT … #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK … #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT … #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK … #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT … #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK … #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT … #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK … #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT … #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK … #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT … #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK … #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT … #define RLC_MAX_PG_CU__SPARE_MASK … #define RLC_MAX_PG_CU__SPARE__SHIFT … #define RLC_MC_CNTL__RDNFO_STALL_MASK … #define RLC_MC_CNTL__RDNFO_STALL__SHIFT … #define RLC_MC_CNTL__RDNFO_URG_MASK … #define RLC_MC_CNTL__RDNFO_URG__SHIFT … #define RLC_MC_CNTL__RDREQ_PRIV_MASK … #define RLC_MC_CNTL__RDREQ_PRIV__SHIFT … #define RLC_MC_CNTL__RDREQ_SWAP_MASK … #define RLC_MC_CNTL__RDREQ_SWAP__SHIFT … #define RLC_MC_CNTL__RDREQ_TRAN_MASK … #define RLC_MC_CNTL__RDREQ_TRAN__SHIFT … #define RLC_MC_CNTL__RESERVED_B_MASK … #define RLC_MC_CNTL__RESERVED_B__SHIFT … #define RLC_MC_CNTL__RESERVED_MASK … #define RLC_MC_CNTL__RESERVED__SHIFT … #define RLC_MC_CNTL__WRNFO_STALL_MASK … #define RLC_MC_CNTL__WRNFO_STALL__SHIFT … #define RLC_MC_CNTL__WRNFO_URG_MASK … #define RLC_MC_CNTL__WRNFO_URG__SHIFT … #define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK … #define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT … #define RLC_MC_CNTL__WRREQ_PRIV_MASK … #define RLC_MC_CNTL__WRREQ_PRIV__SHIFT … #define RLC_MC_CNTL__WRREQ_SWAP_MASK … #define RLC_MC_CNTL__WRREQ_SWAP__SHIFT … #define RLC_MC_CNTL__WRREQ_TRAN_MASK … #define RLC_MC_CNTL__WRREQ_TRAN__SHIFT … #define RLC_MEM_SLP_CNTL__RESERVED1_MASK … #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … #define RLC_MEM_SLP_CNTL__RESERVED_MASK … #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT … #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK … #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT … #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT … #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK … #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT … #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK … #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT … #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK … #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT … #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK … #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT … #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK … #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK … #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT … #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK … #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT … #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK … #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT … #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK … #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT … #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK … #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT … #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK … #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT … #define RLC_PG_CNTL__PG_ERROR_STATUS_MASK … #define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT … #define RLC_PG_CNTL__RESERVED1_MASK … #define RLC_PG_CNTL__RESERVED1__SHIFT … #define RLC_PG_CNTL__RESERVED_MASK … #define RLC_PG_CNTL__RESERVED__SHIFT … #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK … #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT … #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK … #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT … #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK … #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT … #define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK … #define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT … #define RLC_SERDES_RD_DATA_0__DATA_MASK … #define RLC_SERDES_RD_DATA_0__DATA__SHIFT … #define RLC_SERDES_RD_DATA_1__DATA_MASK … #define RLC_SERDES_RD_DATA_1__DATA__SHIFT … #define RLC_SERDES_RD_DATA_2__DATA_MASK … #define RLC_SERDES_RD_DATA_2__DATA__SHIFT … #define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK … #define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT … #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK … #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT … #define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK … #define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT … #define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK … #define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT … #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK … #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT … #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK … #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT … #define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK … #define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT … #define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK … #define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT … #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK … #define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT … #define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK … #define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT … #define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK … #define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT … #define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK … #define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT … #define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK … #define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT … #define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK … #define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT … #define RLC_SERDES_WR_CTRL__CGLS_ON_MASK … #define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT … #define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK … #define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT … #define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK … #define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT … #define RLC_SERDES_WR_CTRL__P1_SELECT_MASK … #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT … #define RLC_SERDES_WR_CTRL__P2_SELECT_MASK … #define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT … #define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK … #define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT … #define RLC_SERDES_WR_CTRL__POWER_UP_MASK … #define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT … #define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK … #define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT … #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK … #define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT … #define RLC_SERDES_WR_CTRL__RESERVED_1_MASK … #define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT … #define RLC_SERDES_WR_CTRL__RESERVED_2_MASK … #define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT … #define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK … #define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT … #define RLC_SERDES_WR_DATA__DATA_MASK … #define RLC_SERDES_WR_DATA__DATA__SHIFT … #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK … #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT … #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK … #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT … #define RLC_SMU_PG_CTRL__SPARE_MASK … #define RLC_SMU_PG_CTRL__SPARE__SHIFT … #define RLC_SMU_PG_CTRL__START_PG_MASK … #define RLC_SMU_PG_CTRL__START_PG__SHIFT … #define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK … #define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT … #define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK … #define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT … #define RLC_SOFT_RESET_GPU__RESERVED_MASK … #define RLC_SOFT_RESET_GPU__RESERVED__SHIFT … #define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK … #define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT … #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK … #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT … #define RLC_STAT__RESERVED_MASK … #define RLC_STAT__RESERVED__SHIFT … #define RLC_STAT__RLC_BUSY_MASK … #define RLC_STAT__RLC_BUSY__SHIFT … #define RLC_STAT__RLC_GPM_BUSY_MASK … #define RLC_STAT__RLC_GPM_BUSY__SHIFT … #define RLC_STAT__RLC_SPM_BUSY_MASK … #define RLC_STAT__RLC_SPM_BUSY__SHIFT … #define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK … #define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT … #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK … #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT … #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK … #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT … #define RLC_THREAD1_DELAY__SPARE_MASK … #define RLC_THREAD1_DELAY__SPARE__SHIFT … #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK … #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT … #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK … #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT … #define SCRATCH_REG0__SCRATCH_REG0_MASK … #define SCRATCH_REG0__SCRATCH_REG0__SHIFT … #define SCRATCH_REG1__SCRATCH_REG1_MASK … #define SCRATCH_REG1__SCRATCH_REG1__SHIFT … #define SCRATCH_REG2__SCRATCH_REG2_MASK … #define SCRATCH_REG2__SCRATCH_REG2__SHIFT … #define SCRATCH_REG3__SCRATCH_REG3_MASK … #define SCRATCH_REG3__SCRATCH_REG3__SHIFT … #define SCRATCH_REG4__SCRATCH_REG4_MASK … #define SCRATCH_REG4__SCRATCH_REG4__SHIFT … #define SCRATCH_REG5__SCRATCH_REG5_MASK … #define SCRATCH_REG5__SCRATCH_REG5__SHIFT … #define SCRATCH_REG6__SCRATCH_REG6_MASK … #define SCRATCH_REG6__SCRATCH_REG6__SHIFT … #define SCRATCH_REG7__SCRATCH_REG7_MASK … #define SCRATCH_REG7__SCRATCH_REG7__SHIFT … #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK … #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT … #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK … #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT … #define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK … #define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT … #define SETUP_DEBUG_REG0__event_gated_MASK … #define SETUP_DEBUG_REG0__event_gated__SHIFT … #define SETUP_DEBUG_REG0__event_id_gated_MASK … #define SETUP_DEBUG_REG0__event_id_gated__SHIFT … #define SETUP_DEBUG_REG0__geom_busy_MASK … #define SETUP_DEBUG_REG0__geom_busy__SHIFT … #define SETUP_DEBUG_REG0__geom_enable_MASK … #define SETUP_DEBUG_REG0__geom_enable__SHIFT … #define SETUP_DEBUG_REG0__ge_stallb_MASK … #define SETUP_DEBUG_REG0__ge_stallb__SHIFT … #define SETUP_DEBUG_REG0__pfifo_busy_MASK … #define SETUP_DEBUG_REG0__pfifo_busy__SHIFT … #define SETUP_DEBUG_REG0__pmode_prim_gated_MASK … #define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT … #define SETUP_DEBUG_REG0__pmode_state_MASK … #define SETUP_DEBUG_REG0__pmode_state__SHIFT … #define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK … #define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT … #define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK … #define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT … #define SETUP_DEBUG_REG0__su_clip_rtr_MASK … #define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT … #define SETUP_DEBUG_REG0__su_cntl_busy_MASK … #define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT … #define SETUP_DEBUG_REG0__su_cntl_state_MASK … #define SETUP_DEBUG_REG0__su_cntl_state__SHIFT … #define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK … #define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT … #define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK … #define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT … #define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK … #define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT … #define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK … #define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT … #define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK … #define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT … #define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK … #define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT … #define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK … #define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT … #define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK … #define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT … #define SETUP_DEBUG_REG4__backfacing_gated_MASK … #define SETUP_DEBUG_REG4__backfacing_gated__SHIFT … #define SETUP_DEBUG_REG4__clipped_gated_MASK … #define SETUP_DEBUG_REG4__clipped_gated__SHIFT … #define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK … #define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT … #define SETUP_DEBUG_REG4__diamond_rule_gated_MASK … #define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT … #define SETUP_DEBUG_REG4__eop_gated_MASK … #define SETUP_DEBUG_REG4__eop_gated__SHIFT … #define SETUP_DEBUG_REG4__fpov_gated_MASK … #define SETUP_DEBUG_REG4__fpov_gated__SHIFT … #define SETUP_DEBUG_REG4__null_prim_gated_MASK … #define SETUP_DEBUG_REG4__null_prim_gated__SHIFT … #define SETUP_DEBUG_REG4__st_indx_gated_MASK … #define SETUP_DEBUG_REG4__st_indx_gated__SHIFT … #define SETUP_DEBUG_REG4__type_gated_MASK … #define SETUP_DEBUG_REG4__type_gated__SHIFT … #define SETUP_DEBUG_REG4__xmajor_gated_MASK … #define SETUP_DEBUG_REG4__xmajor_gated__SHIFT … #define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK … #define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT … #define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK … #define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT … #define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK … #define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT … #define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK … #define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT … #define SETUP_DEBUG_REG5__valid_prim_gated_MASK … #define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT … #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK … #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT … #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK … #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT … #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK … #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT … #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK … #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT … #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK … #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT … #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK … #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT … #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK … #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT … #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK … #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT … #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK … #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT … #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK … #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT … #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK … #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT … #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK … #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT … #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK … #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT … #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK … #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT … #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK … #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT … #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK … #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT … #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK … #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT … #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK … #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT … #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK … #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT … #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK … #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT … #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK … #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT … #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK … #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT … #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK … #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT … #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT … #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK … #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT … #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK … #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT … #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK … #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT … #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK … #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT … #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK … #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT … #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK … #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT … #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK … #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT … #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK … #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT … #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK … #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT … #define SPI_DEBUG_BUSY__CS0_BUSY_MASK … #define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT … #define SPI_DEBUG_BUSY__CS1_BUSY_MASK … #define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT … #define SPI_DEBUG_BUSY__CS2_BUSY_MASK … #define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT … #define SPI_DEBUG_BUSY__CS3_BUSY_MASK … #define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT … #define SPI_DEBUG_BUSY__CS4_BUSY_MASK … #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT … #define SPI_DEBUG_BUSY__CS5_BUSY_MASK … #define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT … #define SPI_DEBUG_BUSY__CS6_BUSY_MASK … #define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT … #define SPI_DEBUG_BUSY__CS7_BUSY_MASK … #define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT … #define SPI_DEBUG_BUSY__CSG_BUSY_MASK … #define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT … #define SPI_DEBUG_BUSY__ES_BUSY_MASK … #define SPI_DEBUG_BUSY__ES_BUSY__SHIFT … #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK … #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT … #define SPI_DEBUG_BUSY__GRBM_BUSY_MASK … #define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT … #define SPI_DEBUG_BUSY__GS_BUSY_MASK … #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT … #define SPI_DEBUG_BUSY__HS_BUSY_MASK … #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT … #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK … #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT … #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK … #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT … #define SPI_DEBUG_BUSY__LS_BUSY_MASK … #define SPI_DEBUG_BUSY__LS_BUSY__SHIFT … #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK … #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT … #define SPI_DEBUG_BUSY__PS0_BUSY_MASK … #define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT … #define SPI_DEBUG_BUSY__PS1_BUSY_MASK … #define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT … #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK … #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT … #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK … #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT … #define SPI_DEBUG_BUSY__SPIS_BUSY_MASK … #define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT … #define SPI_DEBUG_BUSY__VS_BUSY_MASK … #define SPI_DEBUG_BUSY__VS_BUSY__SHIFT … #define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK … #define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT … #define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK … #define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT … #define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK … #define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT … #define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK … #define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT … #define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK … #define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT … #define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK … #define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT … #define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK … #define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK … #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT … #define SPI_DEBUG_READ__DATA_MASK … #define SPI_DEBUG_READ__DATA__SHIFT … #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK … #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT … #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK … #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT … #define SPI_GDS_CREDITS__UNUSED_MASK … #define SPI_GDS_CREDITS__UNUSED__SHIFT … #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK … #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK … #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT … #define SPI_LB_CTR_CTRL__LOAD_MASK … #define SPI_LB_CTR_CTRL__LOAD__SHIFT … #define SPI_LB_CU_MASK__CU_MASK_MASK … #define SPI_LB_CU_MASK__CU_MASK__SHIFT … #define SPI_LB_DATA_REG__CNT_DATA_MASK … #define SPI_LB_DATA_REG__CNT_DATA__SHIFT … #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK … #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT … #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK … #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK … #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT … #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK … #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT … #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK … #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT … #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK … #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT … #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK … #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT … #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK … #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT … #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK … #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT … #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK … #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT … #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK … #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT … #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK … #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT … #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK … #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT … #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT … #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK … #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT … #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK … #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT … #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK … #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT … #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK … #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT … #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK … #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT … #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK … #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT … #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK … #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT … #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK … #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT … #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK … #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK … #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK … #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK … #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK … #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK … #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK … #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK … #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK … #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK … #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK … #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK … #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK … #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK … #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK … #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT … #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK … #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT … #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_0__DUP_MASK … #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_10__DUP_MASK … #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_11__DUP_MASK … #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_12__DUP_MASK … #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_13__DUP_MASK … #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_14__DUP_MASK … #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_15__DUP_MASK … #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_16__DUP_MASK … #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_17__DUP_MASK … #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_18__DUP_MASK … #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_19__DUP_MASK … #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_1__DUP_MASK … #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_20__DUP_MASK … #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_21__DUP_MASK … #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_22__DUP_MASK … #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_23__DUP_MASK … #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_24__DUP_MASK … #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_25__DUP_MASK … #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_26__DUP_MASK … #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_27__DUP_MASK … #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_28__DUP_MASK … #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_29__DUP_MASK … #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_2__DUP_MASK … #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_30__DUP_MASK … #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_31__DUP_MASK … #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_3__DUP_MASK … #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_4__DUP_MASK … #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_5__DUP_MASK … #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_6__DUP_MASK … #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_7__DUP_MASK … #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_8__DUP_MASK … #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK … #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT … #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK … #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT … #define SPI_PS_INPUT_CNTL_9__DUP_MASK … #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT … #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK … #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT … #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK … #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT … #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK … #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT … #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK … #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT … #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK … #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT … #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK … #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT … #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK … #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT … #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK … #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT … #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK … #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT … #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK … #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT … #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK … #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT … #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK … #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT … #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK … #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT … #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK … #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT … #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK … #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT … #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK … #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT … #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK … #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT … #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK … #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT … #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK … #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT … #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK … #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT … #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK … #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK … #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK … #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK … #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK … #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK … #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK … #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK … #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK … #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK … #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK … #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK … #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK … #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK … #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK … #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK … #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK … #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK … #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK … #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK … #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK … #define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK … #define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK … #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK … #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK … #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK … #define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK … #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT … #define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK … #define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK … #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK … #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK … #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK … #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK … #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK … #define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK … #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK … #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK … #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK … #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK … #define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK … #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK … #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK … #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK … #define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK … #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT … #define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK … #define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK … #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK … #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK … #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK … #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK … #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK … #define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK … #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK … #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK … #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK … #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK … #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK … #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK … #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT … #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK … #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK … #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK … #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK … #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK … #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK … #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK … #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK … #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK … #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK … #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK … #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT … #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT … #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK … #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK … #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK … #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK … #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK … #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK … #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK … #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK … #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK … #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK … #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT … #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK … #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT … #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK … #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK … #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK … #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK … #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT … #define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK … #define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK … #define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK … #define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK … #define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK … #define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK … #define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK … #define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK … #define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK … #define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK … #define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK … #define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT … #define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK … #define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK … #define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK … #define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK … #define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK … #define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK … #define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK … #define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK … #define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK … #define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK … #define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK … #define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK … #define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT … #define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK … #define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT … #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT … #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK … #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_0__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_10__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_11__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_12__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_13__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_14__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_15__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_1__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_2__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_3__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_4__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_5__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_6__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_7__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_8__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT … #define SPI_SHADER_USER_DATA_GS_9__DATA_MASK … #define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_0__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_10__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_11__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_12__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_13__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_14__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_15__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_1__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_2__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_3__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_4__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_5__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_6__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_7__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_8__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT … #define SPI_SHADER_USER_DATA_HS_9__DATA_MASK … #define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT … #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK … #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT … #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK … #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT … #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK … #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT … #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK … #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT … #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK … #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT … #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK … #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT … #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK … #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT … #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK … #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT … #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK … #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT … #define SPI_TMPRING_SIZE__WAVESIZE_MASK … #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT … #define SPI_TMPRING_SIZE__WAVES_MASK … #define SPI_TMPRING_SIZE__WAVES__SHIFT … #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK … #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT … #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK … #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT … #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK … #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT … #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK … #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT … #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK … #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT … #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK … #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT … #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK … #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT … #define SQ_BUF_RSRC_WORD1__STRIDE_MASK … #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT … #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK … #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT … #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK … #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT … #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK … #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT … #define SQ_BUF_RSRC_WORD3__ATC_MASK … #define SQ_BUF_RSRC_WORD3__ATC__SHIFT … #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK … #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT … #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK … #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT … #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK … #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT … #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK … #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT … #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK … #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT … #define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK … #define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT … #define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK … #define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT … #define SQ_BUF_RSRC_WORD3__HEAP_MASK … #define SQ_BUF_RSRC_WORD3__HEAP__SHIFT … #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK … #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT … #define SQ_BUF_RSRC_WORD3__MTYPE_MASK … #define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT … #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK … #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT … #define SQ_BUF_RSRC_WORD3__TYPE_MASK … #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT … #define SQC_CACHES__DATA_INVALIDATE_MASK … #define SQC_CACHES__DATA_INVALIDATE__SHIFT … #define SQC_CACHES__INST_INVALIDATE_MASK … #define SQC_CACHES__INST_INVALIDATE__SHIFT … #define SQC_CACHES__INVALIDATE_VOLATILE_MASK … #define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT … #define SQC_CONFIG__DATA_CACHE_SIZE_MASK … #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT … #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK … #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT … #define SQC_CONFIG__FORCE_IN_ORDER_MASK … #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT … #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK … #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT … #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK … #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT … #define SQC_CONFIG__IDENTITY_HASH_SET_MASK … #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT … #define SQC_CONFIG__INST_CACHE_SIZE_MASK … #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT … #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK … #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT … #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK … #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT … #define SQ_CONFIG__DEBUG_EN_MASK … #define SQ_CONFIG__DEBUG_EN__SHIFT … #define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK … #define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT … #define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK … #define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT … #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK … #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT … #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK … #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT … #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK … #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT … #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK … #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT … #define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK … #define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT … #define SQ_CONFIG__UNUSED_MASK … #define SQ_CONFIG__UNUSED__SHIFT … #define SQC_SECDED_CNT__DATA_DED_MASK … #define SQC_SECDED_CNT__DATA_DED__SHIFT … #define SQC_SECDED_CNT__DATA_SEC_MASK … #define SQC_SECDED_CNT__DATA_SEC__SHIFT … #define SQC_SECDED_CNT__INST_DED_MASK … #define SQC_SECDED_CNT__INST_DED__SHIFT … #define SQC_SECDED_CNT__INST_SEC_MASK … #define SQC_SECDED_CNT__INST_SEC__SHIFT … #define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK … #define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT … #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK … #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT … #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK … #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT … #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK … #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT … #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK … #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT … #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK … #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT … #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK … #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT … #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK … #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT … #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK … #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT … #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK … #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT … #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK … #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT … #define SQ_DEBUG_STS_LOCAL__BUSY_MASK … #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT … #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK … #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT … #define SQ_DED_CNT__LDS_DED_MASK … #define SQ_DED_CNT__LDS_DED__SHIFT … #define SQ_DED_CNT__SGPR_DED_MASK … #define SQ_DED_CNT__SGPR_DED__SHIFT … #define SQ_DED_CNT__VGPR_DED_MASK … #define SQ_DED_CNT__VGPR_DED__SHIFT … #define SQ_DED_INFO__SIMD_ID_MASK … #define SQ_DED_INFO__SIMD_ID__SHIFT … #define SQ_DED_INFO__SOURCE_MASK … #define SQ_DED_INFO__SOURCE__SHIFT … #define SQ_DED_INFO__VM_ID_MASK … #define SQ_DED_INFO__VM_ID__SHIFT … #define SQ_DED_INFO__WAVE_ID_MASK … #define SQ_DED_INFO__WAVE_ID__SHIFT … #define SQ_DS_0__ENCODING_MASK … #define SQ_DS_0__ENCODING__SHIFT … #define SQ_DS_0__GDS_MASK … #define SQ_DS_0__GDS__SHIFT … #define SQ_DS_0__OFFSET0_MASK … #define SQ_DS_0__OFFSET0__SHIFT … #define SQ_DS_0__OFFSET1_MASK … #define SQ_DS_0__OFFSET1__SHIFT … #define SQ_DS_0__OP_MASK … #define SQ_DS_0__OP__SHIFT … #define SQ_DS_1__ADDR_MASK … #define SQ_DS_1__ADDR__SHIFT … #define SQ_DS_1__DATA0_MASK … #define SQ_DS_1__DATA0__SHIFT … #define SQ_DS_1__DATA1_MASK … #define SQ_DS_1__DATA1__SHIFT … #define SQ_DS_1__VDST_MASK … #define SQ_DS_1__VDST__SHIFT … #define SQ_EXP_0__COMPR_MASK … #define SQ_EXP_0__COMPR__SHIFT … #define SQ_EXP_0__DONE_MASK … #define SQ_EXP_0__DONE__SHIFT … #define SQ_EXP_0__ENCODING_MASK … #define SQ_EXP_0__ENCODING__SHIFT … #define SQ_EXP_0__EN_MASK … #define SQ_EXP_0__EN__SHIFT … #define SQ_EXP_0__TGT_MASK … #define SQ_EXP_0__TGT__SHIFT … #define SQ_EXP_0__VM_MASK … #define SQ_EXP_0__VM__SHIFT … #define SQ_EXP_1__VSRC0_MASK … #define SQ_EXP_1__VSRC0__SHIFT … #define SQ_EXP_1__VSRC1_MASK … #define SQ_EXP_1__VSRC1__SHIFT … #define SQ_EXP_1__VSRC2_MASK … #define SQ_EXP_1__VSRC2__SHIFT … #define SQ_EXP_1__VSRC3_MASK … #define SQ_EXP_1__VSRC3__SHIFT … #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK … #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT … #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK … #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT … #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK … #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT … #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK … #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT … #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK … #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT … #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK … #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT … #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK … #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT … #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK … #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT … #define SQ_IMG_RSRC_WORD1__MTYPE_MASK … #define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT … #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK … #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT … #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK … #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT … #define SQ_IMG_RSRC_WORD2__INTERLACED_MASK … #define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT … #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK … #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT … #define SQ_IMG_RSRC_WORD2__WIDTH_MASK … #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT … #define SQ_IMG_RSRC_WORD3__ATC_MASK … #define SQ_IMG_RSRC_WORD3__ATC__SHIFT … #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK … #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT … #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK … #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT … #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK … #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT … #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK … #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT … #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK … #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT … #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK … #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT … #define SQ_IMG_RSRC_WORD3__MTYPE_MASK … #define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT … #define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK … #define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT … #define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK … #define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT … #define SQ_IMG_RSRC_WORD3__TYPE_MASK … #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT … #define SQ_IMG_RSRC_WORD4__DEPTH_MASK … #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT … #define SQ_IMG_RSRC_WORD4__PITCH_MASK … #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT … #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK … #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT … #define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK … #define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT … #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK … #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT … #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK … #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT … #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK … #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT … #define SQ_IMG_RSRC_WORD6__UNUNSED_MASK … #define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT … #define SQ_IMG_RSRC_WORD7__UNUNSED_MASK … #define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT … #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK … #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT … #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK … #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT … #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK … #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT … #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK … #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT … #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK … #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT … #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK … #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT … #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK … #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT … #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK … #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT … #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK … #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT … #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK … #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT … #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK … #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT … #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK … #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT … #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK … #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT … #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK … #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT … #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK … #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT … #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK … #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT … #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK … #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT … #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK … #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT … #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK … #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT … #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK … #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK … #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT … #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT … #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK … #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT … #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK … #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT … #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK … #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT … #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK … #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT … #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK … #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT … #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK … #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT … #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK … #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT … #define SQ_IND_DATA__DATA_MASK … #define SQ_IND_DATA__DATA__SHIFT … #define SQ_IND_INDEX__AUTO_INCR_MASK … #define SQ_IND_INDEX__AUTO_INCR__SHIFT … #define SQ_IND_INDEX__FORCE_READ_MASK … #define SQ_IND_INDEX__FORCE_READ__SHIFT … #define SQ_IND_INDEX__INDEX_MASK … #define SQ_IND_INDEX__INDEX__SHIFT … #define SQ_IND_INDEX__READ_TIMEOUT_MASK … #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT … #define SQ_IND_INDEX__SIMD_ID_MASK … #define SQ_IND_INDEX__SIMD_ID__SHIFT … #define SQ_IND_INDEX__THREAD_ID_MASK … #define SQ_IND_INDEX__THREAD_ID__SHIFT … #define SQ_IND_INDEX__UNINDEXED_MASK … #define SQ_IND_INDEX__UNINDEXED__SHIFT … #define SQ_IND_INDEX__WAVE_ID_MASK … #define SQ_IND_INDEX__WAVE_ID__SHIFT … #define SQ_INST__ENCODING_MASK … #define SQ_INST__ENCODING__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK … #define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK … #define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK … #define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK … #define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK … #define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK … #define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK … #define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK … #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK … #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT … #define SQ_INTERRUPT_WORD_AUTO__WLT_MASK … #define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT … #define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK … #define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT … #define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK … #define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK … #define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__DATA_MASK … #define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK … #define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK … #define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK … #define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK … #define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK … #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK … #define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT … #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK … #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT … #define SQ_LB_CTR_CTRL__CLEAR_MASK … #define SQ_LB_CTR_CTRL__CLEAR__SHIFT … #define SQ_LB_CTR_CTRL__LOAD_MASK … #define SQ_LB_CTR_CTRL__LOAD__SHIFT … #define SQ_LB_CTR_CTRL__START_MASK … #define SQ_LB_CTR_CTRL__START__SHIFT … #define SQ_LB_DATA_ALU_CYCLES__DATA_MASK … #define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT … #define SQ_LB_DATA_ALU_STALLS__DATA_MASK … #define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT … #define SQ_LB_DATA_TEX_CYCLES__DATA_MASK … #define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT … #define SQ_LB_DATA_TEX_STALLS__DATA_MASK … #define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT … #define SQ_MIMG_0__DA_MASK … #define SQ_MIMG_0__DA__SHIFT … #define SQ_MIMG_0__DMASK_MASK … #define SQ_MIMG_0__DMASK__SHIFT … #define SQ_MIMG_0__ENCODING_MASK … #define SQ_MIMG_0__ENCODING__SHIFT … #define SQ_MIMG_0__GLC_MASK … #define SQ_MIMG_0__GLC__SHIFT … #define SQ_MIMG_0__LWE_MASK … #define SQ_MIMG_0__LWE__SHIFT … #define SQ_MIMG_0__OP_MASK … #define SQ_MIMG_0__OP__SHIFT … #define SQ_MIMG_0__R128_MASK … #define SQ_MIMG_0__R128__SHIFT … #define SQ_MIMG_0__SLC_MASK … #define SQ_MIMG_0__SLC__SHIFT … #define SQ_MIMG_0__TFE_MASK … #define SQ_MIMG_0__TFE__SHIFT … #define SQ_MIMG_0__UNORM_MASK … #define SQ_MIMG_0__UNORM__SHIFT … #define SQ_MIMG_1__SRSRC_MASK … #define SQ_MIMG_1__SRSRC__SHIFT … #define SQ_MIMG_1__SSAMP_MASK … #define SQ_MIMG_1__SSAMP__SHIFT … #define SQ_MIMG_1__VADDR_MASK … #define SQ_MIMG_1__VADDR__SHIFT … #define SQ_MIMG_1__VDATA_MASK … #define SQ_MIMG_1__VDATA__SHIFT … #define SQ_MTBUF_0__ADDR64_MASK … #define SQ_MTBUF_0__ADDR64__SHIFT … #define SQ_MTBUF_0__DFMT_MASK … #define SQ_MTBUF_0__DFMT__SHIFT … #define SQ_MTBUF_0__ENCODING_MASK … #define SQ_MTBUF_0__ENCODING__SHIFT … #define SQ_MTBUF_0__GLC_MASK … #define SQ_MTBUF_0__GLC__SHIFT … #define SQ_MTBUF_0__IDXEN_MASK … #define SQ_MTBUF_0__IDXEN__SHIFT … #define SQ_MTBUF_0__NFMT_MASK … #define SQ_MTBUF_0__NFMT__SHIFT … #define SQ_MTBUF_0__OFFEN_MASK … #define SQ_MTBUF_0__OFFEN__SHIFT … #define SQ_MTBUF_0__OFFSET_MASK … #define SQ_MTBUF_0__OFFSET__SHIFT … #define SQ_MTBUF_0__OP_MASK … #define SQ_MTBUF_0__OP__SHIFT … #define SQ_MTBUF_1__SLC_MASK … #define SQ_MTBUF_1__SLC__SHIFT … #define SQ_MTBUF_1__SOFFSET_MASK … #define SQ_MTBUF_1__SOFFSET__SHIFT … #define SQ_MTBUF_1__SRSRC_MASK … #define SQ_MTBUF_1__SRSRC__SHIFT … #define SQ_MTBUF_1__TFE_MASK … #define SQ_MTBUF_1__TFE__SHIFT … #define SQ_MTBUF_1__VADDR_MASK … #define SQ_MTBUF_1__VADDR__SHIFT … #define SQ_MTBUF_1__VDATA_MASK … #define SQ_MTBUF_1__VDATA__SHIFT … #define SQ_MUBUF_0__ADDR64_MASK … #define SQ_MUBUF_0__ADDR64__SHIFT … #define SQ_MUBUF_0__ENCODING_MASK … #define SQ_MUBUF_0__ENCODING__SHIFT … #define SQ_MUBUF_0__GLC_MASK … #define SQ_MUBUF_0__GLC__SHIFT … #define SQ_MUBUF_0__IDXEN_MASK … #define SQ_MUBUF_0__IDXEN__SHIFT … #define SQ_MUBUF_0__LDS_MASK … #define SQ_MUBUF_0__LDS__SHIFT … #define SQ_MUBUF_0__OFFEN_MASK … #define SQ_MUBUF_0__OFFEN__SHIFT … #define SQ_MUBUF_0__OFFSET_MASK … #define SQ_MUBUF_0__OFFSET__SHIFT … #define SQ_MUBUF_0__OP_MASK … #define SQ_MUBUF_0__OP__SHIFT … #define SQ_MUBUF_1__SLC_MASK … #define SQ_MUBUF_1__SLC__SHIFT … #define SQ_MUBUF_1__SOFFSET_MASK … #define SQ_MUBUF_1__SOFFSET__SHIFT … #define SQ_MUBUF_1__SRSRC_MASK … #define SQ_MUBUF_1__SRSRC__SHIFT … #define SQ_MUBUF_1__TFE_MASK … #define SQ_MUBUF_1__TFE__SHIFT … #define SQ_MUBUF_1__VADDR_MASK … #define SQ_MUBUF_1__VADDR__SHIFT … #define SQ_MUBUF_1__VDATA_MASK … #define SQ_MUBUF_1__VDATA__SHIFT … #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK … #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT … #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK … #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT … #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK … #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT … #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK … #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT … #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK … #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT … #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK … #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT … #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK … #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT … #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK … #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT … #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK … #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT … #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK … #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT … #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK … #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT … #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK … #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT … #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK … #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT … #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK … #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT … #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK … #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT … #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK … #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT … #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK … #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT … #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK … #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT … #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK … #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT … #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK … #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT … #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK … #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT … #define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK … #define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT … #define SQ_POWER_THROTTLE__MAX_POWER_MASK … #define SQ_POWER_THROTTLE__MAX_POWER__SHIFT … #define SQ_POWER_THROTTLE__MIN_POWER_MASK … #define SQ_POWER_THROTTLE__MIN_POWER__SHIFT … #define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK … #define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT … #define SQ_RANDOM_WAVE_PRI__RET_MASK … #define SQ_RANDOM_WAVE_PRI__RET__SHIFT … #define SQ_RANDOM_WAVE_PRI__RNG_MASK … #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT … #define SQ_RANDOM_WAVE_PRI__RUI_MASK … #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT … #define SQ_REG_CREDITS__CMD_CREDITS_MASK … #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT … #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK … #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT … #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK … #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT … #define SQ_REG_CREDITS__REG_BUSY_MASK … #define SQ_REG_CREDITS__REG_BUSY__SHIFT … #define SQ_REG_CREDITS__SRBM_CREDITS_MASK … #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT … #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK … #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT … #define SQ_SEC_CNT__LDS_SEC_MASK … #define SQ_SEC_CNT__LDS_SEC__SHIFT … #define SQ_SEC_CNT__SGPR_SEC_MASK … #define SQ_SEC_CNT__SGPR_SEC__SHIFT … #define SQ_SEC_CNT__VGPR_SEC_MASK … #define SQ_SEC_CNT__VGPR_SEC__SHIFT … #define SQ_SMRD__ENCODING_MASK … #define SQ_SMRD__ENCODING__SHIFT … #define SQ_SMRD__IMM_MASK … #define SQ_SMRD__IMM__SHIFT … #define SQ_SMRD__OFFSET_MASK … #define SQ_SMRD__OFFSET__SHIFT … #define SQ_SMRD__OP_MASK … #define SQ_SMRD__OP__SHIFT … #define SQ_SMRD__SBASE_MASK … #define SQ_SMRD__SBASE__SHIFT … #define SQ_SMRD__SDST_MASK … #define SQ_SMRD__SDST__SHIFT … #define SQ_SOP1__ENCODING_MASK … #define SQ_SOP1__ENCODING__SHIFT … #define SQ_SOP1__OP_MASK … #define SQ_SOP1__OP__SHIFT … #define SQ_SOP1__SDST_MASK … #define SQ_SOP1__SDST__SHIFT … #define SQ_SOP1__SSRC0_MASK … #define SQ_SOP1__SSRC0__SHIFT … #define SQ_SOP2__ENCODING_MASK … #define SQ_SOP2__ENCODING__SHIFT … #define SQ_SOP2__OP_MASK … #define SQ_SOP2__OP__SHIFT … #define SQ_SOP2__SDST_MASK … #define SQ_SOP2__SDST__SHIFT … #define SQ_SOP2__SSRC0_MASK … #define SQ_SOP2__SSRC0__SHIFT … #define SQ_SOP2__SSRC1_MASK … #define SQ_SOP2__SSRC1__SHIFT … #define SQ_SOPC__ENCODING_MASK … #define SQ_SOPC__ENCODING__SHIFT … #define SQ_SOPC__OP_MASK … #define SQ_SOPC__OP__SHIFT … #define SQ_SOPC__SSRC0_MASK … #define SQ_SOPC__SSRC0__SHIFT … #define SQ_SOPC__SSRC1_MASK … #define SQ_SOPC__SSRC1__SHIFT … #define SQ_SOPK__ENCODING_MASK … #define SQ_SOPK__ENCODING__SHIFT … #define SQ_SOPK__OP_MASK … #define SQ_SOPK__OP__SHIFT … #define SQ_SOPK__SDST_MASK … #define SQ_SOPK__SDST__SHIFT … #define SQ_SOPK__SIMM16_MASK … #define SQ_SOPK__SIMM16__SHIFT … #define SQ_SOPP__ENCODING_MASK … #define SQ_SOPP__ENCODING__SHIFT … #define SQ_SOPP__OP_MASK … #define SQ_SOPP__OP__SHIFT … #define SQ_SOPP__SIMM16_MASK … #define SQ_SOPP__SIMM16__SHIFT … #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK … #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT … #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK … #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT … #define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK … #define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT … #define SQ_THREAD_TRACE_BASE2__ATC_MASK … #define SQ_THREAD_TRACE_BASE2__ATC__SHIFT … #define SQ_THREAD_TRACE_BASE__ADDR_MASK … #define SQ_THREAD_TRACE_BASE__ADDR__SHIFT … #define SQ_THREAD_TRACE_CNTR__CNTR_MASK … #define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT … #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK … #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT … #define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK … #define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT … #define SQ_THREAD_TRACE_MASK__CU_SEL_MASK … #define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT … #define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK … #define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT … #define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK … #define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT … #define SQ_THREAD_TRACE_MASK__SH_SEL_MASK … #define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT … #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK … #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT … #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK … #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT … #define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK … #define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT … #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK … #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT … #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK … #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT … #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK … #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT … #define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK … #define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT … #define SQ_THREAD_TRACE_MODE__MASK_CS_MASK … #define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT … #define SQ_THREAD_TRACE_MODE__MASK_ES_MASK … #define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT … #define SQ_THREAD_TRACE_MODE__MASK_GS_MASK … #define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT … #define SQ_THREAD_TRACE_MODE__MASK_HS_MASK … #define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT … #define SQ_THREAD_TRACE_MODE__MASK_LS_MASK … #define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT … #define SQ_THREAD_TRACE_MODE__MASK_PS_MASK … #define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT … #define SQ_THREAD_TRACE_MODE__MASK_VS_MASK … #define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT … #define SQ_THREAD_TRACE_MODE__MODE_MASK … #define SQ_THREAD_TRACE_MODE__MODE__SHIFT … #define SQ_THREAD_TRACE_MODE__PRIV_MASK … #define SQ_THREAD_TRACE_MODE__PRIV__SHIFT … #define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK … #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT … #define SQ_THREAD_TRACE_MODE__WRAP_MASK … #define SQ_THREAD_TRACE_MODE__WRAP__SHIFT … #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK … #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT … #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK … #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT … #define SQ_THREAD_TRACE_SIZE__SIZE_MASK … #define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT … #define SQ_THREAD_TRACE_STATUS__BUSY_MASK … #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT … #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK … #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT … #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK … #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT … #define SQ_THREAD_TRACE_STATUS__FULL_MASK … #define SQ_THREAD_TRACE_STATUS__FULL__SHIFT … #define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK … #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT … #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK … #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT … #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK … #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT … #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK … #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT … #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK … #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT … #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK … #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT … #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK … #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT … #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK … #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT … #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK … #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT … #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK … #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK … #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT … #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK … #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK … #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT … #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK … #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK … #define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT … #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK … #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT … #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK … #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK … #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK … #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK … #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT … #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK … #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK … #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT … #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK … #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT … #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK … #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK … #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK … #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT … #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK … #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT … #define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK … #define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT … #define SQ_THREAD_TRACE_WPTR__WPTR_MASK … #define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT … #define SQ_TIME_HI__TIME_MASK … #define SQ_TIME_HI__TIME__SHIFT … #define SQ_TIME_LO__TIME_MASK … #define SQ_TIME_LO__TIME__SHIFT … #define SQ_VINTRP__ATTRCHAN_MASK … #define SQ_VINTRP__ATTRCHAN__SHIFT … #define SQ_VINTRP__ATTR_MASK … #define SQ_VINTRP__ATTR__SHIFT … #define SQ_VINTRP__ENCODING_MASK … #define SQ_VINTRP__ENCODING__SHIFT … #define SQ_VINTRP__OP_MASK … #define SQ_VINTRP__OP__SHIFT … #define SQ_VINTRP__VDST_MASK … #define SQ_VINTRP__VDST__SHIFT … #define SQ_VINTRP__VSRC_MASK … #define SQ_VINTRP__VSRC__SHIFT … #define SQ_VOP1__ENCODING_MASK … #define SQ_VOP1__ENCODING__SHIFT … #define SQ_VOP1__OP_MASK … #define SQ_VOP1__OP__SHIFT … #define SQ_VOP1__SRC0_MASK … #define SQ_VOP1__SRC0__SHIFT … #define SQ_VOP1__VDST_MASK … #define SQ_VOP1__VDST__SHIFT … #define SQ_VOP2__ENCODING_MASK … #define SQ_VOP2__ENCODING__SHIFT … #define SQ_VOP2__OP_MASK … #define SQ_VOP2__OP__SHIFT … #define SQ_VOP2__SRC0_MASK … #define SQ_VOP2__SRC0__SHIFT … #define SQ_VOP2__VDST_MASK … #define SQ_VOP2__VDST__SHIFT … #define SQ_VOP2__VSRC1_MASK … #define SQ_VOP2__VSRC1__SHIFT … #define SQ_VOP3_0__ABS_MASK … #define SQ_VOP3_0__ABS__SHIFT … #define SQ_VOP3_0__CLAMP_MASK … #define SQ_VOP3_0__CLAMP__SHIFT … #define SQ_VOP3_0__ENCODING_MASK … #define SQ_VOP3_0__ENCODING__SHIFT … #define SQ_VOP3_0__OP_MASK … #define SQ_VOP3_0__OP__SHIFT … #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK … #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT … #define SQ_VOP3_0_SDST_ENC__OP_MASK … #define SQ_VOP3_0_SDST_ENC__OP__SHIFT … #define SQ_VOP3_0_SDST_ENC__SDST_MASK … #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT … #define SQ_VOP3_0_SDST_ENC__VDST_MASK … #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT … #define SQ_VOP3_0__VDST_MASK … #define SQ_VOP3_0__VDST__SHIFT … #define SQ_VOP3_1__NEG_MASK … #define SQ_VOP3_1__NEG__SHIFT … #define SQ_VOP3_1__OMOD_MASK … #define SQ_VOP3_1__OMOD__SHIFT … #define SQ_VOP3_1__SRC0_MASK … #define SQ_VOP3_1__SRC0__SHIFT … #define SQ_VOP3_1__SRC1_MASK … #define SQ_VOP3_1__SRC1__SHIFT … #define SQ_VOP3_1__SRC2_MASK … #define SQ_VOP3_1__SRC2__SHIFT … #define SQ_VOPC__ENCODING_MASK … #define SQ_VOPC__ENCODING__SHIFT … #define SQ_VOPC__OP_MASK … #define SQ_VOPC__OP__SHIFT … #define SQ_VOPC__SRC0_MASK … #define SQ_VOPC__SRC0__SHIFT … #define SQ_VOPC__VSRC1_MASK … #define SQ_VOPC__VSRC1__SHIFT … #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK … #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT … #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK … #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT … #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK … #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT … #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK … #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT … #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK … #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT … #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK … #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT … #define SQ_WAVE_HW_ID__CU_ID_MASK … #define SQ_WAVE_HW_ID__CU_ID__SHIFT … #define SQ_WAVE_HW_ID__ME_ID_MASK … #define SQ_WAVE_HW_ID__ME_ID__SHIFT … #define SQ_WAVE_HW_ID__PIPE_ID_MASK … #define SQ_WAVE_HW_ID__PIPE_ID__SHIFT … #define SQ_WAVE_HW_ID__QUEUE_ID_MASK … #define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT … #define SQ_WAVE_HW_ID__SE_ID_MASK … #define SQ_WAVE_HW_ID__SE_ID__SHIFT … #define SQ_WAVE_HW_ID__SH_ID_MASK … #define SQ_WAVE_HW_ID__SH_ID__SHIFT … #define SQ_WAVE_HW_ID__SIMD_ID_MASK … #define SQ_WAVE_HW_ID__SIMD_ID__SHIFT … #define SQ_WAVE_HW_ID__STATE_ID_MASK … #define SQ_WAVE_HW_ID__STATE_ID__SHIFT … #define SQ_WAVE_HW_ID__TG_ID_MASK … #define SQ_WAVE_HW_ID__TG_ID__SHIFT … #define SQ_WAVE_HW_ID__VM_ID_MASK … #define SQ_WAVE_HW_ID__VM_ID__SHIFT … #define SQ_WAVE_HW_ID__WAVE_ID_MASK … #define SQ_WAVE_HW_ID__WAVE_ID__SHIFT … #define SQ_WAVE_IB_DBG0__ECC_ST_MASK … #define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT … #define SQ_WAVE_IB_DBG0__HYB_CNT_MASK … #define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT … #define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK … #define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT … #define SQ_WAVE_IB_DBG0__IBUF_ST_MASK … #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT … #define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK … #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT … #define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK … #define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT … #define SQ_WAVE_IB_DBG0__IS_HYB_MASK … #define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT … #define SQ_WAVE_IB_DBG0__KILL_MASK … #define SQ_WAVE_IB_DBG0__KILL__SHIFT … #define SQ_WAVE_IB_DBG0__MISC_CNT_MASK … #define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT … #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK … #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT … #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK … #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT … #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK … #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT … #define SQ_WAVE_IB_DBG0__PC_INVALID_MASK … #define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT … #define SQ_WAVE_IB_STS__EXP_CNT_MASK … #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT … #define SQ_WAVE_IB_STS__LGKM_CNT_MASK … #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT … #define SQ_WAVE_IB_STS__VALU_CNT_MASK … #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT … #define SQ_WAVE_IB_STS__VM_CNT_MASK … #define SQ_WAVE_IB_STS__VM_CNT__SHIFT … #define SQ_WAVE_INST_DW0__INST_DW0_MASK … #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT … #define SQ_WAVE_INST_DW1__INST_DW1_MASK … #define SQ_WAVE_INST_DW1__INST_DW1__SHIFT … #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK … #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT … #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK … #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT … #define SQ_WAVE_M0__M0_MASK … #define SQ_WAVE_M0__M0__SHIFT … #define SQ_WAVE_MODE__CSP_MASK … #define SQ_WAVE_MODE__CSP__SHIFT … #define SQ_WAVE_MODE__DEBUG_EN_MASK … #define SQ_WAVE_MODE__DEBUG_EN__SHIFT … #define SQ_WAVE_MODE__DX10_CLAMP_MASK … #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT … #define SQ_WAVE_MODE__EXCP_EN_MASK … #define SQ_WAVE_MODE__EXCP_EN__SHIFT … #define SQ_WAVE_MODE__FP_DENORM_MASK … #define SQ_WAVE_MODE__FP_DENORM__SHIFT … #define SQ_WAVE_MODE__FP_ROUND_MASK … #define SQ_WAVE_MODE__FP_ROUND__SHIFT … #define SQ_WAVE_MODE__IEEE_MASK … #define SQ_WAVE_MODE__IEEE__SHIFT … #define SQ_WAVE_MODE__LOD_CLAMPED_MASK … #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT … #define SQ_WAVE_MODE__VSKIP_MASK … #define SQ_WAVE_MODE__VSKIP__SHIFT … #define SQ_WAVE_PC_HI__PC_HI_MASK … #define SQ_WAVE_PC_HI__PC_HI__SHIFT … #define SQ_WAVE_PC_LO__PC_LO_MASK … #define SQ_WAVE_PC_LO__PC_LO__SHIFT … #define SQ_WAVE_STATUS__COND_DBG_SYS_MASK … #define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT … #define SQ_WAVE_STATUS__COND_DBG_USER_MASK … #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT … #define SQ_WAVE_STATUS__DATA_ATC_MASK … #define SQ_WAVE_STATUS__DATA_ATC__SHIFT … #define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK … #define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT … #define SQ_WAVE_STATUS__ECC_ERR_MASK … #define SQ_WAVE_STATUS__ECC_ERR__SHIFT … #define SQ_WAVE_STATUS__EXECZ_MASK … #define SQ_WAVE_STATUS__EXECZ__SHIFT … #define SQ_WAVE_STATUS__EXPORT_RDY_MASK … #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT … #define SQ_WAVE_STATUS__HALT_MASK … #define SQ_WAVE_STATUS__HALT__SHIFT … #define SQ_WAVE_STATUS__IN_BARRIER_MASK … #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT … #define SQ_WAVE_STATUS__INST_ATC_MASK … #define SQ_WAVE_STATUS__INST_ATC__SHIFT … #define SQ_WAVE_STATUS__IN_TG_MASK … #define SQ_WAVE_STATUS__IN_TG__SHIFT … #define SQ_WAVE_STATUS__MUST_EXPORT_MASK … #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT … #define SQ_WAVE_STATUS__PERF_EN_MASK … #define SQ_WAVE_STATUS__PERF_EN__SHIFT … #define SQ_WAVE_STATUS__PRIV_MASK … #define SQ_WAVE_STATUS__PRIV__SHIFT … #define SQ_WAVE_STATUS__SCC_MASK … #define SQ_WAVE_STATUS__SCC__SHIFT … #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK … #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT … #define SQ_WAVE_STATUS__SPI_PRIO_MASK … #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT … #define SQ_WAVE_STATUS__TRAP_EN_MASK … #define SQ_WAVE_STATUS__TRAP_EN__SHIFT … #define SQ_WAVE_STATUS__TRAP_MASK … #define SQ_WAVE_STATUS__TRAP__SHIFT … #define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK … #define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT … #define SQ_WAVE_STATUS__TTRACE_EN_MASK … #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT … #define SQ_WAVE_STATUS__VALID_MASK … #define SQ_WAVE_STATUS__VALID__SHIFT … #define SQ_WAVE_STATUS__VCCZ_MASK … #define SQ_WAVE_STATUS__VCCZ__SHIFT … #define SQ_WAVE_STATUS__WAVE_PRIO_MASK … #define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT … #define SQ_WAVE_TBA_HI__ADDR_HI_MASK … #define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT … #define SQ_WAVE_TBA_LO__ADDR_LO_MASK … #define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT … #define SQ_WAVE_TMA_HI__ADDR_HI_MASK … #define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT … #define SQ_WAVE_TMA_LO__ADDR_LO_MASK … #define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT … #define SQ_WAVE_TRAPSTS__DP_RATE_MASK … #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT … #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK … #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT … #define SQ_WAVE_TRAPSTS__EXCP_MASK … #define SQ_WAVE_TRAPSTS__EXCP__SHIFT … #define SQ_WAVE_TTMP0__DATA_MASK … #define SQ_WAVE_TTMP0__DATA__SHIFT … #define SQ_WAVE_TTMP10__DATA_MASK … #define SQ_WAVE_TTMP10__DATA__SHIFT … #define SQ_WAVE_TTMP11__DATA_MASK … #define SQ_WAVE_TTMP11__DATA__SHIFT … #define SQ_WAVE_TTMP1__DATA_MASK … #define SQ_WAVE_TTMP1__DATA__SHIFT … #define SQ_WAVE_TTMP2__DATA_MASK … #define SQ_WAVE_TTMP2__DATA__SHIFT … #define SQ_WAVE_TTMP3__DATA_MASK … #define SQ_WAVE_TTMP3__DATA__SHIFT … #define SQ_WAVE_TTMP4__DATA_MASK … #define SQ_WAVE_TTMP4__DATA__SHIFT … #define SQ_WAVE_TTMP5__DATA_MASK … #define SQ_WAVE_TTMP5__DATA__SHIFT … #define SQ_WAVE_TTMP6__DATA_MASK … #define SQ_WAVE_TTMP6__DATA__SHIFT … #define SQ_WAVE_TTMP7__DATA_MASK … #define SQ_WAVE_TTMP7__DATA__SHIFT … #define SQ_WAVE_TTMP8__DATA_MASK … #define SQ_WAVE_TTMP8__DATA__SHIFT … #define SQ_WAVE_TTMP9__DATA_MASK … #define SQ_WAVE_TTMP9__DATA__SHIFT … #define SX_DEBUG_1__DEBUG_DATA_MASK … #define SX_DEBUG_1__DEBUG_DATA__SHIFT … #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK … #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT … #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK … #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK … #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK … #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK … #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK … #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK … #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK … #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT … #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK … #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT … #define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK … #define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK … #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY_4__RESERVED_MASK … #define SX_DEBUG_BUSY_4__RESERVED__SHIFT … #define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK … #define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT … #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK … #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT … #define SX_DEBUG_BUSY__PA_SX_BUSY_MASK … #define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT … #define SX_DEBUG_BUSY__PCCMD_VALID_MASK … #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT … #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK … #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK … #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT … #define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK … #define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT … #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK … #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT … #define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK … #define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT … #define SX_DEBUG_BUSY__VDATA0_VALID_MASK … #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT … #define SX_DEBUG_BUSY__VDATA1_VALID_MASK … #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT … #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK … #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT … #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK … #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT … #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK … #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT … #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK … #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT … #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK … #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT … #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK … #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT … #define SXIFCCG_DEBUG_REG0__point_address_MASK … #define SXIFCCG_DEBUG_REG0__point_address__SHIFT … #define SXIFCCG_DEBUG_REG0__position_address_MASK … #define SXIFCCG_DEBUG_REG0__position_address__SHIFT … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK … #define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT … #define SXIFCCG_DEBUG_REG1__aux_sel_MASK … #define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT … #define SXIFCCG_DEBUG_REG1__available_positions_MASK … #define SXIFCCG_DEBUG_REG1__available_positions__SHIFT … #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK … #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT … #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK … #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT … #define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK … #define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT … #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK … #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT … #define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK … #define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT … #define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK … #define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT … #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK … #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT … #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK … #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT … #define SXIFCCG_DEBUG_REG2__param_cache_base_MASK … #define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT … #define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK … #define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT … #define SXIFCCG_DEBUG_REG2__req_active_verts_MASK … #define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT … #define SXIFCCG_DEBUG_REG2__sx_aux_MASK … #define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT … #define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK … #define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT … #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK … #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT … #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK … #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT … #define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK … #define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT … #define SXIFCCG_DEBUG_REG3__available_positions_MASK … #define SXIFCCG_DEBUG_REG3__available_positions__SHIFT … #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK … #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT … #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK … #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT … #define SXIFCCG_DEBUG_REG3__current_state_MASK … #define SXIFCCG_DEBUG_REG3__current_state__SHIFT … #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK … #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT … #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK … #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT … #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK … #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT … #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK … #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT … #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK … #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT … #define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK … #define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT … #define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK … #define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT … #define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK … #define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT … #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK … #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT … #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK … #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT … #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK … #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT … #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK … #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT … #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK … #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT … #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK … #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT … #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK … #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT … #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK … #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT … #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK … #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT … #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK … #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT … #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK … #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT … #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK … #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT … #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK … #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT … #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK … #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT … #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK … #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT … #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK … #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT … #define TA_BC_BASE_ADDR__ADDRESS_MASK … #define TA_BC_BASE_ADDR__ADDRESS__SHIFT … #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK … #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT … #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK … #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT … #define TA_CGTT_CTRL__ON_DELAY_MASK … #define TA_CGTT_CTRL__ON_DELAY__SHIFT … #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK … #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT … #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK … #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT … #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK … #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT … #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK … #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT … #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK … #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT … #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK … #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT … #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK … #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT … #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK … #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT … #define TA_CNTL__ALIGNER_CREDIT_MASK … #define TA_CNTL__ALIGNER_CREDIT__SHIFT … #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK … #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT … #define TA_CNTL__TC_DATA_CREDIT_MASK … #define TA_CNTL__TC_DATA_CREDIT__SHIFT … #define TA_CNTL__TD_FIFO_CREDIT_MASK … #define TA_CNTL__TD_FIFO_CREDIT__SHIFT … #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK … #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT … #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK … #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT … #define TA_DEBUG_DATA__DATA_MASK … #define TA_DEBUG_DATA__DATA__SHIFT … #define TA_DEBUG_INDEX__INDEX_MASK … #define TA_DEBUG_INDEX__INDEX__SHIFT … #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK … #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT … #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK … #define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT … #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK … #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT … #define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK … #define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT … #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define TA_SCRATCH__SCRATCH_MASK … #define TA_SCRATCH__SCRATCH__SHIFT … #define TA_STATUS__AL_BUSY_MASK … #define TA_STATUS__AL_BUSY__SHIFT … #define TA_STATUS__BUSY_MASK … #define TA_STATUS__BUSY__SHIFT … #define TA_STATUS__FA_BUSY_MASK … #define TA_STATUS__FA_BUSY__SHIFT … #define TA_STATUS__FA_LFIFO_EMPTYB_MASK … #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT … #define TA_STATUS__FA_PFIFO_EMPTYB_MASK … #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT … #define TA_STATUS__FA_SFIFO_EMPTYB_MASK … #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT … #define TA_STATUS__FG_BUSY_MASK … #define TA_STATUS__FG_BUSY__SHIFT … #define TA_STATUS__FG_LFIFO_EMPTYB_MASK … #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT … #define TA_STATUS__FG_PFIFO_EMPTYB_MASK … #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT … #define TA_STATUS__FG_SFIFO_EMPTYB_MASK … #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT … #define TA_STATUS__FL_BUSY_MASK … #define TA_STATUS__FL_BUSY__SHIFT … #define TA_STATUS__FL_LFIFO_EMPTYB_MASK … #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT … #define TA_STATUS__FL_PFIFO_EMPTYB_MASK … #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT … #define TA_STATUS__FL_SFIFO_EMPTYB_MASK … #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT … #define TA_STATUS__IN_BUSY_MASK … #define TA_STATUS__IN_BUSY__SHIFT … #define TA_STATUS__LA_BUSY_MASK … #define TA_STATUS__LA_BUSY__SHIFT … #define TA_STATUS__TA_BUSY_MASK … #define TA_STATUS__TA_BUSY__SHIFT … #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK … #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT … #define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK … #define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK … #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define TCA_CTRL__HOLE_TIMEOUT_MASK … #define TCA_CTRL__HOLE_TIMEOUT__SHIFT … #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK … #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT … #define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK … #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT … #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK … #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT … #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK … #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT … #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK … #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK … #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT … #define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK … #define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT … #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK … #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT … #define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK … #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT … #define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK … #define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT … #define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK … #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT … #define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK … #define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT … #define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK … #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT … #define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK … #define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK … #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT … #define TCC_CTRL__CACHE_SIZE_MASK … #define TCC_CTRL__CACHE_SIZE__SHIFT … #define TCC_CTRL__LATENCY_FIFO_SIZE_MASK … #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT … #define TCC_CTRL__RATE_MASK … #define TCC_CTRL__RATE__SHIFT … #define TCC_CTRL__SRC_FIFO_SIZE_MASK … #define TCC_CTRL__SRC_FIFO_SIZE__SHIFT … #define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK … #define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT … #define TCC_CTRL__WRITEBACK_MARGIN_MASK … #define TCC_CTRL__WRITEBACK_MARGIN__SHIFT … #define TCC_EDC_COUNTER__DED_COUNT_MASK … #define TCC_EDC_COUNTER__DED_COUNT__SHIFT … #define TCC_EDC_COUNTER__SEC_COUNT_MASK … #define TCC_EDC_COUNTER__SEC_COUNT__SHIFT … #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK … #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT … #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK … #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT … #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK … #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT … #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK … #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT … #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK … #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK … #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT … #define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK … #define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT … #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK … #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT … #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK … #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT … #define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK … #define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT … #define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK … #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT … #define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK … #define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT … #define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK … #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT … #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK … #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT … #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK … #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT … #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK … #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT … #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK … #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT … #define TCI_STATUS__TCI_BUSY_MASK … #define TCI_STATUS__TCI_BUSY__SHIFT … #define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK … #define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT … #define TCP_ADDR_CONFIG__NUM_BANKS_MASK … #define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT … #define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK … #define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT … #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK … #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT … #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK … #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT … #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK … #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT … #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK … #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT … #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK … #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT … #define TCP_CHAN_STEER_HI__CHAN8_MASK … #define TCP_CHAN_STEER_HI__CHAN8__SHIFT … #define TCP_CHAN_STEER_HI__CHAN9_MASK … #define TCP_CHAN_STEER_HI__CHAN9__SHIFT … #define TCP_CHAN_STEER_HI__CHANA_MASK … #define TCP_CHAN_STEER_HI__CHANA__SHIFT … #define TCP_CHAN_STEER_HI__CHANB_MASK … #define TCP_CHAN_STEER_HI__CHANB__SHIFT … #define TCP_CHAN_STEER_HI__CHANC_MASK … #define TCP_CHAN_STEER_HI__CHANC__SHIFT … #define TCP_CHAN_STEER_HI__CHAND_MASK … #define TCP_CHAN_STEER_HI__CHAND__SHIFT … #define TCP_CHAN_STEER_HI__CHANE_MASK … #define TCP_CHAN_STEER_HI__CHANE__SHIFT … #define TCP_CHAN_STEER_HI__CHANF_MASK … #define TCP_CHAN_STEER_HI__CHANF__SHIFT … #define TCP_CHAN_STEER_LO__CHAN0_MASK … #define TCP_CHAN_STEER_LO__CHAN0__SHIFT … #define TCP_CHAN_STEER_LO__CHAN1_MASK … #define TCP_CHAN_STEER_LO__CHAN1__SHIFT … #define TCP_CHAN_STEER_LO__CHAN2_MASK … #define TCP_CHAN_STEER_LO__CHAN2__SHIFT … #define TCP_CHAN_STEER_LO__CHAN3_MASK … #define TCP_CHAN_STEER_LO__CHAN3__SHIFT … #define TCP_CHAN_STEER_LO__CHAN4_MASK … #define TCP_CHAN_STEER_LO__CHAN4__SHIFT … #define TCP_CHAN_STEER_LO__CHAN5_MASK … #define TCP_CHAN_STEER_LO__CHAN5__SHIFT … #define TCP_CHAN_STEER_LO__CHAN6_MASK … #define TCP_CHAN_STEER_LO__CHAN6__SHIFT … #define TCP_CHAN_STEER_LO__CHAN7_MASK … #define TCP_CHAN_STEER_LO__CHAN7__SHIFT … #define TCP_CNTL__DISABLE_Z_MAP_MASK … #define TCP_CNTL__DISABLE_Z_MAP__SHIFT … #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK … #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT … #define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK … #define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT … #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK … #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT … #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK … #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT … #define TCP_CNTL__FORCE_HIT_MASK … #define TCP_CNTL__FORCE_HIT__SHIFT … #define TCP_CNTL__FORCE_MISS_MASK … #define TCP_CNTL__FORCE_MISS__SHIFT … #define TCP_CNTL__INV_ALL_VMIDS_MASK … #define TCP_CNTL__INV_ALL_VMIDS__SHIFT … #define TCP_CNTL__L1_SIZE_MASK … #define TCP_CNTL__L1_SIZE__SHIFT … #define TCP_CREDIT__LFIFO_CREDIT_MASK … #define TCP_CREDIT__LFIFO_CREDIT__SHIFT … #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK … #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT … #define TCP_CREDIT__TD_CREDIT_MASK … #define TCP_CREDIT__TD_CREDIT__SHIFT … #define TCP_EDC_COUNTER__DED_COUNT_MASK … #define TCP_EDC_COUNTER__DED_COUNT__SHIFT … #define TCP_EDC_COUNTER__SEC_COUNT_MASK … #define TCP_EDC_COUNTER__SEC_COUNT__SHIFT … #define TCP_INVALIDATE__START_MASK … #define TCP_INVALIDATE__START__SHIFT … #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK … #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT … #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK … #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT … #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK … #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT … #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK … #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT … #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK … #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK … #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT … #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK … #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT … #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK … #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT … #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK … #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT … #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK … #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT … #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK … #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT … #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK … #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT … #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define TCP_STATUS__TCP_BUSY_MASK … #define TCP_STATUS__TCP_BUSY__SHIFT … #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK … #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT … #define TD_CGTT_CTRL__ON_DELAY_MASK … #define TD_CGTT_CTRL__ON_DELAY__SHIFT … #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK … #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT … #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK … #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT … #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK … #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT … #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK … #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT … #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK … #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT … #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK … #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT … #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK … #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT … #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK … #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT … #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK … #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT … #define TD_CNTL__EXTEND_LDS_STALL_MASK … #define TD_CNTL__EXTEND_LDS_STALL__SHIFT … #define TD_CNTL__GATHER4_DX9_MODE_MASK … #define TD_CNTL__GATHER4_DX9_MODE__SHIFT … #define TD_CNTL__GATHER4_FLOAT_MODE_MASK … #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT … #define TD_CNTL__LD_FLOAT_MODE_MASK … #define TD_CNTL__LD_FLOAT_MODE__SHIFT … #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK … #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT … #define TD_CNTL__PAD_STALL_EN_MASK … #define TD_CNTL__PAD_STALL_EN__SHIFT … #define TD_CNTL__PRECISION_COMPATIBILITY_MASK … #define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT … #define TD_CNTL__SYNC_PHASE_SH_MASK … #define TD_CNTL__SYNC_PHASE_SH__SHIFT … #define TD_CNTL__SYNC_PHASE_VC_SMX_MASK … #define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT … #define TD_DEBUG_DATA__DATA_MASK … #define TD_DEBUG_DATA__DATA__SHIFT … #define TD_DEBUG_INDEX__INDEX_MASK … #define TD_DEBUG_INDEX__INDEX__SHIFT … #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK … #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT … #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define TD_SCRATCH__SCRATCH_MASK … #define TD_SCRATCH__SCRATCH__SHIFT … #define TD_STATUS__BUSY_MASK … #define TD_STATUS__BUSY__SHIFT … #define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK … #define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT … #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK … #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT … #define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK … #define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT … #define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK … #define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT … #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK … #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT … #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK … #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT … #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK … #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT … #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK … #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT … #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK … #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT … #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK … #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT … #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK … #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT … #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK … #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT … #define VGT_CNTL_STATUS__VGT_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT … #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK … #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT … #define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK … #define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT … #define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK … #define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT … #define VGT_DEBUG_DATA__DATA_MASK … #define VGT_DEBUG_DATA__DATA__SHIFT … #define VGT_DEBUG_REG0__cm_busy_MASK … #define VGT_DEBUG_REG0__cm_busy__SHIFT … #define VGT_DEBUG_REG0__combined_out_busy_MASK … #define VGT_DEBUG_REG0__combined_out_busy__SHIFT … #define VGT_DEBUG_REG0__core_clk_busy_MASK … #define VGT_DEBUG_REG0__core_clk_busy__SHIFT … #define VGT_DEBUG_REG0__frmt_busy_MASK … #define VGT_DEBUG_REG0__frmt_busy__SHIFT … #define VGT_DEBUG_REG0__gog_busy_MASK … #define VGT_DEBUG_REG0__gog_busy__SHIFT … #define VGT_DEBUG_REG0__gs_busy_MASK … #define VGT_DEBUG_REG0__gs_busy__SHIFT … #define VGT_DEBUG_REG0__gs_clk_busy_MASK … #define VGT_DEBUG_REG0__gs_clk_busy__SHIFT … #define VGT_DEBUG_REG0__pa_interfaces_busy_MASK … #define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT … #define VGT_DEBUG_REG0__pi_busy_MASK … #define VGT_DEBUG_REG0__pi_busy__SHIFT … #define VGT_DEBUG_REG0__pt_pi_busy_MASK … #define VGT_DEBUG_REG0__pt_pi_busy__SHIFT … #define VGT_DEBUG_REG0__rcm_busy_MASK … #define VGT_DEBUG_REG0__rcm_busy__SHIFT … #define VGT_DEBUG_REG0__reg_clk_busy_MASK … #define VGT_DEBUG_REG0__reg_clk_busy__SHIFT … #define VGT_DEBUG_REG0__sclk_core_vld_MASK … #define VGT_DEBUG_REG0__sclk_core_vld__SHIFT … #define VGT_DEBUG_REG0__sclk_gs_vld_MASK … #define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT … #define VGT_DEBUG_REG0__SPARE0_MASK … #define VGT_DEBUG_REG0__SPARE0__SHIFT … #define VGT_DEBUG_REG0__SPARE10_MASK … #define VGT_DEBUG_REG0__SPARE10__SHIFT … #define VGT_DEBUG_REG0__SPARE1_MASK … #define VGT_DEBUG_REG0__SPARE1__SHIFT … #define VGT_DEBUG_REG0__SPARE2_MASK … #define VGT_DEBUG_REG0__SPARE2__SHIFT … #define VGT_DEBUG_REG0__SPARE3_MASK … #define VGT_DEBUG_REG0__SPARE3__SHIFT … #define VGT_DEBUG_REG0__SPARE4_MASK … #define VGT_DEBUG_REG0__SPARE4__SHIFT … #define VGT_DEBUG_REG0__SPARE5_MASK … #define VGT_DEBUG_REG0__SPARE5__SHIFT … #define VGT_DEBUG_REG0__SPARE6_MASK … #define VGT_DEBUG_REG0__SPARE6__SHIFT … #define VGT_DEBUG_REG0__SPARE7_MASK … #define VGT_DEBUG_REG0__SPARE7__SHIFT … #define VGT_DEBUG_REG0__SPARE8_MASK … #define VGT_DEBUG_REG0__SPARE8__SHIFT … #define VGT_DEBUG_REG0__SPARE9_MASK … #define VGT_DEBUG_REG0__SPARE9__SHIFT … #define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK … #define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT … #define VGT_DEBUG_REG0__te11_pi_busy_MASK … #define VGT_DEBUG_REG0__te11_pi_busy__SHIFT … #define VGT_DEBUG_REG0__te_pi_busy_MASK … #define VGT_DEBUG_REG0__te_pi_busy__SHIFT … #define VGT_DEBUG_REG0__tm_busy_MASK … #define VGT_DEBUG_REG0__tm_busy__SHIFT … #define VGT_DEBUG_REG0__vgt_busy_extended_MASK … #define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT … #define VGT_DEBUG_REG0__vgt_busy_MASK … #define VGT_DEBUG_REG0__vgt_busy__SHIFT … #define VGT_DEBUG_REG0__vr_pi_busy_MASK … #define VGT_DEBUG_REG0__vr_pi_busy__SHIFT … #define VGT_DEBUG_REG10__eopg_r2_q_MASK … #define VGT_DEBUG_REG10__eopg_r2_q__SHIFT … #define VGT_DEBUG_REG10__eotg_r2_q_MASK … #define VGT_DEBUG_REG10__eotg_r2_q__SHIFT … #define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK … #define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT … #define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK … #define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT … #define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK … #define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT … #define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK … #define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT … #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK … #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK … #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT … #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT … #define VGT_DEBUG_REG10__SPARE2_MASK … #define VGT_DEBUG_REG10__SPARE2__SHIFT … #define VGT_DEBUG_REG11__counters_available_r0_MASK … #define VGT_DEBUG_REG11__counters_available_r0__SHIFT … #define VGT_DEBUG_REG11__counters_avail_r0_MASK … #define VGT_DEBUG_REG11__counters_avail_r0__SHIFT … #define VGT_DEBUG_REG11__counters_busy_r0_MASK … #define VGT_DEBUG_REG11__counters_busy_r0__SHIFT … #define VGT_DEBUG_REG11__es_r0_rtr_MASK … #define VGT_DEBUG_REG11__es_r0_rtr__SHIFT … #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK … #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT … #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK … #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT … #define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK … #define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT … #define VGT_DEBUG_REG11__es_tbl_empty_MASK … #define VGT_DEBUG_REG11__es_tbl_empty__SHIFT … #define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK … #define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT … #define VGT_DEBUG_REG11__gs_issue_rtr_MASK … #define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT … #define VGT_DEBUG_REG11__gs_r0_rtr_MASK … #define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT … #define VGT_DEBUG_REG11__hold_eswave_MASK … #define VGT_DEBUG_REG11__hold_eswave__SHIFT … #define VGT_DEBUG_REG11__no_active_states_r0_MASK … #define VGT_DEBUG_REG11__no_active_states_r0__SHIFT … #define VGT_DEBUG_REG11__send_event_q_MASK … #define VGT_DEBUG_REG11__send_event_q__SHIFT … #define VGT_DEBUG_REG11__SPARE0_MASK … #define VGT_DEBUG_REG11__SPARE0__SHIFT … #define VGT_DEBUG_REG11__SPARE1_MASK … #define VGT_DEBUG_REG11__SPARE1__SHIFT … #define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK … #define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT … #define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK … #define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT … #define VGT_DEBUG_REG11__tm_busy_q_MASK … #define VGT_DEBUG_REG11__tm_busy_q__SHIFT … #define VGT_DEBUG_REG11__tm_noif_busy_q_MASK … #define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT … #define VGT_DEBUG_REG11__tm_out_busy_q_MASK … #define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT … #define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK … #define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT … #define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK … #define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT … #define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK … #define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT … #define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK … #define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT … #define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK … #define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT … #define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK … #define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT … #define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK … #define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT … #define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK … #define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT … #define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK … #define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT … #define VGT_DEBUG_REG11__vs_event_fifo_full_MASK … #define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT … #define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK … #define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT … #define VGT_DEBUG_REG12__gs_state0_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state1_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state2_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state3_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state4_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state5_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state6_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state7_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state8_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT … #define VGT_DEBUG_REG12__gs_state9_r0_q_MASK … #define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT … #define VGT_DEBUG_REG12__hold_eswave_eop_MASK … #define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT … #define VGT_DEBUG_REG12__SPARE0_MASK … #define VGT_DEBUG_REG12__SPARE0__SHIFT … #define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK … #define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT … #define VGT_DEBUG_REG13__es_tbl_full_MASK … #define VGT_DEBUG_REG13__es_tbl_full__SHIFT … #define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK … #define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT … #define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK … #define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT … #define VGT_DEBUG_REG13__gs_state10_r0_q_MASK … #define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT … #define VGT_DEBUG_REG13__gs_state11_r0_q_MASK … #define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT … #define VGT_DEBUG_REG13__gs_state12_r0_q_MASK … #define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT … #define VGT_DEBUG_REG13__gs_state13_r0_q_MASK … #define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT … #define VGT_DEBUG_REG13__gs_state14_r0_q_MASK … #define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT … #define VGT_DEBUG_REG13__gs_state15_r0_q_MASK … #define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT … #define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK … #define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT … #define VGT_DEBUG_REG13__SPARE0_MASK … #define VGT_DEBUG_REG13__SPARE0__SHIFT … #define VGT_DEBUG_REG13__SPARE1_MASK … #define VGT_DEBUG_REG13__SPARE1__SHIFT … #define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK … #define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT … #define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK … #define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT … #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK … #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT … #define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK … #define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT … #define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK … #define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT … #define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK … #define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT … #define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK … #define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT … #define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK … #define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT … #define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK … #define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT … #define VGT_DEBUG_REG14__SPARE0_MASK … #define VGT_DEBUG_REG14__SPARE0__SHIFT … #define VGT_DEBUG_REG14__SPARE1_MASK … #define VGT_DEBUG_REG14__SPARE1__SHIFT … #define VGT_DEBUG_REG14__SPARE2_MASK … #define VGT_DEBUG_REG14__SPARE2__SHIFT … #define VGT_DEBUG_REG14__SPARE3_MASK … #define VGT_DEBUG_REG14__SPARE3__SHIFT … #define VGT_DEBUG_REG14__SPARE8_MASK … #define VGT_DEBUG_REG14__SPARE8__SHIFT … #define VGT_DEBUG_REG14__SPARE_MASK … #define VGT_DEBUG_REG14__SPARE__SHIFT … #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK … #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT … #define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK … #define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT … #define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK … #define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT … #define VGT_DEBUG_REG15__active_sm_q_MASK … #define VGT_DEBUG_REG15__active_sm_q__SHIFT … #define VGT_DEBUG_REG15__cm_busy_q_MASK … #define VGT_DEBUG_REG15__cm_busy_q__SHIFT … #define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK … #define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT … #define VGT_DEBUG_REG15__counters_busy_q_MASK … #define VGT_DEBUG_REG15__counters_busy_q__SHIFT … #define VGT_DEBUG_REG15__counters_full_MASK … #define VGT_DEBUG_REG15__counters_full__SHIFT … #define VGT_DEBUG_REG15__entry_rdptr_q_MASK … #define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT … #define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK … #define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT … #define VGT_DEBUG_REG15__output_fifo_empty_MASK … #define VGT_DEBUG_REG15__output_fifo_empty__SHIFT … #define VGT_DEBUG_REG15__output_fifo_full_MASK … #define VGT_DEBUG_REG15__output_fifo_full__SHIFT … #define VGT_DEBUG_REG15__SPARE25_MASK … #define VGT_DEBUG_REG15__SPARE25__SHIFT … #define VGT_DEBUG_REG15__SPARE31_MASK … #define VGT_DEBUG_REG15__SPARE31__SHIFT … #define VGT_DEBUG_REG15__st_cut_mode_q_MASK … #define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT … #define VGT_DEBUG_REG16__gog_busy_MASK … #define VGT_DEBUG_REG16__gog_busy__SHIFT … #define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK … #define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT … #define VGT_DEBUG_REG16__gog_state_q_MASK … #define VGT_DEBUG_REG16__gog_state_q__SHIFT … #define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK … #define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT … #define VGT_DEBUG_REG16__indx_valid_r0_q_MASK … #define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT … #define VGT_DEBUG_REG16__indx_valid_r1_q_MASK … #define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT … #define VGT_DEBUG_REG16__indx_valid_r2_q_MASK … #define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT … #define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK … #define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT … #define VGT_DEBUG_REG16__new_vs_thread_r2_MASK … #define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT … #define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK … #define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT … #define VGT_DEBUG_REG16__prim_valid_r0_q_MASK … #define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT … #define VGT_DEBUG_REG16__prim_valid_r1_q_MASK … #define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT … #define VGT_DEBUG_REG16__prim_valid_r2_q_MASK … #define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT … #define VGT_DEBUG_REG16__r0_rtr_MASK … #define VGT_DEBUG_REG16__r0_rtr__SHIFT … #define VGT_DEBUG_REG16__r1_rtr_MASK … #define VGT_DEBUG_REG16__r1_rtr__SHIFT … #define VGT_DEBUG_REG16__r1_upstream_rtr_MASK … #define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT … #define VGT_DEBUG_REG16__r2_indx_rtr_MASK … #define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT … #define VGT_DEBUG_REG16__r2_prim_rtr_MASK … #define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT … #define VGT_DEBUG_REG16__r2_rtr_MASK … #define VGT_DEBUG_REG16__r2_rtr__SHIFT … #define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK … #define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT … #define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK … #define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT … #define VGT_DEBUG_REG16__send_event_q_MASK … #define VGT_DEBUG_REG16__send_event_q__SHIFT … #define VGT_DEBUG_REG16__SPARE24_MASK … #define VGT_DEBUG_REG16__SPARE24__SHIFT … #define VGT_DEBUG_REG16__valid_r0_q_MASK … #define VGT_DEBUG_REG16__valid_r0_q__SHIFT … #define VGT_DEBUG_REG16__valid_r1_q_MASK … #define VGT_DEBUG_REG16__valid_r1_q__SHIFT … #define VGT_DEBUG_REG16__valid_r2_q_MASK … #define VGT_DEBUG_REG16__valid_r2_q__SHIFT … #define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK … #define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT … #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK … #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT … #define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK … #define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT … #define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK … #define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT … #define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK … #define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT … #define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK … #define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT … #define VGT_DEBUG_REG18__components_valid_r0_q_MASK … #define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT … #define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK … #define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT … #define VGT_DEBUG_REG18__eop_r0_q_MASK … #define VGT_DEBUG_REG18__eop_r0_q__SHIFT … #define VGT_DEBUG_REG18__grp_vr_valid_MASK … #define VGT_DEBUG_REG18__grp_vr_valid__SHIFT … #define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK … #define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT … #define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK … #define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT … #define VGT_DEBUG_REG18__indices_to_send_q_MASK … #define VGT_DEBUG_REG18__indices_to_send_q__SHIFT … #define VGT_DEBUG_REG18__indx0_hit_d_MASK … #define VGT_DEBUG_REG18__indx0_hit_d__SHIFT … #define VGT_DEBUG_REG18__indx0_new_d_MASK … #define VGT_DEBUG_REG18__indx0_new_d__SHIFT … #define VGT_DEBUG_REG18__indx1_hit_d_MASK … #define VGT_DEBUG_REG18__indx1_hit_d__SHIFT … #define VGT_DEBUG_REG18__indx1_new_d_MASK … #define VGT_DEBUG_REG18__indx1_new_d__SHIFT … #define VGT_DEBUG_REG18__indx2_hit_d_MASK … #define VGT_DEBUG_REG18__indx2_hit_d__SHIFT … #define VGT_DEBUG_REG18__indx2_new_d_MASK … #define VGT_DEBUG_REG18__indx2_new_d__SHIFT … #define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK … #define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT … #define VGT_DEBUG_REG18__last_indx_of_prim_MASK … #define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT … #define VGT_DEBUG_REG18__null_primitive_r0_q_MASK … #define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT … #define VGT_DEBUG_REG18__out_vr_indx_read_MASK … #define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT … #define VGT_DEBUG_REG18__out_vr_prim_read_MASK … #define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT … #define VGT_DEBUG_REG18__pipe0_dr_MASK … #define VGT_DEBUG_REG18__pipe0_dr__SHIFT … #define VGT_DEBUG_REG18__pipe0_rtr_MASK … #define VGT_DEBUG_REG18__pipe0_rtr__SHIFT … #define VGT_DEBUG_REG18__pipe1_dr_MASK … #define VGT_DEBUG_REG18__pipe1_dr__SHIFT … #define VGT_DEBUG_REG18__pipe1_rtr_MASK … #define VGT_DEBUG_REG18__pipe1_rtr__SHIFT … #define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK … #define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT … #define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK … #define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT … #define VGT_DEBUG_REG18__valid_indices_MASK … #define VGT_DEBUG_REG18__valid_indices__SHIFT … #define VGT_DEBUG_REG18__vr_grp_read_MASK … #define VGT_DEBUG_REG18__vr_grp_read__SHIFT … #define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK … #define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT … #define VGT_DEBUG_REG19__buffered_prim_eop_MASK … #define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT … #define VGT_DEBUG_REG19__buffered_prim_event_MASK … #define VGT_DEBUG_REG19__buffered_prim_event__SHIFT … #define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK … #define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT … #define VGT_DEBUG_REG19__buffered_prim_type_event_MASK … #define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT … #define VGT_DEBUG_REG19__filter_event_MASK … #define VGT_DEBUG_REG19__filter_event__SHIFT … #define VGT_DEBUG_REG19__hold_prim_MASK … #define VGT_DEBUG_REG19__hold_prim__SHIFT … #define VGT_DEBUG_REG19__new_packet_q_MASK … #define VGT_DEBUG_REG19__new_packet_q__SHIFT … #define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK … #define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT … #define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK … #define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT … #define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK … #define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT … #define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK … #define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT … #define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK … #define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT … #define VGT_DEBUG_REG19__prim_buffer_empty_MASK … #define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT … #define VGT_DEBUG_REG19__prim_buffer_full_MASK … #define VGT_DEBUG_REG19__prim_buffer_full__SHIFT … #define VGT_DEBUG_REG19__separate_out_busy_q_MASK … #define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT … #define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK … #define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT … #define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK … #define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT … #define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK … #define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT … #define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK … #define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT … #define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK … #define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT … #define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK … #define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT … #define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK … #define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT … #define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK … #define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT … #define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK … #define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT … #define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK … #define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT … #define VGT_DEBUG_REG1__gog_out_indx_valid_MASK … #define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT … #define VGT_DEBUG_REG1__gog_out_prim_valid_MASK … #define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT … #define VGT_DEBUG_REG1__gs_pi_read_MASK … #define VGT_DEBUG_REG1__gs_pi_read__SHIFT … #define VGT_DEBUG_REG1__out_indx_read_MASK … #define VGT_DEBUG_REG1__out_indx_read__SHIFT … #define VGT_DEBUG_REG1__out_prim_read_MASK … #define VGT_DEBUG_REG1__out_prim_read__SHIFT … #define VGT_DEBUG_REG1__pi_gs_valid_MASK … #define VGT_DEBUG_REG1__pi_gs_valid__SHIFT … #define VGT_DEBUG_REG1__pi_pt_valid_MASK … #define VGT_DEBUG_REG1__pi_pt_valid__SHIFT … #define VGT_DEBUG_REG1__pi_te_valid_MASK … #define VGT_DEBUG_REG1__pi_te_valid__SHIFT … #define VGT_DEBUG_REG1__pi_vr_valid_MASK … #define VGT_DEBUG_REG1__pi_vr_valid__SHIFT … #define VGT_DEBUG_REG1__pt_out_indx_valid_MASK … #define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT … #define VGT_DEBUG_REG1__pt_out_prim_valid_MASK … #define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT … #define VGT_DEBUG_REG1__pt_pi_read_MASK … #define VGT_DEBUG_REG1__pt_pi_read__SHIFT … #define VGT_DEBUG_REG1__SPARE0_MASK … #define VGT_DEBUG_REG1__SPARE0__SHIFT … #define VGT_DEBUG_REG1__SPARE10_MASK … #define VGT_DEBUG_REG1__SPARE10__SHIFT … #define VGT_DEBUG_REG1__SPARE11_MASK … #define VGT_DEBUG_REG1__SPARE11__SHIFT … #define VGT_DEBUG_REG1__SPARE12_MASK … #define VGT_DEBUG_REG1__SPARE12__SHIFT … #define VGT_DEBUG_REG1__SPARE1_MASK … #define VGT_DEBUG_REG1__SPARE1__SHIFT … #define VGT_DEBUG_REG1__SPARE23_MASK … #define VGT_DEBUG_REG1__SPARE23__SHIFT … #define VGT_DEBUG_REG1__SPARE25_MASK … #define VGT_DEBUG_REG1__SPARE25__SHIFT … #define VGT_DEBUG_REG1__SPARE2_MASK … #define VGT_DEBUG_REG1__SPARE2__SHIFT … #define VGT_DEBUG_REG1__SPARE3_MASK … #define VGT_DEBUG_REG1__SPARE3__SHIFT … #define VGT_DEBUG_REG1__SPARE4_MASK … #define VGT_DEBUG_REG1__SPARE4__SHIFT … #define VGT_DEBUG_REG1__SPARE5_MASK … #define VGT_DEBUG_REG1__SPARE5__SHIFT … #define VGT_DEBUG_REG1__SPARE6_MASK … #define VGT_DEBUG_REG1__SPARE6__SHIFT … #define VGT_DEBUG_REG1__SPARE7_MASK … #define VGT_DEBUG_REG1__SPARE7__SHIFT … #define VGT_DEBUG_REG1__SPARE8_MASK … #define VGT_DEBUG_REG1__SPARE8__SHIFT … #define VGT_DEBUG_REG1__SPARE9_MASK … #define VGT_DEBUG_REG1__SPARE9__SHIFT … #define VGT_DEBUG_REG1__te_grp_read_MASK … #define VGT_DEBUG_REG1__te_grp_read__SHIFT … #define VGT_DEBUG_REG1__te_out_data_valid_MASK … #define VGT_DEBUG_REG1__te_out_data_valid__SHIFT … #define VGT_DEBUG_REG1__vr_out_indx_valid_MASK … #define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT … #define VGT_DEBUG_REG1__vr_out_prim_valid_MASK … #define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT … #define VGT_DEBUG_REG1__vr_pi_read_MASK … #define VGT_DEBUG_REG1__vr_pi_read__SHIFT … #define VGT_DEBUG_REG20__alloc_counter_q_MASK … #define VGT_DEBUG_REG20__alloc_counter_q__SHIFT … #define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK … #define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT … #define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK … #define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT … #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK … #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT … #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK … #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT … #define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK … #define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT … #define VGT_DEBUG_REG20__new_allocate_q_MASK … #define VGT_DEBUG_REG20__new_allocate_q__SHIFT … #define VGT_DEBUG_REG20__SPARE17_MASK … #define VGT_DEBUG_REG20__SPARE17__SHIFT … #define VGT_DEBUG_REG21__buff_full_p1_MASK … #define VGT_DEBUG_REG21__buff_full_p1__SHIFT … #define VGT_DEBUG_REG21__eopg_p0_q_MASK … #define VGT_DEBUG_REG21__eopg_p0_q__SHIFT … #define VGT_DEBUG_REG21__eotg_r2_q_MASK … #define VGT_DEBUG_REG21__eotg_r2_q__SHIFT … #define VGT_DEBUG_REG21__full_state_p1_q_MASK … #define VGT_DEBUG_REG21__full_state_p1_q__SHIFT … #define VGT_DEBUG_REG21__indx_count_q_not_0_MASK … #define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT … #define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK … #define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT … #define VGT_DEBUG_REG21__indx_side_fifo_full_MASK … #define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT … #define VGT_DEBUG_REG21__indx_side_indx_valid_MASK … #define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT … #define VGT_DEBUG_REG21__interfaces_rtr_MASK … #define VGT_DEBUG_REG21__interfaces_rtr__SHIFT … #define VGT_DEBUG_REG21__is_event_p0_q_MASK … #define VGT_DEBUG_REG21__is_event_p0_q__SHIFT … #define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK … #define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT … #define VGT_DEBUG_REG21__null_r2_q_MASK … #define VGT_DEBUG_REG21__null_r2_q__SHIFT … #define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK … #define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT … #define VGT_DEBUG_REG21__out_indx_fifo_full_MASK … #define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT … #define VGT_DEBUG_REG21__p0_dr_MASK … #define VGT_DEBUG_REG21__p0_dr__SHIFT … #define VGT_DEBUG_REG21__p0_nobp_MASK … #define VGT_DEBUG_REG21__p0_nobp__SHIFT … #define VGT_DEBUG_REG21__p0_rtr_MASK … #define VGT_DEBUG_REG21__p0_rtr__SHIFT … #define VGT_DEBUG_REG21__pipe0_dr_MASK … #define VGT_DEBUG_REG21__pipe0_dr__SHIFT … #define VGT_DEBUG_REG21__pipe0_rtr_MASK … #define VGT_DEBUG_REG21__pipe0_rtr__SHIFT … #define VGT_DEBUG_REG21__pipe1_dr_MASK … #define VGT_DEBUG_REG21__pipe1_dr__SHIFT … #define VGT_DEBUG_REG21__pipe1_rtr_MASK … #define VGT_DEBUG_REG21__pipe1_rtr__SHIFT … #define VGT_DEBUG_REG21__pipe2_dr_MASK … #define VGT_DEBUG_REG21__pipe2_dr__SHIFT … #define VGT_DEBUG_REG21__pipe2_rtr_MASK … #define VGT_DEBUG_REG21__pipe2_rtr__SHIFT … #define VGT_DEBUG_REG21__stateid_p0_q_MASK … #define VGT_DEBUG_REG21__stateid_p0_q__SHIFT … #define VGT_DEBUG_REG21__stream_id_r2_q_MASK … #define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT … #define VGT_DEBUG_REG21__strmout_valid_p1_MASK … #define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT … #define VGT_DEBUG_REG21__vsthread_buff_empty_MASK … #define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT … #define VGT_DEBUG_REG21__vsthread_buff_full_MASK … #define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT … #define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK … #define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT … #define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK … #define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT … #define VGT_DEBUG_REG22__cm_state16_MASK … #define VGT_DEBUG_REG22__cm_state16__SHIFT … #define VGT_DEBUG_REG22__cm_state17_MASK … #define VGT_DEBUG_REG22__cm_state17__SHIFT … #define VGT_DEBUG_REG22__cm_state18_MASK … #define VGT_DEBUG_REG22__cm_state18__SHIFT … #define VGT_DEBUG_REG22__cm_state19_MASK … #define VGT_DEBUG_REG22__cm_state19__SHIFT … #define VGT_DEBUG_REG22__cm_state20_MASK … #define VGT_DEBUG_REG22__cm_state20__SHIFT … #define VGT_DEBUG_REG22__cm_state21_MASK … #define VGT_DEBUG_REG22__cm_state21__SHIFT … #define VGT_DEBUG_REG22__cm_state22_MASK … #define VGT_DEBUG_REG22__cm_state22__SHIFT … #define VGT_DEBUG_REG22__cm_state23_MASK … #define VGT_DEBUG_REG22__cm_state23__SHIFT … #define VGT_DEBUG_REG22__cm_state24_MASK … #define VGT_DEBUG_REG22__cm_state24__SHIFT … #define VGT_DEBUG_REG22__cm_state25_MASK … #define VGT_DEBUG_REG22__cm_state25__SHIFT … #define VGT_DEBUG_REG22__cm_state26_MASK … #define VGT_DEBUG_REG22__cm_state26__SHIFT … #define VGT_DEBUG_REG22__cm_state27_MASK … #define VGT_DEBUG_REG22__cm_state27__SHIFT … #define VGT_DEBUG_REG22__cm_state28_MASK … #define VGT_DEBUG_REG22__cm_state28__SHIFT … #define VGT_DEBUG_REG22__cm_state29_MASK … #define VGT_DEBUG_REG22__cm_state29__SHIFT … #define VGT_DEBUG_REG22__cm_state30_MASK … #define VGT_DEBUG_REG22__cm_state30__SHIFT … #define VGT_DEBUG_REG22__cm_state31_MASK … #define VGT_DEBUG_REG22__cm_state31__SHIFT … #define VGT_DEBUG_REG23__frmt_busy_MASK … #define VGT_DEBUG_REG23__frmt_busy__SHIFT … #define VGT_DEBUG_REG23__new_verts_r2_q_MASK … #define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT … #define VGT_DEBUG_REG23__prim_dr_r2_q_MASK … #define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT … #define VGT_DEBUG_REG23__prim_fifo_empty_MASK … #define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT … #define VGT_DEBUG_REG23__prim_fifo_full_MASK … #define VGT_DEBUG_REG23__prim_fifo_full__SHIFT … #define VGT_DEBUG_REG23__prim_r2_rtr_MASK … #define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT … #define VGT_DEBUG_REG23__prim_r3_rtr_MASK … #define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT … #define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK … #define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT … #define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK … #define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT … #define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK … #define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT … #define VGT_DEBUG_REG23__SPARE_MASK … #define VGT_DEBUG_REG23__SPARE__SHIFT … #define VGT_DEBUG_REG23__vert_dr_r0_q_MASK … #define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT … #define VGT_DEBUG_REG23__vert_dr_r1_q_MASK … #define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT … #define VGT_DEBUG_REG23__vert_dr_r2_q_MASK … #define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT … #define VGT_DEBUG_REG23__vert_r0_rtr_MASK … #define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT … #define VGT_DEBUG_REG23__vert_r1_rtr_MASK … #define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT … #define VGT_DEBUG_REG23__vert_r2_rtr_MASK … #define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT … #define VGT_DEBUG_REG23__vert_r3_rtr_MASK … #define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT … #define VGT_DEBUG_REG23__verts_sent_r2_q_MASK … #define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT … #define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK … #define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT … #define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK … #define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT … #define VGT_DEBUG_REG24__SPARE31_MASK … #define VGT_DEBUG_REG24__SPARE31__SHIFT … #define VGT_DEBUG_REG25__active_sm_r0_q_MASK … #define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT … #define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK … #define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT … #define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK … #define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT … #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK … #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT … #define VGT_DEBUG_REG26__cm_state0_MASK … #define VGT_DEBUG_REG26__cm_state0__SHIFT … #define VGT_DEBUG_REG26__cm_state10_MASK … #define VGT_DEBUG_REG26__cm_state10__SHIFT … #define VGT_DEBUG_REG26__cm_state11_MASK … #define VGT_DEBUG_REG26__cm_state11__SHIFT … #define VGT_DEBUG_REG26__cm_state12_MASK … #define VGT_DEBUG_REG26__cm_state12__SHIFT … #define VGT_DEBUG_REG26__cm_state13_MASK … #define VGT_DEBUG_REG26__cm_state13__SHIFT … #define VGT_DEBUG_REG26__cm_state14_MASK … #define VGT_DEBUG_REG26__cm_state14__SHIFT … #define VGT_DEBUG_REG26__cm_state15_MASK … #define VGT_DEBUG_REG26__cm_state15__SHIFT … #define VGT_DEBUG_REG26__cm_state1_MASK … #define VGT_DEBUG_REG26__cm_state1__SHIFT … #define VGT_DEBUG_REG26__cm_state2_MASK … #define VGT_DEBUG_REG26__cm_state2__SHIFT … #define VGT_DEBUG_REG26__cm_state3_MASK … #define VGT_DEBUG_REG26__cm_state3__SHIFT … #define VGT_DEBUG_REG26__cm_state4_MASK … #define VGT_DEBUG_REG26__cm_state4__SHIFT … #define VGT_DEBUG_REG26__cm_state5_MASK … #define VGT_DEBUG_REG26__cm_state5__SHIFT … #define VGT_DEBUG_REG26__cm_state6_MASK … #define VGT_DEBUG_REG26__cm_state6__SHIFT … #define VGT_DEBUG_REG26__cm_state7_MASK … #define VGT_DEBUG_REG26__cm_state7__SHIFT … #define VGT_DEBUG_REG26__cm_state8_MASK … #define VGT_DEBUG_REG26__cm_state8__SHIFT … #define VGT_DEBUG_REG26__cm_state9_MASK … #define VGT_DEBUG_REG26__cm_state9__SHIFT … #define VGT_DEBUG_REG27__eop_p1_q_MASK … #define VGT_DEBUG_REG27__eop_p1_q__SHIFT … #define VGT_DEBUG_REG27__event_flag_p1_q_MASK … #define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT … #define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK … #define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT … #define VGT_DEBUG_REG27__gsc0_dr_MASK … #define VGT_DEBUG_REG27__gsc0_dr__SHIFT … #define VGT_DEBUG_REG27__gsc0_rtr_MASK … #define VGT_DEBUG_REG27__gsc0_rtr__SHIFT … #define VGT_DEBUG_REG27__gsc_2cycle_output_MASK … #define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT … #define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK … #define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT … #define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK … #define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT … #define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK … #define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT … #define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK … #define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT … #define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK … #define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT … #define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK … #define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT … #define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK … #define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT … #define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK … #define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT … #define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK … #define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT … #define VGT_DEBUG_REG27__pipe0_dr_MASK … #define VGT_DEBUG_REG27__pipe0_dr__SHIFT … #define VGT_DEBUG_REG27__pipe0_rtr_MASK … #define VGT_DEBUG_REG27__pipe0_rtr__SHIFT … #define VGT_DEBUG_REG27__pipe1_dr_MASK … #define VGT_DEBUG_REG27__pipe1_dr__SHIFT … #define VGT_DEBUG_REG27__pipe1_rtr_MASK … #define VGT_DEBUG_REG27__pipe1_rtr__SHIFT … #define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK … #define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT … #define VGT_DEBUG_REG28__advance_inner_point_p1_MASK … #define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT … #define VGT_DEBUG_REG28__advance_outer_point_p1_MASK … #define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT … #define VGT_DEBUG_REG28__con_state_q_MASK … #define VGT_DEBUG_REG28__con_state_q__SHIFT … #define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK … #define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT … #define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK … #define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT … #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK … #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT … #define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK … #define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT … #define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK … #define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT … #define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK … #define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT … #define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK … #define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT … #define VGT_DEBUG_REG28__outer_parity_p0_q_MASK … #define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT … #define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK … #define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT … #define VGT_DEBUG_REG28__pipe0_edge_dr_MASK … #define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT … #define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK … #define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT … #define VGT_DEBUG_REG28__pipe0_patch_dr_MASK … #define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT … #define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK … #define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT … #define VGT_DEBUG_REG28__pipe1_dr_MASK … #define VGT_DEBUG_REG28__pipe1_dr__SHIFT … #define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK … #define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT … #define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK … #define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT … #define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK … #define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT … #define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK … #define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT … #define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK … #define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT … #define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK … #define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT … #define VGT_DEBUG_REG28__pipe1_rtr_MASK … #define VGT_DEBUG_REG28__pipe1_rtr__SHIFT … #define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK … #define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT … #define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK … #define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT … #define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK … #define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT … #define VGT_DEBUG_REG28__second_cycle_q_MASK … #define VGT_DEBUG_REG28__second_cycle_q__SHIFT … #define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK … #define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT … #define VGT_DEBUG_REG29__advance_inner_point_p1_MASK … #define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT … #define VGT_DEBUG_REG29__advance_outer_point_p1_MASK … #define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT … #define VGT_DEBUG_REG29__con_state_q_MASK … #define VGT_DEBUG_REG29__con_state_q__SHIFT … #define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK … #define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT … #define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK … #define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT … #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK … #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT … #define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK … #define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT … #define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK … #define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT … #define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK … #define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT … #define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK … #define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT … #define VGT_DEBUG_REG29__outer_parity_p0_q_MASK … #define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT … #define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK … #define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT … #define VGT_DEBUG_REG29__pipe0_edge_dr_MASK … #define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT … #define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK … #define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT … #define VGT_DEBUG_REG29__pipe0_patch_dr_MASK … #define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT … #define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK … #define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT … #define VGT_DEBUG_REG29__pipe1_dr_MASK … #define VGT_DEBUG_REG29__pipe1_dr__SHIFT … #define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK … #define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT … #define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK … #define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT … #define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK … #define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT … #define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK … #define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT … #define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK … #define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT … #define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK … #define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT … #define VGT_DEBUG_REG29__pipe1_rtr_MASK … #define VGT_DEBUG_REG29__pipe1_rtr__SHIFT … #define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK … #define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT … #define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK … #define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT … #define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK … #define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT … #define VGT_DEBUG_REG29__second_cycle_q_MASK … #define VGT_DEBUG_REG29__second_cycle_q__SHIFT … #define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK … #define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT … #define VGT_DEBUG_REG2__grpModBusy_MASK … #define VGT_DEBUG_REG2__grpModBusy__SHIFT … #define VGT_DEBUG_REG2__hs_grp_busy_MASK … #define VGT_DEBUG_REG2__hs_grp_busy__SHIFT … #define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK … #define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT … #define VGT_DEBUG_REG2__hsInputFifoFull_MASK … #define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT … #define VGT_DEBUG_REG2__hs_noif_busy_MASK … #define VGT_DEBUG_REG2__hs_noif_busy__SHIFT … #define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK … #define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT … #define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK … #define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT … #define VGT_DEBUG_REG2__hsTifFifoFull_MASK … #define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT … #define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK … #define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT … #define VGT_DEBUG_REG2__hsVertFifoFull_MASK … #define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT … #define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK … #define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT … #define VGT_DEBUG_REG2__hsWaveFifoFull_MASK … #define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT … #define VGT_DEBUG_REG2__lsFwaveFlag_MASK … #define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT … #define VGT_DEBUG_REG2__ls_sh_id_MASK … #define VGT_DEBUG_REG2__ls_sh_id__SHIFT … #define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK … #define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT … #define VGT_DEBUG_REG2__lsVertFifoFull_MASK … #define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT … #define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK … #define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT … #define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK … #define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT … #define VGT_DEBUG_REG2__lsWaveFifoFull_MASK … #define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT … #define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK … #define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT … #define VGT_DEBUG_REG2__lsWaveSendFlush_MASK … #define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT … #define VGT_DEBUG_REG2__p0_dr_MASK … #define VGT_DEBUG_REG2__p0_dr__SHIFT … #define VGT_DEBUG_REG2__p0_rtr_MASK … #define VGT_DEBUG_REG2__p0_rtr__SHIFT … #define VGT_DEBUG_REG2__p0_rts_MASK … #define VGT_DEBUG_REG2__p0_rts__SHIFT … #define VGT_DEBUG_REG2__p1_dr_MASK … #define VGT_DEBUG_REG2__p1_dr__SHIFT … #define VGT_DEBUG_REG2__p1_rtr_MASK … #define VGT_DEBUG_REG2__p1_rtr__SHIFT … #define VGT_DEBUG_REG2__p1_rts_MASK … #define VGT_DEBUG_REG2__p1_rts__SHIFT … #define VGT_DEBUG_REG2__SPARE_MASK … #define VGT_DEBUG_REG2__SPARE__SHIFT … #define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK … #define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT … #define VGT_DEBUG_REG2__tfmmIsBusy_MASK … #define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT … #define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK … #define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT … #define VGT_DEBUG_REG30__event_or_null_p0_q_MASK … #define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT … #define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK … #define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT … #define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK … #define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT … #define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK … #define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT … #define VGT_DEBUG_REG30__last_tf_of_tg_MASK … #define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT … #define VGT_DEBUG_REG30__pipe0_dr_MASK … #define VGT_DEBUG_REG30__pipe0_dr__SHIFT … #define VGT_DEBUG_REG30__pipe0_rtr_MASK … #define VGT_DEBUG_REG30__pipe0_rtr__SHIFT … #define VGT_DEBUG_REG30__pipe0_tf_dr_MASK … #define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT … #define VGT_DEBUG_REG30__pipe1_rtr_MASK … #define VGT_DEBUG_REG30__pipe1_rtr__SHIFT … #define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK … #define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT … #define VGT_DEBUG_REG30__pipe2_dr_MASK … #define VGT_DEBUG_REG30__pipe2_dr__SHIFT … #define VGT_DEBUG_REG30__pipe2_rtr_MASK … #define VGT_DEBUG_REG30__pipe2_rtr__SHIFT … #define VGT_DEBUG_REG30__pipe4_dr_MASK … #define VGT_DEBUG_REG30__pipe4_dr__SHIFT … #define VGT_DEBUG_REG30__pipe4_rtr_MASK … #define VGT_DEBUG_REG30__pipe4_rtr__SHIFT … #define VGT_DEBUG_REG30__tf_fetch_state_q_MASK … #define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT … #define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK … #define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT … #define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK … #define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT … #define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK … #define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT … #define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK … #define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT … #define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK … #define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT … #define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK … #define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT … #define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK … #define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT … #define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK … #define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT … #define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK … #define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT … #define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK … #define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT … #define VGT_DEBUG_REG31__inner_ring_done_q_MASK … #define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT … #define VGT_DEBUG_REG31__outer_ring_done_q_MASK … #define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT … #define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK … #define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT … #define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK … #define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT … #define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK … #define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT … #define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK … #define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT … #define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK … #define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT … #define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK … #define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT … #define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK … #define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT … #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK … #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT … #define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK … #define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT … #define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK … #define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT … #define VGT_DEBUG_REG31__pipe0_dr_MASK … #define VGT_DEBUG_REG31__pipe0_dr__SHIFT … #define VGT_DEBUG_REG31__pipe0_rtr_MASK … #define VGT_DEBUG_REG31__pipe0_rtr__SHIFT … #define VGT_DEBUG_REG31__pipe1_inner_dr_MASK … #define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT … #define VGT_DEBUG_REG31__pipe1_outer_dr_MASK … #define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT … #define VGT_DEBUG_REG31__pipe2_inner_dr_MASK … #define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT … #define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK … #define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT … #define VGT_DEBUG_REG31__pipe2_outer_dr_MASK … #define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT … #define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK … #define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT … #define VGT_DEBUG_REG31__pipe3_inner_dr_MASK … #define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT … #define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK … #define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT … #define VGT_DEBUG_REG31__pipe3_outer_dr_MASK … #define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT … #define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK … #define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT … #define VGT_DEBUG_REG31__pipe4_inner_dr_MASK … #define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT … #define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK … #define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT … #define VGT_DEBUG_REG31__pipe4_outer_dr_MASK … #define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT … #define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK … #define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT … #define VGT_DEBUG_REG31__pipe5_inner_dr_MASK … #define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT … #define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK … #define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT … #define VGT_DEBUG_REG31__pipe5_outer_dr_MASK … #define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT … #define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK … #define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT … #define VGT_DEBUG_REG32__event_flag_p5_q_MASK … #define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT … #define VGT_DEBUG_REG32__event_null_special_p0_q_MASK … #define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT … #define VGT_DEBUG_REG32__fifos_rtr_MASK … #define VGT_DEBUG_REG32__fifos_rtr__SHIFT … #define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK … #define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT … #define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK … #define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT … #define VGT_DEBUG_REG32__first_ring_of_patch_MASK … #define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT … #define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK … #define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT … #define VGT_DEBUG_REG32__inner_fifos_rtr_MASK … #define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT … #define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK … #define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT … #define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK … #define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT … #define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK … #define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT … #define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK … #define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT … #define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK … #define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT … #define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK … #define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT … #define VGT_DEBUG_REG32__last_ring_of_patch_MASK … #define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT … #define VGT_DEBUG_REG32__outer_fifos_rtr_MASK … #define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT … #define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK … #define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT … #define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK … #define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT … #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK … #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT … #define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK … #define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT … #define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK … #define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT … #define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK … #define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT … #define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK … #define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT … #define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK … #define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT … #define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK … #define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT … #define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK … #define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT … #define VGT_DEBUG_REG32__SPARE_MASK … #define VGT_DEBUG_REG32__SPARE__SHIFT … #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK … #define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT … #define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK … #define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT … #define VGT_DEBUG_REG33__con_prim_fifo_full_MASK … #define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT … #define VGT_DEBUG_REG33__con_ring1_busy_MASK … #define VGT_DEBUG_REG33__con_ring1_busy__SHIFT … #define VGT_DEBUG_REG33__con_ring2_busy_MASK … #define VGT_DEBUG_REG33__con_ring2_busy__SHIFT … #define VGT_DEBUG_REG33__con_ring3_busy_MASK … #define VGT_DEBUG_REG33__con_ring3_busy__SHIFT … #define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK … #define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT … #define VGT_DEBUG_REG33__con_vert_fifo_full_MASK … #define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT … #define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK … #define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT … #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK … #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT … #define VGT_DEBUG_REG33__pipe0_patch_dr_MASK … #define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT … #define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK … #define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT … #define VGT_DEBUG_REG33__pipe1_dr_MASK … #define VGT_DEBUG_REG33__pipe1_dr__SHIFT … #define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK … #define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT … #define VGT_DEBUG_REG33__pipe2_dr_MASK … #define VGT_DEBUG_REG33__pipe2_dr__SHIFT … #define VGT_DEBUG_REG33__pipe2_rtr_MASK … #define VGT_DEBUG_REG33__pipe2_rtr__SHIFT … #define VGT_DEBUG_REG33__pipe3_dr_MASK … #define VGT_DEBUG_REG33__pipe3_dr__SHIFT … #define VGT_DEBUG_REG33__pipe3_rtr_MASK … #define VGT_DEBUG_REG33__pipe3_rtr__SHIFT … #define VGT_DEBUG_REG33__ring1_in_sync_q_MASK … #define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT … #define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK … #define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT … #define VGT_DEBUG_REG33__ring1_valid_p2_MASK … #define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT … #define VGT_DEBUG_REG33__ring2_in_sync_q_MASK … #define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT … #define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK … #define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT … #define VGT_DEBUG_REG33__ring2_valid_p2_MASK … #define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT … #define VGT_DEBUG_REG33__ring3_in_sync_q_MASK … #define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT … #define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK … #define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT … #define VGT_DEBUG_REG33__ring3_valid_p2_MASK … #define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT … #define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK … #define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT … #define VGT_DEBUG_REG33__tess_topology_p0_q_MASK … #define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT … #define VGT_DEBUG_REG33__tess_type_p0_q_MASK … #define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT … #define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK … #define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT … #define VGT_DEBUG_REG34__advance_inner_point_p1_MASK … #define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT … #define VGT_DEBUG_REG34__advance_outer_point_p1_MASK … #define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT … #define VGT_DEBUG_REG34__con_state_q_MASK … #define VGT_DEBUG_REG34__con_state_q__SHIFT … #define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK … #define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT … #define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK … #define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT … #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK … #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT … #define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK … #define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT … #define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK … #define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT … #define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK … #define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT … #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK … #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT … #define VGT_DEBUG_REG34__outer_parity_p0_q_MASK … #define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT … #define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK … #define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT … #define VGT_DEBUG_REG34__pipe0_edge_dr_MASK … #define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT … #define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK … #define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT … #define VGT_DEBUG_REG34__pipe0_patch_dr_MASK … #define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT … #define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK … #define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT … #define VGT_DEBUG_REG34__pipe1_dr_MASK … #define VGT_DEBUG_REG34__pipe1_dr__SHIFT … #define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK … #define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT … #define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK … #define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT … #define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK … #define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT … #define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK … #define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT … #define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK … #define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT … #define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK … #define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT … #define VGT_DEBUG_REG34__pipe1_rtr_MASK … #define VGT_DEBUG_REG34__pipe1_rtr__SHIFT … #define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK … #define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT … #define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK … #define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT … #define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK … #define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT … #define VGT_DEBUG_REG34__second_cycle_q_MASK … #define VGT_DEBUG_REG34__second_cycle_q__SHIFT … #define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK … #define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT … #define VGT_DEBUG_REG35__event_flag_p1_q_MASK … #define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT … #define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK … #define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT … #define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK … #define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT … #define VGT_DEBUG_REG35__null_flag_p1_q_MASK … #define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT … #define VGT_DEBUG_REG35__pipe0_dr_MASK … #define VGT_DEBUG_REG35__pipe0_dr__SHIFT … #define VGT_DEBUG_REG35__pipe0_rtr_MASK … #define VGT_DEBUG_REG35__pipe0_rtr__SHIFT … #define VGT_DEBUG_REG35__pipe1_dr_MASK … #define VGT_DEBUG_REG35__pipe1_dr__SHIFT … #define VGT_DEBUG_REG35__pipe1_rtr_MASK … #define VGT_DEBUG_REG35__pipe1_rtr__SHIFT … #define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK … #define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT … #define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK … #define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT … #define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK … #define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT … #define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK … #define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT … #define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK … #define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT … #define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK … #define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT … #define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK … #define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT … #define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK … #define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT … #define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK … #define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT … #define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK … #define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT … #define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK … #define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT … #define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK … #define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT … #define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK … #define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT … #define VGT_DEBUG_REG3__hsWaveRelInd_MASK … #define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT … #define VGT_DEBUG_REG3__lsPatchCnt_MASK … #define VGT_DEBUG_REG3__lsPatchCnt__SHIFT … #define VGT_DEBUG_REG3__lsTgRelInd_MASK … #define VGT_DEBUG_REG3__lsTgRelInd__SHIFT … #define VGT_DEBUG_REG3__lsWaveRelInd_MASK … #define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT … #define VGT_DEBUG_REG4__hsCpCnt_MASK … #define VGT_DEBUG_REG4__hsCpCnt__SHIFT … #define VGT_DEBUG_REG4__hsFwaveFlag_MASK … #define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT … #define VGT_DEBUG_REG4__hsPatchCnt_MASK … #define VGT_DEBUG_REG4__hsPatchCnt__SHIFT … #define VGT_DEBUG_REG4__hsPrimId_15_0_MASK … #define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT … #define VGT_DEBUG_REG4__hsWaveSendFlush_MASK … #define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT … #define VGT_DEBUG_REG4__SPARE_MASK … #define VGT_DEBUG_REG4__SPARE__SHIFT … #define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK … #define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT … #define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK … #define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT … #define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK … #define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT … #define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK … #define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT … #define VGT_DEBUG_REG5__SPARE1_MASK … #define VGT_DEBUG_REG5__SPARE1__SHIFT … #define VGT_DEBUG_REG5__SPARE2_MASK … #define VGT_DEBUG_REG5__SPARE2__SHIFT … #define VGT_DEBUG_REG5__SPARE3_MASK … #define VGT_DEBUG_REG5__SPARE3__SHIFT … #define VGT_DEBUG_REG5__SPARE4_MASK … #define VGT_DEBUG_REG5__SPARE4__SHIFT … #define VGT_DEBUG_REG6__debug_BASE_MASK … #define VGT_DEBUG_REG6__debug_BASE__SHIFT … #define VGT_DEBUG_REG6__debug_SIZE_MASK … #define VGT_DEBUG_REG6__debug_SIZE__SHIFT … #define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK … #define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT … #define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK … #define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT … #define VGT_DEBUG_REG7__hs_pipe0_dr_MASK … #define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT … #define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK … #define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT … #define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK … #define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT … #define VGT_DEBUG_REG7__SPARE_MASK … #define VGT_DEBUG_REG7__SPARE__SHIFT … #define VGT_DEBUG_REG7__TF_addr_MASK … #define VGT_DEBUG_REG7__TF_addr__SHIFT … #define VGT_DEBUG_REG8__es_gs_rtr_MASK … #define VGT_DEBUG_REG8__es_gs_rtr__SHIFT … #define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK … #define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT … #define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK … #define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT … #define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK … #define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT … #define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK … #define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT … #define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK … #define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT … #define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK … #define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT … #define VGT_DEBUG_REG8__hold_for_es_flush_MASK … #define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT … #define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK … #define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT … #define VGT_DEBUG_REG8__r0_rtr_MASK … #define VGT_DEBUG_REG8__r0_rtr__SHIFT … #define VGT_DEBUG_REG8__r1_inst_rtr_MASK … #define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT … #define VGT_DEBUG_REG8__r1_rtr_MASK … #define VGT_DEBUG_REG8__r1_rtr__SHIFT … #define VGT_DEBUG_REG8__r2_indx_rtr_MASK … #define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT … #define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK … #define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT … #define VGT_DEBUG_REG8__r2_rtr_MASK … #define VGT_DEBUG_REG8__r2_rtr__SHIFT … #define VGT_DEBUG_REG8__rcm_busy_q_MASK … #define VGT_DEBUG_REG8__rcm_busy_q__SHIFT … #define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK … #define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT … #define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK … #define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT … #define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK … #define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT … #define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK … #define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT … #define VGT_DEBUG_REG8__te_prim_fifo_full_MASK … #define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT … #define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK … #define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT … #define VGT_DEBUG_REG8__te_vert_fifo_full_MASK … #define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT … #define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK … #define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT … #define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK … #define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT … #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK … #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT … #define VGT_DEBUG_REG8__valid_r0_q_MASK … #define VGT_DEBUG_REG8__valid_r0_q__SHIFT … #define VGT_DEBUG_REG8__valid_r1_q_MASK … #define VGT_DEBUG_REG8__valid_r1_q__SHIFT … #define VGT_DEBUG_REG8__valid_r2_MASK … #define VGT_DEBUG_REG8__valid_r2_q_MASK … #define VGT_DEBUG_REG8__valid_r2_q__SHIFT … #define VGT_DEBUG_REG8__valid_r2__SHIFT … #define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK … #define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT … #define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK … #define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT … #define VGT_DEBUG_REG9__eop_indx_r3_MASK … #define VGT_DEBUG_REG9__eop_indx_r3__SHIFT … #define VGT_DEBUG_REG9__eop_prim_r3_MASK … #define VGT_DEBUG_REG9__eop_prim_r3__SHIFT … #define VGT_DEBUG_REG9__es_eov_r3_MASK … #define VGT_DEBUG_REG9__es_eov_r3__SHIFT … #define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK … #define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT … #define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK … #define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT … #define VGT_DEBUG_REG9__gs_eov_r3_MASK … #define VGT_DEBUG_REG9__gs_eov_r3__SHIFT … #define VGT_DEBUG_REG9__gs_instancing_state_q_MASK … #define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT … #define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK … #define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT … #define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK … #define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT … #define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK … #define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT … #define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK … #define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT … #define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK … #define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT … #define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK … #define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT … #define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK … #define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT … #define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK … #define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT … #define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK … #define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT … #define VGT_DEBUG_REG9__pending_es_flush_r3_MASK … #define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT … #define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK … #define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT … #define VGT_DEBUG_REG9__pre_r0_rtr_MASK … #define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT … #define VGT_DEBUG_REG9__SPARE0_MASK … #define VGT_DEBUG_REG9__SPARE0__SHIFT … #define VGT_DEBUG_REG9__valid_indices_r3_MASK … #define VGT_DEBUG_REG9__valid_indices_r3__SHIFT … #define VGT_DEBUG_REG9__valid_pre_r0_q_MASK … #define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT … #define VGT_DEBUG_REG9__valid_r3_q_MASK … #define VGT_DEBUG_REG9__valid_r3_q__SHIFT … #define VGT_DMA_BASE__BASE_ADDR_MASK … #define VGT_DMA_BASE__BASE_ADDR__SHIFT … #define VGT_DMA_BASE_HI__BASE_ADDR_MASK … #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT … #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK … #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT … #define VGT_DMA_INDEX_TYPE__ATC_MASK … #define VGT_DMA_INDEX_TYPE__ATC__SHIFT … #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK … #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT … #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK … #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT … #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK … #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT … #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK … #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT … #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK … #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT … #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK … #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT … #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK … #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT … #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK … #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT … #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK … #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT … #define VGT_DMA_SIZE__NUM_INDICES_MASK … #define VGT_DMA_SIZE__NUM_INDICES__SHIFT … #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK … #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT … #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK … #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT … #define VGT_DRAW_INITIATOR__NOT_EOP_MASK … #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT … #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK … #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT … #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK … #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT … #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK … #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT … #define VGT_ENHANCE__MISC_MASK … #define VGT_ENHANCE__MISC__SHIFT … #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK … #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT … #define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK … #define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT … #define VGT_ES_PER_GS__ES_PER_GS_MASK … #define VGT_ES_PER_GS__ES_PER_GS__SHIFT … #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK … #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT … #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK … #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT … #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK … #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT … #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK … #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT … #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK … #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT … #define VGT_FIFO_DEPTHS__RESERVED_0_MASK … #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT … #define VGT_FIFO_DEPTHS__RESERVED_1_MASK … #define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT … #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK … #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT … #define VGT_GROUP_DECR__DECR_MASK … #define VGT_GROUP_DECR__DECR__SHIFT … #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK … #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT … #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK … #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT … #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK … #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT … #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK … #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT … #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK … #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT … #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK … #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT … #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK … #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT … #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK … #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT … #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK … #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT … #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK … #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT … #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK … #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT … #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK … #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT … #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK … #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT … #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK … #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT … #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK … #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT … #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK … #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT … #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK … #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT … #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK … #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT … #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK … #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT … #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK … #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT … #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK … #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT … #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK … #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT … #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK … #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT … #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK … #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT … #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK … #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT … #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK … #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT … #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK … #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT … #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK … #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT … #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK … #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT … #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK … #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT … #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK … #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT … #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK … #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT … #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK … #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT … #define VGT_GS_INSTANCE_CNT__CNT_MASK … #define VGT_GS_INSTANCE_CNT__CNT__SHIFT … #define VGT_GS_INSTANCE_CNT__ENABLE_MASK … #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT … #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK … #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT … #define VGT_GS_MODE__COMPUTE_MODE_MASK … #define VGT_GS_MODE__COMPUTE_MODE__SHIFT … #define VGT_GS_MODE__CUT_MODE_MASK … #define VGT_GS_MODE__CUT_MODE__SHIFT … #define VGT_GS_MODE__ELEMENT_INFO_EN_MASK … #define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT … #define VGT_GS_MODE__ES_PASSTHRU_MASK … #define VGT_GS_MODE__ES_PASSTHRU__SHIFT … #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK … #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT … #define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK … #define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT … #define VGT_GS_MODE__GS_C_PACK_EN_MASK … #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT … #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK … #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT … #define VGT_GS_MODE__MODE_MASK … #define VGT_GS_MODE__MODE__SHIFT … #define VGT_GS_MODE__ONCHIP_MASK … #define VGT_GS_MODE__ONCHIP__SHIFT … #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK … #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT … #define VGT_GS_MODE__RESERVED_0_MASK … #define VGT_GS_MODE__RESERVED_0__SHIFT … #define VGT_GS_MODE__RESERVED_1_MASK … #define VGT_GS_MODE__RESERVED_1__SHIFT … #define VGT_GS_MODE__RESERVED_2_MASK … #define VGT_GS_MODE__RESERVED_2__SHIFT … #define VGT_GS_MODE__SUPPRESS_CUTS_MASK … #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT … #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK … #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT … #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK … #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT … #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK … #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT … #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK … #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT … #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK … #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT … #define VGT_GS_PER_ES__GS_PER_ES_MASK … #define VGT_GS_PER_ES__GS_PER_ES__SHIFT … #define VGT_GS_PER_VS__GS_PER_VS_MASK … #define VGT_GS_PER_VS__GS_PER_VS__SHIFT … #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK … #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT … #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK … #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT … #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK … #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT … #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK … #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT … #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK … #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT … #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK … #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT … #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK … #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT … #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK … #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT … #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK … #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT … #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK … #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT … #define VGT_HOS_CNTL__TESS_MODE_MASK … #define VGT_HOS_CNTL__TESS_MODE__SHIFT … #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK … #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT … #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK … #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT … #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK … #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT … #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK … #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT … #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK … #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT … #define VGT_IMMED_DATA__DATA_MASK … #define VGT_IMMED_DATA__DATA__SHIFT … #define VGT_INDEX_TYPE__INDEX_TYPE_MASK … #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT … #define VGT_INDX_OFFSET__INDX_OFFSET_MASK … #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT … #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK … #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT … #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK … #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT … #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK … #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT … #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK … #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT … #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK … #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT … #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK … #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT … #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK … #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT … #define VGT_MAX_VTX_INDX__MAX_INDX_MASK … #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT … #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK … #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT … #define VGT_MIN_VTX_INDX__MIN_INDX_MASK … #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT … #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK … #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT … #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK … #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT … #define VGT_NUM_INDICES__NUM_INDICES_MASK … #define VGT_NUM_INDICES__NUM_INDICES__SHIFT … #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK … #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT … #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK … #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT … #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK … #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT … #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK … #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT … #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK … #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT … #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK … #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT … #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT … #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK … #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT … #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK … #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT … #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK … #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT … #define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK … #define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT … #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK … #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … #define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK … #define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK … #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT … #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK … #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT … #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK … #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT … #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK … #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT … #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK … #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT … #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK … #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK … #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT … #define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK … #define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT … #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK … #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT … #define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK … #define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK … #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT … #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK … #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT … #define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK … #define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT … #define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK … #define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT … #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK … #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT … #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK … #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT … #define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK … #define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT … #define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK … #define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT … #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK … #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT … #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK … #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT … #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK … #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT … #define VGT_PRIMITIVEID_RESET__VALUE_MASK … #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT … #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK … #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT … #define VGT_REUSE_OFF__REUSE_OFF_MASK … #define VGT_REUSE_OFF__REUSE_OFF__SHIFT … #define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK … #define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT … #define VGT_SHADER_STAGES_EN__ES_EN_MASK … #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT … #define VGT_SHADER_STAGES_EN__GS_EN_MASK … #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT … #define VGT_SHADER_STAGES_EN__HS_EN_MASK … #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT … #define VGT_SHADER_STAGES_EN__LS_EN_MASK … #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT … #define VGT_SHADER_STAGES_EN__VS_EN_MASK … #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT … #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK … #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT … #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK … #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT … #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK … #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT … #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK … #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT … #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK … #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT … #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK … #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT … #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK … #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT … #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK … #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT … #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK … #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT … #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK … #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT … #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK … #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT … #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK … #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT … #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK … #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT … #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK … #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT … #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK … #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT … #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK … #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT … #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK … #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK … #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT … #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT … #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK … #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT … #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK … #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT … #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK … #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT … #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK … #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT … #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK … #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT … #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK … #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT … #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK … #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT … #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK … #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT … #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK … #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT … #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK … #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT … #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK … #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT … #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK … #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT … #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK … #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT … #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK … #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT … #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK … #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT … #define VGT_TF_MEMORY_BASE__BASE_MASK … #define VGT_TF_MEMORY_BASE__BASE__SHIFT … #define VGT_TF_PARAM__DEPRECATED_MASK … #define VGT_TF_PARAM__DEPRECATED__SHIFT … #define VGT_TF_PARAM__DISABLE_DONUTS_MASK … #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT … #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK … #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT … #define VGT_TF_PARAM__PARTITIONING_MASK … #define VGT_TF_PARAM__PARTITIONING__SHIFT … #define VGT_TF_PARAM__RDREQ_POLICY_MASK … #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT … #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK … #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT … #define VGT_TF_PARAM__TOPOLOGY_MASK … #define VGT_TF_PARAM__TOPOLOGY__SHIFT … #define VGT_TF_PARAM__TYPE_MASK … #define VGT_TF_PARAM__TYPE__SHIFT … #define VGT_TF_RING_SIZE__SIZE_MASK … #define VGT_TF_RING_SIZE__SIZE__SHIFT … #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK … #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT … #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK … #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT … #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK … #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT … #define WD_DEBUG_DATA__DATA_MASK … #define WD_DEBUG_DATA__DATA__SHIFT … #endif
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