/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/pci.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "cikd.h" #include "bif/bif_4_1_d.h" #include "bif/bif_4_1_sh_mask.h" #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" /* * Interrupts * Starting with r6xx, interrupts are handled via a ring buffer. * Ring buffers are areas of GPU accessible memory that the GPU * writes interrupt vectors into and the host reads vectors out of. * There is a rptr (read pointer) that determines where the * host is currently reading, and a wptr (write pointer) * which determines where the GPU has written. When the * pointers are equal, the ring is idle. When the GPU * writes vectors to the ring buffer, it increments the * wptr. When there is an interrupt, the host then starts * fetching commands and processing them until the pointers are * equal again at which point it updates the rptr. */ static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev); /** * cik_ih_enable_interrupts - Enable the interrupt ring buffer * * @adev: amdgpu_device pointer * * Enable the interrupt ring buffer (CIK). */ static void cik_ih_enable_interrupts(struct amdgpu_device *adev) { … } /** * cik_ih_disable_interrupts - Disable the interrupt ring buffer * * @adev: amdgpu_device pointer * * Disable the interrupt ring buffer (CIK). */ static void cik_ih_disable_interrupts(struct amdgpu_device *adev) { … } /** * cik_ih_irq_init - init and enable the interrupt ring * * @adev: amdgpu_device pointer * * Allocate a ring buffer for the interrupt controller, * enable the RLC, disable interrupts, enable the IH * ring buffer and enable it (CIK). * Called at device load and reume. * Returns 0 for success, errors for failure. */ static int cik_ih_irq_init(struct amdgpu_device *adev) { … } /** * cik_ih_irq_disable - disable interrupts * * @adev: amdgpu_device pointer * * Disable interrupts on the hw (CIK). */ static void cik_ih_irq_disable(struct amdgpu_device *adev) { … } /** * cik_ih_get_wptr - get the IH ring buffer wptr * * @adev: amdgpu_device pointer * @ih: IH ring buffer to fetch wptr * * Get the IH ring buffer wptr from either the register * or the writeback memory buffer (CIK). Also check for * ring buffer overflow and deal with it. * Used by cik_irq_process(). * Returns the value of the wptr. */ static u32 cik_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { … } /* CIK IV Ring * Each IV ring entry is 128 bits: * [7:0] - interrupt source id * [31:8] - reserved * [59:32] - interrupt source data * [63:60] - reserved * [71:64] - RINGID * CP: * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0] * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher * - for gfx, hw shader state (0=PS...5=LS, 6=CS) * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes * PIPE_ID - ME0 0=3D * - ME1&2 compute dispatcher (4 pipes each) * SDMA: * INSTANCE_ID [1:0], QUEUE_ID[1:0] * INSTANCE_ID - 0 = sdma0, 1 = sdma1 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1 * [79:72] - VMID * [95:80] - PASID * [127:96] - reserved */ /** * cik_ih_decode_iv - decode an interrupt vector * * @adev: amdgpu_device pointer * * Decodes the interrupt vector at the current rptr * position and also advance the position. */ static void cik_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) { … } /** * cik_ih_set_rptr - set the IH ring buffer rptr * * @adev: amdgpu_device pointer * @ih: IH ring buffer to set wptr * * Set the IH ring buffer rptr. */ static void cik_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { … } static int cik_ih_early_init(void *handle) { … } static int cik_ih_sw_init(void *handle) { … } static int cik_ih_sw_fini(void *handle) { … } static int cik_ih_hw_init(void *handle) { … } static int cik_ih_hw_fini(void *handle) { … } static int cik_ih_suspend(void *handle) { … } static int cik_ih_resume(void *handle) { … } static bool cik_ih_is_idle(void *handle) { … } static int cik_ih_wait_for_idle(void *handle) { … } static int cik_ih_soft_reset(void *handle) { … } static int cik_ih_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int cik_ih_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static const struct amd_ip_funcs cik_ih_ip_funcs = …; static const struct amdgpu_ih_funcs cik_ih_funcs = …; static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev) { … } const struct amdgpu_ip_block_version cik_ih_ip_block = …;
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