linux/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c

/*
 * Copyright 2021 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu_ras.h"
#include "amdgpu.h"
#include "amdgpu_mca.h"

#include "umc/umc_6_7_0_offset.h"
#include "umc/umc_6_7_0_sh_mask.h"

static bool amdgpu_mca_is_deferred_error(struct amdgpu_device *adev,
					uint64_t mc_status)
{ … }

void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
					      uint64_t mc_status_addr,
					      unsigned long *error_count)
{ … }

void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
						uint64_t mc_status_addr,
						unsigned long *error_count)
{ … }

void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
				  uint64_t mc_status_addr)
{ … }

void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
				      uint64_t mc_status_addr,
				      void *ras_error_status)
{ … }

int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev)
{ … }

int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev)
{ … }

int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev)
{ … }

static void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set)
{ … }

static int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry)
{ … }

static int amdgpu_mca_bank_set_merge(struct mca_bank_set *mca_set, struct mca_bank_set *new)
{ … }

static void amdgpu_mca_bank_set_remove_node(struct mca_bank_set *mca_set, struct mca_bank_node *node)
{ … }

static void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set)
{ … }

void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs)
{ … }

int amdgpu_mca_init(struct amdgpu_device *adev)
{ … }

void amdgpu_mca_fini(struct amdgpu_device *adev)
{ … }

int amdgpu_mca_reset(struct amdgpu_device *adev)
{ … }

int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
{ … }

static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry,
					 struct ras_query_context *qctx)
{ … }

static int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
{ … }

static int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
					int idx, struct mca_bank_entry *entry)
{ … }

static bool amdgpu_mca_bank_should_update(struct amdgpu_device *adev, enum amdgpu_mca_error_type type)
{ … }

static int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set,
				      struct ras_query_context *qctx)
{ … }

static int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
						enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
{ … }

static int amdgpu_mca_dispatch_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
				       struct mca_bank_set *mca_set, struct ras_err_data *err_data)
{ … }

static int amdgpu_mca_add_mca_set_to_cache(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, struct mca_bank_set *new)
{ … }

int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
				 struct ras_err_data *err_data, struct ras_query_context *qctx)
{ … }

#if defined(CONFIG_DEBUG_FS)
static int amdgpu_mca_smu_debug_mode_set(void *data, u64 val)
{ … }

static void mca_dump_entry(struct seq_file *m, struct mca_bank_entry *entry)
{ … }

static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type)
{ … }

static int mca_dump_ce_show(struct seq_file *m, void *unused)
{ … }

static int mca_dump_ce_open(struct inode *inode, struct file *file)
{ … }

static const struct file_operations mca_ce_dump_debug_fops = …;

static int mca_dump_ue_show(struct seq_file *m, void *unused)
{ … }

static int mca_dump_ue_open(struct inode *inode, struct file *file)
{ … }

static const struct file_operations mca_ue_dump_debug_fops = …;

DEFINE_DEBUGFS_ATTRIBUTE(…);
#endif

void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)
{ … }