/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _nbio_6_1_DEFAULT_HEADER #define _nbio_6_1_DEFAULT_HEADER // addressBlock: nbio_pcie_pswuscfg0_cfgdecp #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT … #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT … #define cfgPSWUSCFG0_COMMAND_DEFAULT … #define cfgPSWUSCFG0_STATUS_DEFAULT … #define cfgPSWUSCFG0_REVISION_ID_DEFAULT … #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT … #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT … #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT … #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT … #define cfgPSWUSCFG0_LATENCY_DEFAULT … #define cfgPSWUSCFG0_HEADER_DEFAULT … #define cfgPSWUSCFG0_BIST_DEFAULT … #define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_DEFAULT … #define cfgPSWUSCFG0_IO_BASE_LIMIT_DEFAULT … #define cfgPSWUSCFG0_SECONDARY_STATUS_DEFAULT … #define cfgPSWUSCFG0_MEM_BASE_LIMIT_DEFAULT … #define cfgPSWUSCFG0_PREF_BASE_LIMIT_DEFAULT … #define cfgPSWUSCFG0_PREF_BASE_UPPER_DEFAULT … #define cfgPSWUSCFG0_PREF_LIMIT_UPPER_DEFAULT … #define cfgPSWUSCFG0_IO_BASE_LIMIT_HI_DEFAULT … #define cfgPSWUSCFG0_CAP_PTR_DEFAULT … #define cfgPSWUSCFG0_INTERRUPT_LINE_DEFAULT … #define cfgPSWUSCFG0_INTERRUPT_PIN_DEFAULT … #define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL_DEFAULT … #define cfgEXT_BRIDGE_CNTL_DEFAULT … #define cfgPSWUSCFG0_VENDOR_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_ADAPTER_ID_W_DEFAULT … #define cfgPSWUSCFG0_PMI_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PMI_CAP_DEFAULT … #define cfgPSWUSCFG0_PMI_STATUS_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_CAP_DEFAULT … #define cfgPSWUSCFG0_DEVICE_CAP_DEFAULT … #define cfgPSWUSCFG0_DEVICE_CNTL_DEFAULT … #define cfgPSWUSCFG0_DEVICE_STATUS_DEFAULT … #define cfgPSWUSCFG0_LINK_CAP_DEFAULT … #define cfgPSWUSCFG0_LINK_CNTL_DEFAULT … #define cfgPSWUSCFG0_LINK_STATUS_DEFAULT … #define cfgPSWUSCFG0_DEVICE_CAP2_DEFAULT … #define cfgPSWUSCFG0_DEVICE_CNTL2_DEFAULT … #define cfgPSWUSCFG0_DEVICE_STATUS2_DEFAULT … #define cfgPSWUSCFG0_LINK_CAP2_DEFAULT … #define cfgPSWUSCFG0_LINK_CNTL2_DEFAULT … #define cfgPSWUSCFG0_LINK_STATUS2_DEFAULT … #define cfgPSWUSCFG0_MSI_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_MSI_MSG_CNTL_DEFAULT … #define cfgPSWUSCFG0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgPSWUSCFG0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgPSWUSCFG0_MSI_MSG_DATA_DEFAULT … #define cfgPSWUSCFG0_MSI_MSG_DATA_64_DEFAULT … #define cfgPSWUSCFG0_SSID_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_SSID_CAP_DEFAULT … #define cfgMSI_MAP_CAP_LIST_DEFAULT … #define cfgMSI_MAP_CAP_DEFAULT … #define cfgMSI_MAP_ADDR_LO_DEFAULT … #define cfgMSI_MAP_ADDR_HI_DEFAULT … #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1_DEFAULT … #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2_DEFAULT … #define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS_DEFAULT … #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP_DEFAULT … #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS_DEFAULT … #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP_DEFAULT … #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS_DEFAULT … #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT … #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT … #define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_HDR_LOG0_DEFAULT … #define cfgPSWUSCFG0_PCIE_HDR_LOG1_DEFAULT … #define cfgPSWUSCFG0_PCIE_HDR_LOG2_DEFAULT … #define cfgPSWUSCFG0_PCIE_HDR_LOG3_DEFAULT … #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_LINK_CNTL3_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_ACS_CAP_DEFAULT … #define cfgPSWUSCFG0_PCIE_ACS_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_CAP_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_CNTL_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_ADDR0_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_ADDR1_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_RCV0_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_RCV1_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT … #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT … #define cfgPCIE_MC_OVERLAY_BAR0_DEFAULT … #define cfgPCIE_MC_OVERLAY_BAR1_DEFAULT … #define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_LTR_CAP_DEFAULT … #define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgPSWUSCFG0_PCIE_ARI_CAP_DEFAULT … #define cfgPSWUSCFG0_PCIE_ARI_CNTL_DEFAULT … #define cfgPCIE_L1_PM_SUB_CAP_LIST_DEFAULT … #define cfgPCIE_L1_PM_SUB_CAP_DEFAULT … #define cfgPCIE_L1_PM_SUB_CNTL_DEFAULT … #define cfgPCIE_L1_PM_SUB_CNTL2_DEFAULT … #define cfgPCIE_ESM_CAP_LIST_DEFAULT … #define cfgPCIE_ESM_HEADER_1_DEFAULT … #define cfgPCIE_ESM_HEADER_2_DEFAULT … #define cfgPCIE_ESM_STATUS_DEFAULT … #define cfgPCIE_ESM_CTRL_DEFAULT … #define cfgPCIE_ESM_CAP_1_DEFAULT … #define cfgPCIE_ESM_CAP_2_DEFAULT … #define cfgPCIE_ESM_CAP_3_DEFAULT … #define cfgPCIE_ESM_CAP_4_DEFAULT … #define cfgPCIE_ESM_CAP_5_DEFAULT … #define cfgPCIE_ESM_CAP_6_DEFAULT … #define cfgPCIE_ESM_CAP_7_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT … #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP_DEFAULT … #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767] #define mmMM_INDEX_DEFAULT … #define mmMM_DATA_DEFAULT … #define mmMM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767] #define mmSYSHUB_INDEX_OVLP_DEFAULT … #define mmSYSHUB_DATA_OVLP_DEFAULT … #define mmPCIE_INDEX_DEFAULT … #define mmPCIE_DATA_DEFAULT … #define mmPCIE_INDEX2_DEFAULT … #define mmPCIE_DATA2_DEFAULT … #define mmSBIOS_SCRATCH_0_DEFAULT … #define mmSBIOS_SCRATCH_1_DEFAULT … #define mmSBIOS_SCRATCH_2_DEFAULT … #define mmSBIOS_SCRATCH_3_DEFAULT … #define mmBIOS_SCRATCH_0_DEFAULT … #define mmBIOS_SCRATCH_1_DEFAULT … #define mmBIOS_SCRATCH_2_DEFAULT … #define mmBIOS_SCRATCH_3_DEFAULT … #define mmBIOS_SCRATCH_4_DEFAULT … #define mmBIOS_SCRATCH_5_DEFAULT … #define mmBIOS_SCRATCH_6_DEFAULT … #define mmBIOS_SCRATCH_7_DEFAULT … #define mmBIOS_SCRATCH_8_DEFAULT … #define mmBIOS_SCRATCH_9_DEFAULT … #define mmBIOS_SCRATCH_10_DEFAULT … #define mmBIOS_SCRATCH_11_DEFAULT … #define mmBIOS_SCRATCH_12_DEFAULT … #define mmBIOS_SCRATCH_13_DEFAULT … #define mmBIOS_SCRATCH_14_DEFAULT … #define mmBIOS_SCRATCH_15_DEFAULT … #define mmBIF_RLC_INTR_CNTL_DEFAULT … #define mmBIF_VCE_INTR_CNTL_DEFAULT … #define mmBIF_UVD_INTR_CNTL_DEFAULT … #define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT … #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT … #define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT … #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT … #define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT … #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT … #define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT … #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT … #define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT … #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT … #define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT … #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT … #define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT … #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT … #define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT … #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT … #define mmGFX_MMIOREG_CAM_CNTL_DEFAULT … #define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT … #define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT … #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT … // addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39] #define mmSYSHUB_INDEX_DEFAULT … #define mmSYSHUB_DATA_DEFAULT … // addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975] #define mmRCC_DEV0_EPF0_STRAP0_DEFAULT … // addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975] #define mmEP_PCIE_SCRATCH_DEFAULT … #define mmEP_PCIE_CNTL_DEFAULT … #define mmEP_PCIE_INT_CNTL_DEFAULT … #define mmEP_PCIE_INT_STATUS_DEFAULT … #define mmEP_PCIE_RX_CNTL2_DEFAULT … #define mmEP_PCIE_BUS_CNTL_DEFAULT … #define mmEP_PCIE_CFG_CNTL_DEFAULT … #define mmEP_PCIE_TX_LTR_CNTL_DEFAULT … #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT … #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT … #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT … #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT … #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT … #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT … #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT … #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT … #define mmEP_PCIE_F0_DPA_CAP_DEFAULT … #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT … #define mmEP_PCIE_F0_DPA_CNTL_DEFAULT … #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT … #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT … #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT … #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT … #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT … #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT … #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT … #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT … #define mmEP_PCIE_PME_CONTROL_DEFAULT … #define mmEP_PCIEP_RESERVED_DEFAULT … #define mmEP_PCIE_TX_CNTL_DEFAULT … #define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT … #define mmEP_PCIE_ERR_CNTL_DEFAULT … #define mmEP_PCIE_RX_CNTL_DEFAULT … #define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT … // addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975] #define mmDN_PCIE_RESERVED_DEFAULT … #define mmDN_PCIE_SCRATCH_DEFAULT … #define mmDN_PCIE_CNTL_DEFAULT … #define mmDN_PCIE_CONFIG_CNTL_DEFAULT … #define mmDN_PCIE_RX_CNTL2_DEFAULT … #define mmDN_PCIE_BUS_CNTL_DEFAULT … #define mmDN_PCIE_CFG_CNTL_DEFAULT … // addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975] #define mmPCIE_ERR_CNTL_DEFAULT … #define mmPCIE_RX_CNTL_DEFAULT … #define mmPCIE_LC_SPEED_CNTL_DEFAULT … #define mmPCIE_LC_CNTL2_DEFAULT … #define mmPCIEP_STRAP_MISC_DEFAULT … #define mmLTR_MSG_INFO_FROM_EP_DEFAULT … // addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975] #define mmRCC_PF_0_0_RCC_ERR_LOG_DEFAULT … #define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN_DEFAULT … #define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE_DEFAULT … #define mmRCC_PF_0_0_RCC_CONFIG_RESERVED_DEFAULT … #define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT … // addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975] #define mmRCC_ERR_INT_CNTL_DEFAULT … #define mmRCC_BACO_CNTL_MISC_DEFAULT … #define mmRCC_RESET_EN_DEFAULT … #define mmRCC_VDM_SUPPORT_DEFAULT … #define mmRCC_PEER_REG_RANGE0_DEFAULT … #define mmRCC_PEER_REG_RANGE1_DEFAULT … #define mmRCC_BUS_CNTL_DEFAULT … #define mmRCC_CONFIG_CNTL_DEFAULT … #define mmRCC_CONFIG_F0_BASE_DEFAULT … #define mmRCC_CONFIG_APER_SIZE_DEFAULT … #define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT … #define mmRCC_XDMA_LO_DEFAULT … #define mmRCC_XDMA_HI_DEFAULT … #define mmRCC_FEATURES_CONTROL_MISC_DEFAULT … #define mmRCC_BUSNUM_CNTL1_DEFAULT … #define mmRCC_BUSNUM_LIST0_DEFAULT … #define mmRCC_BUSNUM_LIST1_DEFAULT … #define mmRCC_BUSNUM_CNTL2_DEFAULT … #define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT … #define mmRCC_HOST_BUSNUM_DEFAULT … #define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT … #define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT … #define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT … #define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT … #define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT … #define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT … #define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT … #define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT … #define mmRCC_CMN_LINK_CNTL_DEFAULT … #define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT … #define mmRCC_LTR_LSWITCH_CNTL_DEFAULT … #define mmRCC_MH_ARB_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975] #define mmBIF_MM_INDACCESS_CNTL_DEFAULT … #define mmBUS_CNTL_DEFAULT … #define mmBIF_SCRATCH0_DEFAULT … #define mmBIF_SCRATCH1_DEFAULT … #define mmBX_RESET_EN_DEFAULT … #define mmMM_CFGREGS_CNTL_DEFAULT … #define mmBX_RESET_CNTL_DEFAULT … #define mmINTERRUPT_CNTL_DEFAULT … #define mmINTERRUPT_CNTL2_DEFAULT … #define mmCLKREQB_PAD_CNTL_DEFAULT … #define mmBIF_FEATURES_CONTROL_MISC_DEFAULT … #define mmBIF_DOORBELL_CNTL_DEFAULT … #define mmBIF_DOORBELL_INT_CNTL_DEFAULT … #define mmBIF_FB_EN_DEFAULT … #define mmBIF_BUSY_DELAY_CNTR_DEFAULT … #define mmBIF_MST_TRANS_PENDING_VF_DEFAULT … #define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT … #define mmBACO_CNTL_DEFAULT … #define mmBIF_BACO_EXIT_TIME0_DEFAULT … #define mmBIF_BACO_EXIT_TIMER1_DEFAULT … #define mmBIF_BACO_EXIT_TIMER2_DEFAULT … #define mmBIF_BACO_EXIT_TIMER3_DEFAULT … #define mmBIF_BACO_EXIT_TIMER4_DEFAULT … #define mmMEM_TYPE_CNTL_DEFAULT … #define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT … #define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT … #define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT … #define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT … #define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT … #define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT … #define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT … #define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT … #define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT … #define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT … #define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT … #define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT … #define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT … #define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT … #define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT … #define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT … #define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT … #define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT … #define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT … #define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT … #define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT … #define mmBIF_VDDGFX_FB_CMP_DEFAULT … #define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT … #define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT … #define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT … #define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT … #define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT … #define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT … #define mmBIF_RB_CNTL_DEFAULT … #define mmBIF_RB_BASE_DEFAULT … #define mmBIF_RB_RPTR_DEFAULT … #define mmBIF_RB_WPTR_DEFAULT … #define mmBIF_RB_WPTR_ADDR_HI_DEFAULT … #define mmBIF_RB_WPTR_ADDR_LO_DEFAULT … #define mmMAILBOX_INDEX_DEFAULT … #define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT … #define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT … #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT … #define mmBIF_PERSTB_PAD_CNTL_DEFAULT … #define mmBIF_PX_EN_PAD_CNTL_DEFAULT … #define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT … #define mmBIF_CLKREQB_PAD_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1 #define mmBIF_BX_PF0_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_PF0_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_PF0_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_PF0_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487] #define mmNGDC_SDP_PORT_CTRL_DEFAULT … #define mmSHUB_REGS_IF_CTL_DEFAULT … #define mmNGDC_RESERVED_0_DEFAULT … #define mmNGDC_RESERVED_1_DEFAULT … #define mmNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT … #define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT … #define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT … #define mmBIF_IH_DOORBELL_RANGE_DEFAULT … #define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT … #define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT … #define mmS2A_MISC_CNTL_DEFAULT … // addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2 #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA_DEFAULT … #define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL_DEFAULT … #define mmRCC_PF_0_GFXMSIX_PBA_DEFAULT … // addressBlock: nbio_nbif_gdc_GDCDEC #define smnGDC1_NGDC_SDP_PORT_CTRL_DEFAULT … #define smnGDC1_SHUB_REGS_IF_CTL_DEFAULT … #define smnGDC1_NGDC_RESERVED_0_DEFAULT … #define smnGDC1_NGDC_RESERVED_1_DEFAULT … #define smnGDC1_NGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT … #define smnGDC1_BIF_SDMA0_DOORBELL_RANGE_DEFAULT … #define smnGDC1_BIF_SDMA1_DOORBELL_RANGE_DEFAULT … #define smnGDC1_BIF_IH_DOORBELL_RANGE_DEFAULT … #define smnGDC1_BIF_MMSCH0_DOORBELL_RANGE_DEFAULT … #define smnGDC1_BIF_DOORBELL_FENCE_CNTL_DEFAULT … #define smnGDC1_S2A_MISC_CNTL_DEFAULT … // addressBlock: nbio_nbif_syshub_mmreg_direct_syshubdirect #define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD_DEFAULT … #define smnSYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT … // addressBlock: nbio_nbif_nbif_sion_SIONDEC #define smnSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL0_Req_BurstTarget_REG0_DEFAULT … #define smnSION_CL0_Req_BurstTarget_REG1_DEFAULT … #define smnSION_CL0_Req_TimeSlot_REG0_DEFAULT … #define smnSION_CL0_Req_TimeSlot_REG1_DEFAULT … #define smnSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL1_Req_BurstTarget_REG0_DEFAULT … #define smnSION_CL1_Req_BurstTarget_REG1_DEFAULT … #define smnSION_CL1_Req_TimeSlot_REG0_DEFAULT … #define smnSION_CL1_Req_TimeSlot_REG1_DEFAULT … #define smnSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL2_Req_BurstTarget_REG0_DEFAULT … #define smnSION_CL2_Req_BurstTarget_REG1_DEFAULT … #define smnSION_CL2_Req_TimeSlot_REG0_DEFAULT … #define smnSION_CL2_Req_TimeSlot_REG1_DEFAULT … #define smnSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL3_Req_BurstTarget_REG0_DEFAULT … #define smnSION_CL3_Req_BurstTarget_REG1_DEFAULT … #define smnSION_CL3_Req_TimeSlot_REG0_DEFAULT … #define smnSION_CL3_Req_TimeSlot_REG1_DEFAULT … #define smnSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL4_Req_BurstTarget_REG0_DEFAULT … #define smnSION_CL4_Req_BurstTarget_REG1_DEFAULT … #define smnSION_CL4_Req_TimeSlot_REG0_DEFAULT … #define smnSION_CL4_Req_TimeSlot_REG1_DEFAULT … #define smnSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT … #define smnSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT … #define smnSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT … #define smnSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT … #define smnSION_CL5_Req_BurstTarget_REG0_DEFAULT … #define smnSION_CL5_Req_BurstTarget_REG1_DEFAULT … #define smnSION_CL5_Req_TimeSlot_REG0_DEFAULT … #define smnSION_CL5_Req_TimeSlot_REG1_DEFAULT … #define smnSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT … #define smnSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT … #define smnSION_CNTL_REG0_DEFAULT … #define smnSION_CNTL_REG1_DEFAULT … // addressBlock: nbio_nbif_gdc_rst_GDCRST_DEC #define smnSHUB_PF_FLR_RST_DEFAULT … #define smnSHUB_GFX_DRV_VPU_RST_DEFAULT … #define smnSHUB_LINK_RESET_DEFAULT … #define smnSHUB_PF0_VF_FLR_RST_DEFAULT … #define smnSHUB_HARD_RST_CTRL_DEFAULT … #define smnSHUB_SOFT_RST_CTRL_DEFAULT … #define smnSHUB_SDP_PORT_RST_DEFAULT … #define smnSHUB_RST_MISC_TRL_DEFAULT … // addressBlock: nbio_nbif_gdc_ras_gdc_ras_regblk #define smnGDC_RAS_LEAF0_CTRL_DEFAULT … #define smnGDC_RAS_LEAF1_CTRL_DEFAULT … #define smnGDC_RAS_LEAF2_CTRL_DEFAULT … #define smnGDC_RAS_LEAF3_CTRL_DEFAULT … #define smnGDC_RAS_LEAF4_CTRL_DEFAULT … #define smnGDC_RAS_LEAF5_CTRL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp #define smnBIF_CFG_DEV0_SWDS1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PMI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SLOT_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SLOT_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SLOT_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_SSID_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC #define smnBIF_BX_PF3_MM_INDEX_DEFAULT … #define smnBIF_BX_PF3_MM_DATA_DEFAULT … #define smnBIF_BX_PF3_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_SYSDEC #define smnBIF_BX_PF1_SYSHUB_INDEX_OVLP_DEFAULT … #define smnBIF_BX_PF1_SYSHUB_DATA_OVLP_DEFAULT … #define smnBIF_BX_PF1_PCIE_INDEX_DEFAULT … #define smnBIF_BX_PF1_PCIE_DATA_DEFAULT … #define smnBIF_BX_PF1_PCIE_INDEX2_DEFAULT … #define smnBIF_BX_PF1_PCIE_DATA2_DEFAULT … #define smnBIF_BX_PF1_SBIOS_SCRATCH_0_DEFAULT … #define smnBIF_BX_PF1_SBIOS_SCRATCH_1_DEFAULT … #define smnBIF_BX_PF1_SBIOS_SCRATCH_2_DEFAULT … #define smnBIF_BX_PF1_SBIOS_SCRATCH_3_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_0_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_1_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_2_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_3_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_4_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_5_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_6_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_7_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_8_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_9_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_10_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_11_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_12_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_13_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_14_DEFAULT … #define smnBIF_BX_PF1_BIOS_SCRATCH_15_DEFAULT … #define smnBIF_BX_PF1_BIF_RLC_INTR_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_VCE_INTR_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_UVD_INTR_CNTL_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_CNTL_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL_DEFAULT … #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT … // addressBlock: nbio_nbif_rcc_strap_BIFDEC1 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_DEFAULT … // addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1 #define smnRCC_PF_0_1_RCC_ERR_LOG_DEFAULT … #define smnRCC_PF_0_1_RCC_DOORBELL_APER_EN_DEFAULT … #define smnRCC_PF_0_1_RCC_CONFIG_MEMSIZE_DEFAULT … #define smnRCC_PF_0_1_RCC_CONFIG_RESERVED_DEFAULT … #define smnRCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1 #define smnBIF_BX_PF1_BIF_MM_INDACCESS_CNTL_DEFAULT … #define smnBIF_BX_PF1_BUS_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_SCRATCH0_DEFAULT … #define smnBIF_BX_PF1_BIF_SCRATCH1_DEFAULT … #define smnBIF_BX_PF1_BX_RESET_EN_DEFAULT … #define smnBIF_BX_PF1_MM_CFGREGS_CNTL_DEFAULT … #define smnBIF_BX_PF1_BX_RESET_CNTL_DEFAULT … #define smnBIF_BX_PF1_INTERRUPT_CNTL_DEFAULT … #define smnBIF_BX_PF1_INTERRUPT_CNTL2_DEFAULT … #define smnBIF_BX_PF1_CLKREQB_PAD_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_FEATURES_CONTROL_MISC_DEFAULT … #define smnBIF_BX_PF1_BIF_DOORBELL_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_DOORBELL_INT_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_FB_EN_DEFAULT … #define smnBIF_BX_PF1_BIF_BUSY_DELAY_CNTR_DEFAULT … #define smnBIF_BX_PF1_BIF_MST_TRANS_PENDING_VF_DEFAULT … #define smnBIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF_DEFAULT … #define smnBIF_BX_PF1_BACO_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIME0_DEFAULT … #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER1_DEFAULT … #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER2_DEFAULT … #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER3_DEFAULT … #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER4_DEFAULT … #define smnBIF_BX_PF1_MEM_TYPE_CNTL_DEFAULT … #define smnBIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_VDDGFX_FB_CMP_DEFAULT … #define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER_DEFAULT … #define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER_DEFAULT … #define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER_DEFAULT … #define smnBIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL_DEFAULT … #define smnBIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_RB_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_RB_BASE_DEFAULT … #define smnBIF_BX_PF1_BIF_RB_RPTR_DEFAULT … #define smnBIF_BX_PF1_BIF_RB_WPTR_DEFAULT … #define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_HI_DEFAULT … #define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_LO_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_INDEX_DEFAULT … #define smnBIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE_DEFAULT … #define smnBIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE_DEFAULT … #define smnBIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT … #define smnBIF_BX_PF1_BIF_PERSTB_PAD_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_PX_EN_PAD_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_CLKREQB_PAD_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1 #define smnBIF_BX_PF1_BIF_BME_STATUS_DEFAULT … #define smnBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_DEFAULT … #define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define smnBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define smnBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define smnBIF_BX_PF1_GPU_HDP_FLUSH_REQ_DEFAULT … #define smnBIF_BX_PF1_GPU_HDP_FLUSH_DONE_DEFAULT … #define smnBIF_BX_PF1_BIF_TRANS_PENDING_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_CONTROL_DEFAULT … #define smnBIF_BX_PF1_MAILBOX_INT_CNTL_DEFAULT … #define smnBIF_BX_PF1_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_rcc_shadow_reg_shadowdec #define smnSHADOW_COMMAND_DEFAULT … #define smnSHADOW_BASE_ADDR_1_DEFAULT … #define smnSHADOW_BASE_ADDR_2_DEFAULT … #define smnSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT … #define smnSHADOW_IO_BASE_LIMIT_DEFAULT … #define smnSHADOW_MEM_BASE_LIMIT_DEFAULT … #define smnSHADOW_PREF_BASE_LIMIT_DEFAULT … #define smnSHADOW_PREF_BASE_UPPER_DEFAULT … #define smnSHADOW_PREF_LIMIT_UPPER_DEFAULT … #define smnSHADOW_IO_BASE_LIMIT_HI_DEFAULT … #define smnSHADOW_IRQ_BRIDGE_CNTL_DEFAULT … #define smnSUC_INDEX_DEFAULT … #define smnSUC_DATA_DEFAULT … // addressBlock: nbio_nbif_rcc_ep_dev0_RCCPORTDEC #define smnRCC_EP_DEV0_1_EP_PCIE_SCRATCH_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT … #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT … #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT … #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT … #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT … #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT … #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT … #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIEP_RESERVED_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_DEFAULT … #define smnRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_DEFAULT … // addressBlock: nbio_nbif_rcc_dwn_dev0_RCCPORTDEC #define smnRCC_DWN_DEV0_1_DN_PCIE_RESERVED_DEFAULT … #define smnRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_DEFAULT … #define smnRCC_DWN_DEV0_1_DN_PCIE_CNTL_DEFAULT … #define smnRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_DEFAULT … #define smnRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_DEFAULT … #define smnRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_DEFAULT … #define smnRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_DEFAULT … // addressBlock: nbio_nbif_rcc_dwnp_dev0_RCCPORTDEC #define smnRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_DEFAULT … #define smnRCC_DWNP_DEV0_1_PCIE_RX_CNTL_DEFAULT … #define smnRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_DEFAULT … #define smnRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_DEFAULT … #define smnRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_DEFAULT … #define smnRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_DEFAULT … // addressBlock: nbio_nbif_rcc_strap_rcc_strap_internal #define smnRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_DEFAULT … // addressBlock: nbio_nbif_bif_bx_pf_SUMDEC #define smnSUM_INDEX_DEFAULT … #define smnSUM_DATA_DEFAULT … // addressBlock: nbio_nbif_bif_misc_bif_misc_regblk #define smnMISC_SCRATCH_DEFAULT … #define smnINTR_LINE_POLARITY_DEFAULT … #define smnINTR_LINE_ENABLE_DEFAULT … #define smnOUTSTANDING_VC_ALLOC_DEFAULT … #define smnBIFC_MISC_CTRL0_DEFAULT … #define smnBIFC_MISC_CTRL1_DEFAULT … #define smnBIFC_BME_ERR_LOG_DEFAULT … #define smnBIFC_RCCBIH_BME_ERR_LOG_DEFAULT … #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT … #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT … #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT … #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT … #define smnNBIF_VWIRE_CTRL_DEFAULT … #define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT … #define smnNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT … #define smnNBIF_SMN_VWR_VCHG_TRIG_DEFAULT … #define smnNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT … #define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT … #define smnNBIF_MGCG_CTRL_LCLK_DEFAULT … #define smnNBIF_DS_CTRL_LCLK_DEFAULT … #define smnSMN_MST_CNTL0_DEFAULT … #define smnSMN_MST_EP_CNTL1_DEFAULT … #define smnSMN_MST_EP_CNTL2_DEFAULT … #define smnNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT … #define smnNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT … #define smnNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT … #define smnNBIF_SDP_VWR_VCHG_TRIG_DEFAULT … #define smnBME_DUMMY_CNTL_0_DEFAULT … #define smnBIFC_THT_CNTL_DEFAULT … #define smnBIFC_HSTARB_CNTL_DEFAULT … #define smnBIFC_GSI_CNTL_DEFAULT … #define smnBIFC_PCIEFUNC_CNTL_DEFAULT … #define smnBIFC_SDP_CNTL_0_DEFAULT … #define smnBIFC_SDP_CNTL_1_DEFAULT … #define smnBIFC_PERF_CNTL_0_DEFAULT … #define smnBIFC_PERF_CNTL_1_DEFAULT … #define smnBIFC_PERF_CNT_MMIO_RD_DEFAULT … #define smnBIFC_PERF_CNT_MMIO_WR_DEFAULT … #define smnBIFC_PERF_CNT_DMA_RD_DEFAULT … #define smnBIFC_PERF_CNT_DMA_WR_DEFAULT … #define smnNBIF_REGIF_ERRSET_CTRL_DEFAULT … #define smnSMN_MST_EP_CNTL3_DEFAULT … #define smnSMN_MST_EP_CNTL4_DEFAULT … #define smnSMN_MST_CNTL1_DEFAULT … #define smnSMN_MST_EP_CNTL5_DEFAULT … #define smnBIF_SELFRING_BUFFER_VID_DEFAULT … #define smnBIF_SELFRING_VECTOR_CNTL_DEFAULT … #define smnBIF_GMI_WRR_WEIGHT_DEFAULT … // addressBlock: nbio_nbif_rcc_pfc_amdgfx_RCCPFCDEC #define smnRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_DEFAULT … #define smnRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_DEFAULT … #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_DEFAULT … #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_DEFAULT … #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_DEFAULT … #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_DEFAULT … #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_DEFAULT … #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_DEFAULT … #define smnRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_DEFAULT … // addressBlock: nbio_nbif_rcc_pfc_amdgfxaz_RCCPFCDEC #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT … #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT … #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT … #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT … #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT … #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT … #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT … #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT … #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_rst_bif_rst_regblk #define smnHARD_RST_CTRL_DEFAULT … #define smnRSMU_SOFT_RST_CTRL_DEFAULT … #define smnSELF_SOFT_RST_DEFAULT … #define smnBIF_GFX_DRV_VPU_RST_DEFAULT … #define smnBIF_RST_MISC_CTRL_DEFAULT … #define smnBIF_RST_MISC_CTRL2_DEFAULT … #define smnBIF_RST_MISC_CTRL3_DEFAULT … #define smnBIF_RST_GFXVF_FLR_IDLE_DEFAULT … #define smnDEV0_PF0_FLR_RST_CTRL_DEFAULT … #define smnDEV0_PF1_FLR_RST_CTRL_DEFAULT … #define smnDEV0_PF2_FLR_RST_CTRL_DEFAULT … #define smnDEV0_PF3_FLR_RST_CTRL_DEFAULT … #define smnDEV0_PF4_FLR_RST_CTRL_DEFAULT … #define smnDEV0_PF5_FLR_RST_CTRL_DEFAULT … #define smnDEV0_PF6_FLR_RST_CTRL_DEFAULT … #define smnDEV0_PF7_FLR_RST_CTRL_DEFAULT … #define smnBIF_INST_RESET_INTR_STS_DEFAULT … #define smnBIF_PF_FLR_INTR_STS_DEFAULT … #define smnBIF_D3HOTD0_INTR_STS_DEFAULT … #define smnBIF_POWER_INTR_STS_DEFAULT … #define smnBIF_PF_DSTATE_INTR_STS_DEFAULT … #define smnBIF_PF0_VF_FLR_INTR_STS_DEFAULT … #define smnBIF_INST_RESET_INTR_MASK_DEFAULT … #define smnBIF_PF_FLR_INTR_MASK_DEFAULT … #define smnBIF_D3HOTD0_INTR_MASK_DEFAULT … #define smnBIF_POWER_INTR_MASK_DEFAULT … #define smnBIF_PF_DSTATE_INTR_MASK_DEFAULT … #define smnBIF_PF0_VF_FLR_INTR_MASK_DEFAULT … #define smnBIF_PF_FLR_RST_DEFAULT … #define smnBIF_PF0_VF_FLR_RST_DEFAULT … #define smnBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT … #define smnBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT … #define smnBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT … #define smnBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT … #define smnBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT … #define smnBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT … #define smnBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT … #define smnBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT … #define smnDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT … #define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT … #define smnDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT … #define smnDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT … #define smnDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT … #define smnDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT … #define smnDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT … #define smnDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT … #define smnBIF_PORT0_DSTATE_VALUE_DEFAULT … // addressBlock: nbio_nbif_bif_ras_bif_ras_regblk #define smnBIF_RAS_LEAF0_CTRL_DEFAULT … #define smnBIF_RAS_LEAF1_CTRL_DEFAULT … #define smnBIF_RAS_LEAF2_CTRL_DEFAULT … #define smnBIF_RAS_MISC_CTRL_DEFAULT … #define smnBIF_IOHUB_RAS_IH_CNTL_DEFAULT … #define smnBIF_RAS_VWR_FROM_IOHUB_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MIN_GRANT_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MAX_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PMI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp #define smnBIF_CFG_DEV0_EPF1_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MIN_GRANT_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT … #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp #define smnBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_COMMAND_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_LATENCY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_HEADER_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_BIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP_DEFAULT … #define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL_DEFAULT … // addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXTDEC #define smnPCIEMSIX_VECT0_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT0_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT0_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT0_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT1_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT1_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT1_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT1_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT2_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT2_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT2_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT2_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT3_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT3_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT3_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT3_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT4_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT4_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT4_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT4_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT5_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT5_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT5_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT5_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT6_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT6_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT6_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT6_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT7_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT7_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT7_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT7_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT8_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT8_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT8_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT8_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT9_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT9_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT9_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT9_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT10_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT10_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT10_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT10_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT11_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT11_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT11_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT11_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT12_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT12_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT12_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT12_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT13_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT13_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT13_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT13_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT14_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT14_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT14_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT14_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT15_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT15_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT15_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT15_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT16_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT16_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT16_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT16_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT17_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT17_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT17_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT17_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT18_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT18_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT18_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT18_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT19_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT19_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT19_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT19_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT20_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT20_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT20_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT20_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT21_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT21_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT21_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT21_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT22_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT22_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT22_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT22_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT23_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT23_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT23_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT23_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT24_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT24_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT24_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT24_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT25_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT25_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT25_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT25_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT26_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT26_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT26_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT26_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT27_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT27_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT27_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT27_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT28_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT28_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT28_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT28_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT29_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT29_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT29_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT29_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT30_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT30_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT30_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT30_CONTROL_DEFAULT … #define smnPCIEMSIX_VECT31_ADDR_LO_DEFAULT … #define smnPCIEMSIX_VECT31_ADDR_HI_DEFAULT … #define smnPCIEMSIX_VECT31_MSG_DATA_DEFAULT … #define smnPCIEMSIX_VECT31_CONTROL_DEFAULT … // addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXPDEC #define smnPCIEMSIX_PBA_DEFAULT … // addressBlock: nbio_pcie_pswusp0_pciedir_p #define smnPCIEP_RESERVED_DEFAULT … #define smnPCIEP_SCRATCH_DEFAULT … #define smnPCIEP_PORT_CNTL_DEFAULT … #define smnPCIE_TX_CNTL_DEFAULT … #define smnPCIE_TX_REQUESTER_ID_DEFAULT … #define smnPCIE_TX_VENDOR_SPECIFIC_DEFAULT … #define smnPCIE_TX_REQUEST_NUM_CNTL_DEFAULT … #define smnPCIE_TX_SEQ_DEFAULT … #define smnPCIE_TX_REPLAY_DEFAULT … #define smnPCIE_TX_ACK_LATENCY_LIMIT_DEFAULT … #define smnPCIE_TX_CREDITS_ADVT_P_DEFAULT … #define smnPCIE_TX_CREDITS_ADVT_NP_DEFAULT … #define smnPCIE_TX_CREDITS_ADVT_CPL_DEFAULT … #define smnPCIE_TX_CREDITS_INIT_P_DEFAULT … #define smnPCIE_TX_CREDITS_INIT_NP_DEFAULT … #define smnPCIE_TX_CREDITS_INIT_CPL_DEFAULT … #define smnPCIE_TX_CREDITS_STATUS_DEFAULT … #define smnPCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT … #define smnPCIE_P_PORT_LANE_STATUS_DEFAULT … #define smnPCIE_FC_P_DEFAULT … #define smnPCIE_FC_NP_DEFAULT … #define smnPCIE_FC_CPL_DEFAULT … #define smnPSWUSP0_PCIE_ERR_CNTL_DEFAULT … #define smnPSWUSP0_PCIE_RX_CNTL_DEFAULT … #define smnPCIE_RX_EXPECTED_SEQNUM_DEFAULT … #define smnPCIE_RX_VENDOR_SPECIFIC_DEFAULT … #define smnPCIE_RX_CNTL3_DEFAULT … #define smnPCIE_RX_CREDITS_ALLOCATED_P_DEFAULT … #define smnPCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT … #define smnPCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT … #define smnPCIEP_ERROR_INJECT_PHYSICAL_DEFAULT … #define smnPCIEP_ERROR_INJECT_TRANSACTION_DEFAULT … #define smnPCIEP_SRIOV_PRIV_CTRL_DEFAULT … #define smnPCIEP_NAK_COUNTER_DEFAULT … #define smnPCIE_LC_CNTL_DEFAULT … #define smnPCIE_LC_TRAINING_CNTL_DEFAULT … #define smnPCIE_LC_LINK_WIDTH_CNTL_DEFAULT … #define smnPCIE_LC_N_FTS_CNTL_DEFAULT … #define smnPSWUSP0_PCIE_LC_SPEED_CNTL_DEFAULT … #define smnPCIE_LC_STATE0_DEFAULT … #define smnPCIE_LC_STATE1_DEFAULT … #define smnPCIE_LC_STATE2_DEFAULT … #define smnPCIE_LC_STATE3_DEFAULT … #define smnPCIE_LC_STATE4_DEFAULT … #define smnPCIE_LC_STATE5_DEFAULT … #define smnPCIE_LINK_MANAGEMENT_CNTL2_DEFAULT … #define smnPSWUSP0_PCIE_LC_CNTL2_DEFAULT … #define smnPCIE_LC_BW_CHANGE_CNTL_DEFAULT … #define smnPCIE_LC_CDR_CNTL_DEFAULT … #define smnPCIE_LC_LANE_CNTL_DEFAULT … #define smnPCIE_LC_CNTL3_DEFAULT … #define smnPCIE_LC_CNTL4_DEFAULT … #define smnPCIE_LC_CNTL5_DEFAULT … #define smnPCIE_LC_FORCE_COEFF_DEFAULT … #define smnPCIE_LC_BEST_EQ_SETTINGS_DEFAULT … #define smnPCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT … #define smnPCIE_LC_CNTL6_DEFAULT … #define smnPCIE_LC_CNTL7_DEFAULT … #define smnPCIE_LINK_MANAGEMENT_STATUS_DEFAULT … #define smnPCIE_LINK_MANAGEMENT_MASK_DEFAULT … #define smnPCIE_LINK_MANAGEMENT_CNTL_DEFAULT … #define smnPCIEP_STRAP_LC_DEFAULT … #define smnPSWUSP0_PCIEP_STRAP_MISC_DEFAULT … #define smnPCIE_LC_L1_PM_SUBSTATE_DEFAULT … #define smnPCIE_LC_L1_PM_SUBSTATE2_DEFAULT … #define smnPCIE_LC_PORT_ORDER_DEFAULT … #define smnPCIEP_BCH_ECC_CNTL_DEFAULT … // addressBlock: nbio_pcie_pciedir #define smnPCIE_RESERVED_DEFAULT … #define smnPCIE_SCRATCH_DEFAULT … #define smnPCIE_RX_NUM_NAK_DEFAULT … #define smnPCIE_RX_NUM_NAK_GENERATED_DEFAULT … #define smnPCIE_CNTL_DEFAULT … #define smnPCIE_CONFIG_CNTL_DEFAULT … #define smnPCIE_TX_TRACKING_ADDR_LO_DEFAULT … #define smnPCIE_TX_TRACKING_ADDR_HI_DEFAULT … #define smnPCIE_TX_TRACKING_CTRL_STATUS_DEFAULT … #define smnPCIE_BW_BY_UNITID_DEFAULT … #define smnPCIE_CNTL2_DEFAULT … #define smnPCIE_RX_CNTL2_DEFAULT … #define smnPCIE_TX_F0_ATTR_CNTL_DEFAULT … #define smnPCIE_TX_SWUS_ATTR_CNTL_DEFAULT … #define smnPCIE_CI_CNTL_DEFAULT … #define smnPCIE_BUS_CNTL_DEFAULT … #define smnPCIE_LC_STATE6_DEFAULT … #define smnPCIE_LC_STATE7_DEFAULT … #define smnPCIE_LC_STATE8_DEFAULT … #define smnPCIE_LC_STATE9_DEFAULT … #define smnPCIE_LC_STATE10_DEFAULT … #define smnPCIE_LC_STATE11_DEFAULT … #define smnPCIE_LC_STATUS1_DEFAULT … #define smnPCIE_LC_STATUS2_DEFAULT … #define smnPCIE_WPR_CNTL_DEFAULT … #define smnPCIE_RX_LAST_TLP0_DEFAULT … #define smnPCIE_RX_LAST_TLP1_DEFAULT … #define smnPCIE_RX_LAST_TLP2_DEFAULT … #define smnPCIE_RX_LAST_TLP3_DEFAULT … #define smnPCIE_TX_LAST_TLP0_DEFAULT … #define smnPCIE_TX_LAST_TLP1_DEFAULT … #define smnPCIE_TX_LAST_TLP2_DEFAULT … #define smnPCIE_TX_LAST_TLP3_DEFAULT … #define smnPCIE_I2C_REG_ADDR_EXPAND_DEFAULT … #define smnPCIE_I2C_REG_DATA_DEFAULT … #define smnPCIE_CFG_CNTL_DEFAULT … #define smnPCIE_LC_PM_CNTL_DEFAULT … #define smnPCIE_LC_PORT_ORDER_CNTL_DEFAULT … #define smnPCIE_P_CNTL_DEFAULT … #define smnPCIE_P_BUF_STATUS_DEFAULT … #define smnPCIE_P_DECODER_STATUS_DEFAULT … #define smnPCIE_P_MISC_STATUS_DEFAULT … #define smnPCIE_P_RCV_L0S_FTS_DET_DEFAULT … #define smnPCIE_RX_AD_DEFAULT … #define smnPCIE_SDP_CTRL_DEFAULT … #define smnPCIE_SDP_SWUS_SLV_ATTR_CTRL_DEFAULT … #define smnPCIE_PERF_COUNT_CNTL_DEFAULT … #define smnPCIE_PERF_CNTL_TXCLK_DEFAULT … #define smnPCIE_PERF_COUNT0_TXCLK_DEFAULT … #define smnPCIE_PERF_COUNT1_TXCLK_DEFAULT … #define smnPCIE_PERF_CNTL_MST_R_CLK_DEFAULT … #define smnPCIE_PERF_COUNT0_MST_R_CLK_DEFAULT … #define smnPCIE_PERF_COUNT1_MST_R_CLK_DEFAULT … #define smnPCIE_PERF_CNTL_MST_C_CLK_DEFAULT … #define smnPCIE_PERF_COUNT0_MST_C_CLK_DEFAULT … #define smnPCIE_PERF_COUNT1_MST_C_CLK_DEFAULT … #define smnPCIE_PERF_CNTL_SLV_R_CLK_DEFAULT … #define smnPCIE_PERF_COUNT0_SLV_R_CLK_DEFAULT … #define smnPCIE_PERF_COUNT1_SLV_R_CLK_DEFAULT … #define smnPCIE_PERF_CNTL_SLV_S_C_CLK_DEFAULT … #define smnPCIE_PERF_COUNT0_SLV_S_C_CLK_DEFAULT … #define smnPCIE_PERF_COUNT1_SLV_S_C_CLK_DEFAULT … #define smnPCIE_PERF_CNTL_SLV_NS_C_CLK_DEFAULT … #define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK_DEFAULT … #define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK_DEFAULT … #define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL_DEFAULT … #define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL_DEFAULT … #define smnPCIE_PERF_CNTL_TXCLK2_DEFAULT … #define smnPCIE_PERF_COUNT0_TXCLK2_DEFAULT … #define smnPCIE_PERF_COUNT1_TXCLK2_DEFAULT … #define smnPCIE_PRBS_CLR_DEFAULT … #define smnPCIE_PRBS_STATUS1_DEFAULT … #define smnPCIE_PRBS_STATUS2_DEFAULT … #define smnPCIE_PRBS_FREERUN_DEFAULT … #define smnPCIE_PRBS_MISC_DEFAULT … #define smnPCIE_PRBS_USER_PATTERN_DEFAULT … #define smnPCIE_PRBS_LO_BITCNT_DEFAULT … #define smnPCIE_PRBS_HI_BITCNT_DEFAULT … #define smnPCIE_PRBS_ERRCNT_0_DEFAULT … #define smnPCIE_PRBS_ERRCNT_1_DEFAULT … #define smnPCIE_PRBS_ERRCNT_2_DEFAULT … #define smnPCIE_PRBS_ERRCNT_3_DEFAULT … #define smnPCIE_PRBS_ERRCNT_4_DEFAULT … #define smnPCIE_PRBS_ERRCNT_5_DEFAULT … #define smnPCIE_PRBS_ERRCNT_6_DEFAULT … #define smnPCIE_PRBS_ERRCNT_7_DEFAULT … #define smnPCIE_PRBS_ERRCNT_8_DEFAULT … #define smnPCIE_PRBS_ERRCNT_9_DEFAULT … #define smnPCIE_PRBS_ERRCNT_10_DEFAULT … #define smnPCIE_PRBS_ERRCNT_11_DEFAULT … #define smnPCIE_PRBS_ERRCNT_12_DEFAULT … #define smnPCIE_PRBS_ERRCNT_13_DEFAULT … #define smnPCIE_PRBS_ERRCNT_14_DEFAULT … #define smnPCIE_PRBS_ERRCNT_15_DEFAULT … #define smnSWRST_COMMAND_STATUS_DEFAULT … #define smnSWRST_GENERAL_CONTROL_DEFAULT … #define smnSWRST_COMMAND_0_DEFAULT … #define smnSWRST_COMMAND_1_DEFAULT … #define smnSWRST_CONTROL_0_DEFAULT … #define smnSWRST_CONTROL_1_DEFAULT … #define smnSWRST_CONTROL_2_DEFAULT … #define smnSWRST_CONTROL_3_DEFAULT … #define smnSWRST_CONTROL_4_DEFAULT … #define smnSWRST_CONTROL_5_DEFAULT … #define smnSWRST_CONTROL_6_DEFAULT … #define smnSWRST_EP_COMMAND_0_DEFAULT … #define smnSWRST_EP_CONTROL_0_DEFAULT … #define smnCPM_CONTROL_DEFAULT … #define smnSMN_APERTURE_ID_A_DEFAULT … #define smnSMN_APERTURE_ID_B_DEFAULT … #define smnRSMU_MASTER_CONTROL_DEFAULT … #define smnRSMU_SLAVE_CONTROL_DEFAULT … #define smnRSMU_POWER_GATING_CONTROL_DEFAULT … #define smnRSMU_BIOS_TIMER_CMD_DEFAULT … #define smnRSMU_BIOS_TIMER_CNTL_DEFAULT … #define smnLNCNT_CONTROL_DEFAULT … #define smnCFG_LNC_WINDOW_REGISTER_DEFAULT … #define smnLNCNT_QUAN_THRD_DEFAULT … #define smnLNCNT_WEIGHT_DEFAULT … #define smnLNC_TOTAL_WACC_REGISTER_DEFAULT … #define smnLNC_BW_WACC_REGISTER_DEFAULT … #define smnLNC_CMN_WACC_REGISTER_DEFAULT … #define smnSMU_INT_PIN_SHARING_PORT_INDICATOR_DEFAULT … #define smnSMU_PCIE_FENCED1_REG_DEFAULT … #define smnSMU_PCIE_FENCED2_REG_DEFAULT … // addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns0_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … // addressBlock: nbio_pipe_pcs_lcu_pcie_pcs_prime_phyx4_pcs_prime_dir #define smnDXIO_HWDID_DEFAULT … #define smnDXIO_LINKAGE_LANEGRP_DEFAULT … #define smnDXIO_LINKAGE_KPDMX_DEFAULT … #define smnDXIO_LINKAGE_KPMX_DEFAULT … #define smnDXIO_LINKAGE_KPFIFO_DEFAULT … #define smnDXIO_LINKAGE_KPNP_DEFAULT … #define smnPCS_LANEGRP0_MAPPING_DEFAULT … #define smnPCS_LANEGRP1_MAPPING_DEFAULT … #define smnPCS_LANEGRP2_MAPPING_DEFAULT … #define smnPCS_LANEGRP3_MAPPING_DEFAULT … #define smnPCS_LANEGRP4_MAPPING_DEFAULT … #define smnPCS_LANEGRP5_MAPPING_DEFAULT … #define smnPCS_LANEGRP6_MAPPING_DEFAULT … #define smnPCS_LANEGRP7_MAPPING_DEFAULT … #define smnMAC_CAPABILITIES1_DEFAULT … #define smnMAC_CAPABILITIES2_DEFAULT … #define smnPCS_CAPABILITIES_DEFAULT … #define smnPCS_EXTENDED_CAP_DEFAULT … #define smnPCS_APERTURE0_LOC_DEFAULT … #define smnPCS_APERTURE0_IDX_DEFAULT … #define smnPCS_APERTURE1_LOC_DEFAULT … #define smnPCS_APERTURE1_IDX_DEFAULT … #define smnPCS_APERTURE2_LOC_DEFAULT … #define smnPCS_APERTURE2_IDX_DEFAULT … #define smnPCS_APERTURE3_LOC_DEFAULT … #define smnPCS_APERTURE3_IDX_DEFAULT … #define smnDXIO_CFG_SOFT_RESET_DEFAULT … #define smnKPX_LANE_DATA_SOFT_RESET1_DEFAULT … #define smnKPX_LANE_DATA_SOFT_RESET_DEFAULT … #define smnKPX_PMA_INFO_SOFT_RESET_DEFAULT … #define smnPCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET_DEFAULT … #define smnPCS_SOFT_RESET_DEFAULT … #define smnPCS_LCU_CNTL_DEFAULT … #define smnPCS_PIPE_PER_LANE_SOFT_RESET_DEFAULT … // addressBlock: nbio_lcu_kpfifo_kpfifo0_kpfifo_dir #define smnKPFIFO0_PRI_TX_FIFO_HSCID_DEFAULT … #define smnKPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0_DEFAULT … #define smnKPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1_DEFAULT … #define smnKPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2_DEFAULT … #define smnKPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3_DEFAULT … #define smnKPFIFO0_PCS_PMA_SOFT_RESET_DEFAULT … // addressBlock: nbio_lcu_kpnp_kpnp0_kpnp_dir #define smnKPNP_SNPS0_KPNP_HWSCVER_DEFAULT … #define smnKPNP_SNPS0_KPNP_PHY_INFO_DEFAULT … #define smnKPNP_SNPS0_KPNP_LANE_ID_DEFAULT … #define smnKPNP_SNPS0_KPNP_LANE_REQ_CONTROL_DEFAULT … #define smnKPNP_SNPS0_KPNP_LANE_REQ_STATUS_DEFAULT … #define smnKPNP_SNPS0_KPNP_PMA_CONTROL0_DEFAULT … #define smnKPNP_SNPS0_KPNP_PMA_CONTROL1_DEFAULT … #define smnKPNP_SNPS0_KPNP_PMA_CONTROL2_DEFAULT … #define smnKPNP_SNPS0_KPNP_PHY_SOFT_RESET_DEFAULT … #define smnKPNP_SNPS0_KPNP_LANE_SOFT_RESET_DEFAULT … #define smnKPNP_SNPS0_REG_RST_CTRL_DEFAULT … // addressBlock: nbio_pipe_pcs_pcs_core0_dir #define smnPCS_PCIEX16_IP_IDENTITY_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL0_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL1_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL2_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL3_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL4_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL5_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL6_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL7_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL8_DEFAULT … #define smnPCS_PCIEX16_LANE0_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE1_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE2_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE3_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE4_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE5_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE6_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE7_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE8_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE9_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE10_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE11_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE12_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE13_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE14_CONTROL_DEFAULT … #define smnPCS_PCIEX16_LANE15_CONTROL_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL9_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL10_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL11_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL12_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL13_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL14_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL15_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL16_DEFAULT … #define smnPCS_PCIEX16_GLOBAL_CONTROL17_DEFAULT … // addressBlock: nbio_pipe_pcs_pcs_pciex16_gaskt_pcs_pciex16_gaskt_dir #define smnPCS_GLOBAL_CONTROL17_DEFAULT … #define smnPCS_GLOBAL_CONTROL18_DEFAULT … #define smnPCS_GLOBAL_CONTROL19_DEFAULT … #define smnPCS_GLOBAL_CONTROL20_DEFAULT … #define smnPCS_GLOBAL_CONTROL21_DEFAULT … #define smnPCS_GLOBAL_CONTROL22_DEFAULT … #define smnPCS_GLOBAL_CONTROL23_DEFAULT … #define smnPCS_GLOBAL_CONTROL24_DEFAULT … #define smnPCS_GLOBAL_CONTROL25_DEFAULT … #define smnPCS_GLOBAL_CONTROL26_DEFAULT … #define smnPCS_GLOBAL_CONTROL27_DEFAULT … #define smnPCS_GLOBAL_CONTROL28_DEFAULT … #define smnPCS_GLOBAL_CONTROL29_DEFAULT … #define smnPCS_GLOBAL_CONTROL30_DEFAULT … #define smnPCS_STATUS1_DEFAULT … #define smnPCS_LANE0_CNTRL1_DEFAULT … #define smnPCS_LANE1_CNTRL1_DEFAULT … #define smnPCS_LANE2_CNTRL1_DEFAULT … #define smnPCS_LANE3_CNTRL1_DEFAULT … #define smnPCS_LANE4_CNTRL1_DEFAULT … #define smnPCS_LANE5_CNTRL1_DEFAULT … #define smnPCS_LANE6_CNTRL1_DEFAULT … #define smnPCS_LANE7_CNTRL1_DEFAULT … #define smnPCS_LANE8_CNTRL1_DEFAULT … #define smnPCS_LANE9_CNTRL1_DEFAULT … #define smnPCS_LANE10_CNTRL1_DEFAULT … #define smnPCS_LANE11_CNTRL1_DEFAULT … #define smnPCS_LANE12_CNTRL1_DEFAULT … #define smnPCS_LANE13_CNTRL1_DEFAULT … #define smnPCS_LANE14_CNTRL1_DEFAULT … #define smnPCS_LANE15_CNTRL1_DEFAULT … #define smnPCS_LANE0_COEFF1_DEFAULT … #define smnPCS_LANE1_COEFF1_DEFAULT … #define smnPCS_LANE2_COEFF1_DEFAULT … #define smnPCS_LANE3_COEFF1_DEFAULT … #define smnPCS_LANE4_COEFF1_DEFAULT … #define smnPCS_LANE5_COEFF1_DEFAULT … #define smnPCS_LANE6_COEFF1_DEFAULT … #define smnPCS_LANE7_COEFF1_DEFAULT … #define smnPCS_LANE8_COEFF1_DEFAULT … #define smnPCS_LANE9_COEFF1_DEFAULT … #define smnPCS_LANE10_COEFF1_DEFAULT … #define smnPCS_LANE11_COEFF1_DEFAULT … #define smnPCS_LANE12_COEFF1_DEFAULT … #define smnPCS_LANE13_COEFF1_DEFAULT … #define smnPCS_LANE14_COEFF1_DEFAULT … #define smnPCS_LANE15_COEFF1_DEFAULT … #define smnPCS_LANE0_COEFF2_DEFAULT … #define smnPCS_LANE1_COEFF2_DEFAULT … #define smnPCS_LANE2_COEFF2_DEFAULT … #define smnPCS_LANE3_COEFF2_DEFAULT … #define smnPCS_LANE4_COEFF2_DEFAULT … #define smnPCS_LANE5_COEFF2_DEFAULT … #define smnPCS_LANE6_COEFF2_DEFAULT … #define smnPCS_LANE7_COEFF2_DEFAULT … #define smnPCS_LANE8_COEFF2_DEFAULT … #define smnPCS_LANE9_COEFF2_DEFAULT … #define smnPCS_LANE10_COEFF2_DEFAULT … #define smnPCS_LANE11_COEFF2_DEFAULT … #define smnPCS_LANE12_COEFF2_DEFAULT … #define smnPCS_LANE13_COEFF2_DEFAULT … #define smnPCS_LANE14_COEFF2_DEFAULT … #define smnPCS_LANE15_COEFF2_DEFAULT … #define smnPCS_LANE0_COEFF3_DEFAULT … #define smnPCS_LANE1_COEFF3_DEFAULT … #define smnPCS_LANE2_COEFF3_DEFAULT … #define smnPCS_LANE3_COEFF3_DEFAULT … #define smnPCS_LANE4_COEFF3_DEFAULT … #define smnPCS_LANE5_COEFF3_DEFAULT … #define smnPCS_LANE6_COEFF3_DEFAULT … #define smnPCS_LANE7_COEFF3_DEFAULT … #define smnPCS_LANE8_COEFF3_DEFAULT … #define smnPCS_LANE9_COEFF3_DEFAULT … #define smnPCS_LANE10_COEFF3_DEFAULT … #define smnPCS_LANE11_COEFF3_DEFAULT … #define smnPCS_LANE12_COEFF3_DEFAULT … #define smnPCS_LANE13_COEFF3_DEFAULT … #define smnPCS_LANE14_COEFF3_DEFAULT … #define smnPCS_LANE15_COEFF3_DEFAULT … // addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns1_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … // addressBlock: nbio_lcu_kpfifo_kpfifo1_kpfifo_dir #define smnKPFIFO1_PRI_TX_FIFO_HSCID_DEFAULT … #define smnKPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0_DEFAULT … #define smnKPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1_DEFAULT … #define smnKPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2_DEFAULT … #define smnKPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3_DEFAULT … #define smnKPFIFO1_PCS_PMA_SOFT_RESET_DEFAULT … // addressBlock: nbio_lcu_kpnp_kpnp1_kpnp_dir #define smnKPNP_SNPS1_KPNP_HWSCVER_DEFAULT … #define smnKPNP_SNPS1_KPNP_PHY_INFO_DEFAULT … #define smnKPNP_SNPS1_KPNP_LANE_ID_DEFAULT … #define smnKPNP_SNPS1_KPNP_LANE_REQ_CONTROL_DEFAULT … #define smnKPNP_SNPS1_KPNP_LANE_REQ_STATUS_DEFAULT … #define smnKPNP_SNPS1_KPNP_PMA_CONTROL0_DEFAULT … #define smnKPNP_SNPS1_KPNP_PMA_CONTROL1_DEFAULT … #define smnKPNP_SNPS1_KPNP_PMA_CONTROL2_DEFAULT … #define smnKPNP_SNPS1_KPNP_PHY_SOFT_RESET_DEFAULT … #define smnKPNP_SNPS1_KPNP_LANE_SOFT_RESET_DEFAULT … #define smnKPNP_SNPS1_REG_RST_CTRL_DEFAULT … // addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns2_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … // addressBlock: nbio_lcu_kpfifo_kpfifo2_kpfifo_dir #define smnKPFIFO2_PRI_TX_FIFO_HSCID_DEFAULT … #define smnKPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0_DEFAULT … #define smnKPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1_DEFAULT … #define smnKPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2_DEFAULT … #define smnKPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3_DEFAULT … #define smnKPFIFO2_PCS_PMA_SOFT_RESET_DEFAULT … // addressBlock: nbio_lcu_kpnp_kpnp2_kpnp_dir #define smnKPNP_SNPS2_KPNP_HWSCVER_DEFAULT … #define smnKPNP_SNPS2_KPNP_PHY_INFO_DEFAULT … #define smnKPNP_SNPS2_KPNP_LANE_ID_DEFAULT … #define smnKPNP_SNPS2_KPNP_LANE_REQ_CONTROL_DEFAULT … #define smnKPNP_SNPS2_KPNP_LANE_REQ_STATUS_DEFAULT … #define smnKPNP_SNPS2_KPNP_PMA_CONTROL0_DEFAULT … #define smnKPNP_SNPS2_KPNP_PMA_CONTROL1_DEFAULT … #define smnKPNP_SNPS2_KPNP_PMA_CONTROL2_DEFAULT … #define smnKPNP_SNPS2_KPNP_PHY_SOFT_RESET_DEFAULT … #define smnKPNP_SNPS2_KPNP_LANE_SOFT_RESET_DEFAULT … #define smnKPNP_SNPS2_REG_RST_CTRL_DEFAULT … // addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns3_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT … #define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT … // addressBlock: nbio_lcu_kpfifo_kpfifo3_kpfifo_dir #define smnKPFIFO3_PRI_TX_FIFO_HSCID_DEFAULT … #define smnKPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0_DEFAULT … #define smnKPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1_DEFAULT … #define smnKPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2_DEFAULT … #define smnKPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3_DEFAULT … #define smnKPFIFO3_PCS_PMA_SOFT_RESET_DEFAULT … // addressBlock: nbio_lcu_kpnp_kpnp3_kpnp_dir #define smnKPNP_SNPS3_KPNP_HWSCVER_DEFAULT … #define smnKPNP_SNPS3_KPNP_PHY_INFO_DEFAULT … #define smnKPNP_SNPS3_KPNP_LANE_ID_DEFAULT … #define smnKPNP_SNPS3_KPNP_LANE_REQ_CONTROL_DEFAULT … #define smnKPNP_SNPS3_KPNP_LANE_REQ_STATUS_DEFAULT … #define smnKPNP_SNPS3_KPNP_PMA_CONTROL0_DEFAULT … #define smnKPNP_SNPS3_KPNP_PMA_CONTROL1_DEFAULT … #define smnKPNP_SNPS3_KPNP_PMA_CONTROL2_DEFAULT … #define smnKPNP_SNPS3_KPNP_PHY_SOFT_RESET_DEFAULT … #define smnKPNP_SNPS3_KPNP_LANE_SOFT_RESET_DEFAULT … #define smnKPNP_SNPS3_REG_RST_CTRL_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_DEFAULT … // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_DEFAULT … #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_DEFAULT … // addressBlock: syshub_mmreg_ind_syshubind #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT … #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD_DEFAULT … #define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT … #endif
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