/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _uvd_7_0_OFFSET_HEADER #define _uvd_7_0_OFFSET_HEADER // addressBlock: uvd0_uvd_pg_dec // base address: 0x1fb00 #define mmUVD_POWER_STATUS … #define mmUVD_POWER_STATUS_BASE_IDX … #define mmUVD_DPG_RBC_RB_CNTL … #define mmUVD_DPG_RBC_RB_CNTL_BASE_IDX … #define mmUVD_DPG_RBC_RB_BASE_LOW … #define mmUVD_DPG_RBC_RB_BASE_LOW_BASE_IDX … #define mmUVD_DPG_RBC_RB_BASE_HIGH … #define mmUVD_DPG_RBC_RB_BASE_HIGH_BASE_IDX … #define mmUVD_DPG_RBC_RB_WPTR_CNTL … #define mmUVD_DPG_RBC_RB_WPTR_CNTL_BASE_IDX … #define mmUVD_DPG_RBC_RB_RPTR … #define mmUVD_DPG_RBC_RB_RPTR_BASE_IDX … #define mmUVD_DPG_RBC_RB_WPTR … #define mmUVD_DPG_RBC_RB_WPTR_BASE_IDX … #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW … #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH … #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_DPG_VCPU_CACHE_OFFSET0 … #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX … // addressBlock: uvd0_uvdnpdec // base address: 0x20000 #define mmUVD_JPEG_ADDR_CONFIG … #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX … #define mmUVD_GPCOM_VCPU_CMD … #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX … #define mmUVD_GPCOM_VCPU_DATA0 … #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX … #define mmUVD_GPCOM_VCPU_DATA1 … #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX … #define mmUVD_UDEC_ADDR_CONFIG … #define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX … #define mmUVD_UDEC_DB_ADDR_CONFIG … #define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX … #define mmUVD_UDEC_DBW_ADDR_CONFIG … #define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX … #define mmUVD_SUVD_CGC_GATE … #define mmUVD_SUVD_CGC_GATE_BASE_IDX … #define mmUVD_SUVD_CGC_CTRL … #define mmUVD_SUVD_CGC_CTRL_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH … #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW … #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH … #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_POWER_STATUS_U … #define mmUVD_POWER_STATUS_U_BASE_IDX … #define mmUVD_NO_OP … #define mmUVD_NO_OP_BASE_IDX … #define mmUVD_GP_SCRATCH8 … #define mmUVD_GP_SCRATCH8_BASE_IDX … #define mmUVD_RB_BASE_LO2 … #define mmUVD_RB_BASE_LO2_BASE_IDX … #define mmUVD_RB_BASE_HI2 … #define mmUVD_RB_BASE_HI2_BASE_IDX … #define mmUVD_RB_SIZE2 … #define mmUVD_RB_SIZE2_BASE_IDX … #define mmUVD_RB_RPTR2 … #define mmUVD_RB_RPTR2_BASE_IDX … #define mmUVD_RB_WPTR2 … #define mmUVD_RB_WPTR2_BASE_IDX … #define mmUVD_RB_BASE_LO … #define mmUVD_RB_BASE_LO_BASE_IDX … #define mmUVD_RB_BASE_HI … #define mmUVD_RB_BASE_HI_BASE_IDX … #define mmUVD_RB_SIZE … #define mmUVD_RB_SIZE_BASE_IDX … #define mmUVD_RB_RPTR … #define mmUVD_RB_RPTR_BASE_IDX … #define mmUVD_RB_WPTR … #define mmUVD_RB_WPTR_BASE_IDX … #define mmUVD_JRBC_RB_RPTR … #define mmUVD_JRBC_RB_RPTR_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH … #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW … #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH … #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW … #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX … // addressBlock: uvd0_uvddec // base address: 0x20c00 #define mmUVD_SEMA_CNTL … #define mmUVD_SEMA_CNTL_BASE_IDX … #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_JRBC_RB_WPTR … #define mmUVD_JRBC_RB_WPTR_BASE_IDX … #define mmUVD_RB_RPTR3 … #define mmUVD_RB_RPTR3_BASE_IDX … #define mmUVD_RB_WPTR3 … #define mmUVD_RB_WPTR3_BASE_IDX … #define mmUVD_RB_BASE_LO3 … #define mmUVD_RB_BASE_LO3_BASE_IDX … #define mmUVD_RB_BASE_HI3 … #define mmUVD_RB_BASE_HI3_BASE_IDX … #define mmUVD_RB_SIZE3 … #define mmUVD_RB_SIZE3_BASE_IDX … #define mmJPEG_CGC_GATE … #define mmJPEG_CGC_GATE_BASE_IDX … #define mmUVD_CTX_INDEX … #define mmUVD_CTX_INDEX_BASE_IDX … #define mmUVD_CTX_DATA … #define mmUVD_CTX_DATA_BASE_IDX … #define mmUVD_CGC_GATE … #define mmUVD_CGC_GATE_BASE_IDX … #define mmUVD_CGC_CTRL … #define mmUVD_CGC_CTRL_BASE_IDX … #define mmUVD_GP_SCRATCH4 … #define mmUVD_GP_SCRATCH4_BASE_IDX … #define mmUVD_LMI_CTRL2 … #define mmUVD_LMI_CTRL2_BASE_IDX … #define mmUVD_MASTINT_EN … #define mmUVD_MASTINT_EN_BASE_IDX … #define mmUVD_FW_STATUS … #define mmUVD_FW_STATUS_BASE_IDX … #define mmJPEG_CGC_CTRL … #define mmJPEG_CGC_CTRL_BASE_IDX … #define mmUVD_LMI_CTRL … #define mmUVD_LMI_CTRL_BASE_IDX … #define mmUVD_LMI_VM_CTRL … #define mmUVD_LMI_VM_CTRL_BASE_IDX … #define mmUVD_LMI_SWAP_CNTL … #define mmUVD_LMI_SWAP_CNTL_BASE_IDX … #define mmUVD_MP_SWAP_CNTL … #define mmUVD_MP_SWAP_CNTL_BASE_IDX … #define mmUVD_MPC_SET_MUXA0 … #define mmUVD_MPC_SET_MUXA0_BASE_IDX … #define mmUVD_MPC_SET_MUXA1 … #define mmUVD_MPC_SET_MUXA1_BASE_IDX … #define mmUVD_MPC_SET_MUXB0 … #define mmUVD_MPC_SET_MUXB0_BASE_IDX … #define mmUVD_MPC_SET_MUXB1 … #define mmUVD_MPC_SET_MUXB1_BASE_IDX … #define mmUVD_MPC_SET_MUX … #define mmUVD_MPC_SET_MUX_BASE_IDX … #define mmUVD_MPC_SET_ALU … #define mmUVD_MPC_SET_ALU_BASE_IDX … #define mmUVD_VCPU_CACHE_OFFSET0 … #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX … #define mmUVD_VCPU_CACHE_SIZE0 … #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX … #define mmUVD_VCPU_CACHE_OFFSET1 … #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX … #define mmUVD_VCPU_CACHE_SIZE1 … #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX … #define mmUVD_VCPU_CACHE_OFFSET2 … #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX … #define mmUVD_VCPU_CACHE_SIZE2 … #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX … #define mmUVD_VCPU_CNTL … #define mmUVD_VCPU_CNTL_BASE_IDX … #define mmUVD_SOFT_RESET … #define mmUVD_SOFT_RESET_BASE_IDX … #define mmUVD_LMI_RBC_IB_VMID … #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX … #define mmUVD_RBC_IB_SIZE … #define mmUVD_RBC_IB_SIZE_BASE_IDX … #define mmUVD_RBC_RB_RPTR … #define mmUVD_RBC_RB_RPTR_BASE_IDX … #define mmUVD_RBC_RB_WPTR … #define mmUVD_RBC_RB_WPTR_BASE_IDX … #define mmUVD_RBC_RB_WPTR_CNTL … #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX … #define mmUVD_RBC_RB_CNTL … #define mmUVD_RBC_RB_CNTL_BASE_IDX … #define mmUVD_RBC_RB_RPTR_ADDR … #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX … #define mmUVD_STATUS … #define mmUVD_STATUS_BASE_IDX … #define mmUVD_SEMA_TIMEOUT_STATUS … #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX … #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL … #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX … #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL … #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX … #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX … #define mmUVD_CONTEXT_ID … #define mmUVD_CONTEXT_ID_BASE_IDX … #define mmUVD_CONTEXT_ID2 … #define mmUVD_CONTEXT_ID2_BASE_IDX … #endif
Codebase Browser
linux