/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/pci.h> #include <drm/amdgpu_drm.h> #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" #include "amdgpu_uvd.h" #include "amdgpu_vce.h" #include "atom.h" #include "amd_pcie.h" #include "si_dpm.h" #include "sid.h" #include "si_ih.h" #include "gfx_v6_0.h" #include "gmc_v6_0.h" #include "si_dma.h" #include "dce_v6_0.h" #include "si.h" #include "uvd_v3_1.h" #include "amdgpu_vkms.h" #include "gca/gfx_6_0_d.h" #include "oss/oss_1_0_d.h" #include "oss/oss_1_0_sh_mask.h" #include "gmc/gmc_6_0_d.h" #include "dce/dce_6_0_d.h" #include "uvd/uvd_4_0_d.h" #include "bif/bif_3_0_d.h" #include "bif/bif_3_0_sh_mask.h" #include "amdgpu_dm.h" static const u32 tahiti_golden_registers[] = …; static const u32 tahiti_golden_registers2[] = …; static const u32 tahiti_golden_rlc_registers[] = …; static const u32 pitcairn_golden_registers[] = …; static const u32 pitcairn_golden_rlc_registers[] = …; static const u32 verde_pg_init[] = …; static const u32 verde_golden_rlc_registers[] = …; static const u32 verde_golden_registers[] = …; static const u32 oland_golden_registers[] = …; static const u32 oland_golden_rlc_registers[] = …; static const u32 hainan_golden_registers[] = …; static const u32 hainan_golden_registers2[] = …; static const u32 tahiti_mgcg_cgcg_init[] = …; static const u32 pitcairn_mgcg_cgcg_init[] = …; static const u32 verde_mgcg_cgcg_init[] = …; static const u32 oland_mgcg_cgcg_init[] = …; static const u32 hainan_mgcg_cgcg_init[] = …; /* XXX: update when we support VCE */ #if 0 /* tahiti, pitcarin, verde */ static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] = { { .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, .max_width = 2048, .max_height = 1152, .max_pixels_per_frame = 2048 * 1152, .max_level = 0, }, }; static const struct amdgpu_video_codecs tahiti_video_codecs_encode = { .codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array), .codec_array = tahiti_video_codecs_encode_array, }; #else static const struct amdgpu_video_codecs tahiti_video_codecs_encode = …; #endif /* oland and hainan don't support encode */ static const struct amdgpu_video_codecs hainan_video_codecs_encode = …; /* tahiti, pitcarin, verde, oland */ static const struct amdgpu_video_codec_info tahiti_video_codecs_decode_array[] = …; static const struct amdgpu_video_codecs tahiti_video_codecs_decode = …; /* hainan doesn't support decode */ static const struct amdgpu_video_codecs hainan_video_codecs_decode = …; static int si_query_video_codecs(struct amdgpu_device *adev, bool encode, const struct amdgpu_video_codecs **codecs) { … } static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) { … } static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) { … } static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) { … } static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) { … } static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = …; static uint32_t si_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { … } static int si_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) { … } static bool si_read_disabled_bios(struct amdgpu_device *adev) { … } #define mmROM_INDEX … #define mmROM_DATA … static bool si_read_bios_from_rom(struct amdgpu_device *adev, u8 *bios, u32 length_bytes) { … } static void si_set_clk_bypass_mode(struct amdgpu_device *adev) { … } static void si_spll_powerdown(struct amdgpu_device *adev) { … } static int si_gpu_pci_config_reset(struct amdgpu_device *adev) { … } static int si_asic_supports_baco(struct amdgpu_device *adev) { … } static enum amd_reset_method si_asic_reset_method(struct amdgpu_device *adev) { … } static int si_asic_reset(struct amdgpu_device *adev) { … } static u32 si_get_config_memsize(struct amdgpu_device *adev) { … } static void si_vga_set_state(struct amdgpu_device *adev, bool state) { … } static u32 si_get_xclk(struct amdgpu_device *adev) { … } static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { … } static void si_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { … } static bool si_need_full_reset(struct amdgpu_device *adev) { … } static bool si_need_reset_on_init(struct amdgpu_device *adev) { … } static int si_get_pcie_lanes(struct amdgpu_device *adev) { … } static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes) { … } static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, uint64_t *count1) { … } static uint64_t si_get_pcie_replay_count(struct amdgpu_device *adev) { … } static int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev, unsigned cg_upll_func_cntl) { … } static unsigned si_uvd_calc_upll_post_div(unsigned vco_freq, unsigned target_freq, unsigned pd_min, unsigned pd_even) { … } /** * si_calc_upll_dividers - calc UPLL clock dividers * * @adev: amdgpu_device pointer * @vclk: wanted VCLK * @dclk: wanted DCLK * @vco_min: minimum VCO frequency * @vco_max: maximum VCO frequency * @fb_factor: factor to multiply vco freq with * @fb_mask: limit and bitmask for feedback divider * @pd_min: post divider minimum * @pd_max: post divider maximum * @pd_even: post divider must be even above this value * @optimal_fb_div: resulting feedback divider * @optimal_vclk_div: resulting vclk post divider * @optimal_dclk_div: resulting dclk post divider * * Calculate dividers for UVDs UPLL (except APUs). * Returns zero on success; -EINVAL on error. */ static int si_calc_upll_dividers(struct amdgpu_device *adev, unsigned vclk, unsigned dclk, unsigned vco_min, unsigned vco_max, unsigned fb_factor, unsigned fb_mask, unsigned pd_min, unsigned pd_max, unsigned pd_even, unsigned *optimal_fb_div, unsigned *optimal_vclk_div, unsigned *optimal_dclk_div) { … } static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) { … } static int si_vce_send_vcepll_ctlreq(struct amdgpu_device *adev) { … } static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) { … } static void si_pre_asic_init(struct amdgpu_device *adev) { … } static const struct amdgpu_asic_funcs si_asic_funcs = …; static uint32_t si_get_rev_id(struct amdgpu_device *adev) { … } static int si_common_early_init(void *handle) { … } static int si_common_sw_init(void *handle) { … } static int si_common_sw_fini(void *handle) { … } static void si_init_golden_registers(struct amdgpu_device *adev) { … } static void si_pcie_gen3_enable(struct amdgpu_device *adev) { … } static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) { … } static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) { … } static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static void si_program_aspm(struct amdgpu_device *adev) { … } static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev) { … } static int si_common_hw_init(void *handle) { … } static int si_common_hw_fini(void *handle) { … } static int si_common_suspend(void *handle) { … } static int si_common_resume(void *handle) { … } static bool si_common_is_idle(void *handle) { … } static int si_common_wait_for_idle(void *handle) { … } static int si_common_soft_reset(void *handle) { … } static int si_common_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int si_common_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static const struct amd_ip_funcs si_common_ip_funcs = …; static const struct amdgpu_ip_block_version si_common_ip_block = …; int si_set_ip_blocks(struct amdgpu_device *adev) { … }
Codebase Browser
linux