/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef SI_ENUMS_H #define SI_ENUMS_H #define VBLANK_INT_MASK … #define DC_HPDx_INT_EN … #define VBLANK_ACK … #define VLINE_ACK … #define CURSOR_WIDTH … #define CURSOR_HEIGHT … #define VGA_VSTATUS_CNTL … #define PRIORITY_MARK_MASK … #define PRIORITY_OFF … #define PRIORITY_ALWAYS_ON … #define INTERLEAVE_EN … #define LATENCY_WATERMARK_MASK(x) … #define DC_LB_MEMORY_CONFIG(x) … #define ICON_DEGAMMA_MODE(x) … #define GRPH_ENDIAN_SWAP(x) … #define GRPH_ENDIAN_NONE … #define GRPH_ENDIAN_8IN16 … #define GRPH_ENDIAN_8IN32 … #define GRPH_ENDIAN_8IN64 … #define GRPH_RED_CROSSBAR(x) … #define GRPH_RED_SEL_R … #define GRPH_RED_SEL_G … #define GRPH_RED_SEL_B … #define GRPH_RED_SEL_A … #define GRPH_GREEN_CROSSBAR(x) … #define GRPH_GREEN_SEL_G … #define GRPH_GREEN_SEL_B … #define GRPH_GREEN_SEL_A … #define GRPH_GREEN_SEL_R … #define GRPH_BLUE_CROSSBAR(x) … #define GRPH_BLUE_SEL_B … #define GRPH_BLUE_SEL_A … #define GRPH_BLUE_SEL_R … #define GRPH_BLUE_SEL_G … #define GRPH_ALPHA_CROSSBAR(x) … #define GRPH_ALPHA_SEL_A … #define GRPH_ALPHA_SEL_R … #define GRPH_ALPHA_SEL_G … #define GRPH_ALPHA_SEL_B … #define GRPH_DEPTH(x) … #define GRPH_DEPTH_8BPP … #define GRPH_DEPTH_16BPP … #define GRPH_DEPTH_32BPP … #define GRPH_FORMAT(x) … #define GRPH_FORMAT_INDEXED … #define GRPH_FORMAT_ARGB1555 … #define GRPH_FORMAT_ARGB565 … #define GRPH_FORMAT_ARGB4444 … #define GRPH_FORMAT_AI88 … #define GRPH_FORMAT_MONO16 … #define GRPH_FORMAT_BGRA5551 … #define GRPH_FORMAT_ARGB8888 … #define GRPH_FORMAT_ARGB2101010 … #define GRPH_FORMAT_32BPP_DIG … #define GRPH_FORMAT_8B_ARGB2101010 … #define GRPH_FORMAT_BGRA1010102 … #define GRPH_FORMAT_8B_BGRA1010102 … #define GRPH_FORMAT_RGB111110 … #define GRPH_FORMAT_BGR101111 … #define GRPH_NUM_BANKS(x) … #define GRPH_ARRAY_MODE(x) … #define GRPH_ARRAY_LINEAR_GENERAL … #define GRPH_ARRAY_LINEAR_ALIGNED … #define GRPH_ARRAY_1D_TILED_THIN1 … #define GRPH_ARRAY_2D_TILED_THIN1 … #define GRPH_TILE_SPLIT(x) … #define GRPH_BANK_WIDTH(x) … #define GRPH_BANK_HEIGHT(x) … #define GRPH_MACRO_TILE_ASPECT(x) … #define GRPH_ARRAY_MODE(x) … #define GRPH_PIPE_CONFIG(x) … #define CURSOR_EN … #define CURSOR_MODE(x) … #define CURSOR_MONO … #define CURSOR_24_1 … #define CURSOR_24_8_PRE_MULT … #define CURSOR_24_8_UNPRE_MULT … #define CURSOR_2X_MAGNIFY … #define CURSOR_FORCE_MC_ON … #define CURSOR_URGENT_CONTROL(x) … #define CURSOR_URGENT_ALWAYS … #define CURSOR_URGENT_1_8 … #define CURSOR_URGENT_1_4 … #define CURSOR_URGENT_3_8 … #define CURSOR_URGENT_1_2 … #define CURSOR_UPDATE_PENDING … #define CURSOR_UPDATE_TAKEN … #define CURSOR_UPDATE_LOCK … #define CURSOR_DISABLE_MULTIPLE_UPDATE … #define SI_CRTC0_REGISTER_OFFSET … #define SI_CRTC1_REGISTER_OFFSET … #define SI_CRTC2_REGISTER_OFFSET … #define SI_CRTC3_REGISTER_OFFSET … #define SI_CRTC4_REGISTER_OFFSET … #define SI_CRTC5_REGISTER_OFFSET … #define DMA0_REGISTER_OFFSET … #define DMA1_REGISTER_OFFSET … #define ES_AND_GS_AUTO … #define RADEON_PACKET_TYPE3 … #define CE_PARTITION_BASE … #define BUF_SWAP_32BIT … #define GFX_POWER_STATUS … #define GFX_CLOCK_STATUS … #define GFX_LS_STATUS … #define RLC_BUSY_STATUS … #define RLC_PUD(x) … #define RLC_PUD_MASK … #define RLC_PDD(x) … #define RLC_PDD_MASK … #define RLC_TTPD(x) … #define RLC_TTPD_MASK … #define RLC_MSD(x) … #define RLC_MSD_MASK … #define WRITE_DATA_ENGINE_SEL(x) … #define WRITE_DATA_DST_SEL(x) … #define EVENT_TYPE(x) … #define EVENT_INDEX(x) … #define WAIT_REG_MEM_MEM_SPACE(x) … #define WAIT_REG_MEM_FUNCTION(x) … #define WAIT_REG_MEM_ENGINE(x) … #define GFX6_NUM_GFX_RINGS … #define GFX6_NUM_COMPUTE_RINGS … #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET … #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET … #define TAHITI_GB_ADDR_CONFIG_GOLDEN … #define VERDE_GB_ADDR_CONFIG_GOLDEN … #define HAINAN_GB_ADDR_CONFIG_GOLDEN … #define PACKET3(op, n) … #define PACKET3_COMPUTE(op, n) … #define PACKET3_NOP … #define PACKET3_SET_BASE … #define PACKET3_BASE_INDEX(x) … #define PACKET3_CLEAR_STATE … #define PACKET3_INDEX_BUFFER_SIZE … #define PACKET3_DISPATCH_DIRECT … #define PACKET3_DISPATCH_INDIRECT … #define PACKET3_ALLOC_GDS … #define PACKET3_WRITE_GDS_RAM … #define PACKET3_ATOMIC_GDS … #define PACKET3_ATOMIC … #define PACKET3_OCCLUSION_QUERY … #define PACKET3_SET_PREDICATION … #define PACKET3_REG_RMW … #define PACKET3_COND_EXEC … #define PACKET3_PRED_EXEC … #define PACKET3_DRAW_INDIRECT … #define PACKET3_DRAW_INDEX_INDIRECT … #define PACKET3_INDEX_BASE … #define PACKET3_DRAW_INDEX_2 … #define PACKET3_CONTEXT_CONTROL … #define PACKET3_INDEX_TYPE … #define PACKET3_DRAW_INDIRECT_MULTI … #define PACKET3_DRAW_INDEX_AUTO … #define PACKET3_DRAW_INDEX_IMMD … #define PACKET3_NUM_INSTANCES … #define PACKET3_DRAW_INDEX_MULTI_AUTO … #define PACKET3_INDIRECT_BUFFER_CONST … #define PACKET3_INDIRECT_BUFFER … #define PACKET3_STRMOUT_BUFFER_UPDATE … #define PACKET3_DRAW_INDEX_OFFSET_2 … #define PACKET3_DRAW_INDEX_MULTI_ELEMENT … #define PACKET3_WRITE_DATA … #define PACKET3_DRAW_INDEX_INDIRECT_MULTI … #define PACKET3_MEM_SEMAPHORE … #define PACKET3_MPEG_INDEX … #define PACKET3_COPY_DW … #define PACKET3_WAIT_REG_MEM … #define PACKET3_MEM_WRITE … #define PACKET3_COPY_DATA … #define PACKET3_CP_DMA … #define PACKET3_CP_DMA_DST_SEL(x) … #define PACKET3_CP_DMA_ENGINE(x) … #define PACKET3_CP_DMA_SRC_SEL(x) … #define PACKET3_CP_DMA_CP_SYNC … #define PACKET3_CP_DMA_DIS_WC … #define PACKET3_CP_DMA_CMD_SRC_SWAP(x) … #define PACKET3_CP_DMA_CMD_DST_SWAP(x) … #define PACKET3_CP_DMA_CMD_SAS … #define PACKET3_CP_DMA_CMD_DAS … #define PACKET3_CP_DMA_CMD_SAIC … #define PACKET3_CP_DMA_CMD_DAIC … #define PACKET3_CP_DMA_CMD_RAW_WAIT … #define PACKET3_PFP_SYNC_ME … #define PACKET3_SURFACE_SYNC … #define PACKET3_DEST_BASE_0_ENA … #define PACKET3_DEST_BASE_1_ENA … #define PACKET3_CB0_DEST_BASE_ENA … #define PACKET3_CB1_DEST_BASE_ENA … #define PACKET3_CB2_DEST_BASE_ENA … #define PACKET3_CB3_DEST_BASE_ENA … #define PACKET3_CB4_DEST_BASE_ENA … #define PACKET3_CB5_DEST_BASE_ENA … #define PACKET3_CB6_DEST_BASE_ENA … #define PACKET3_CB7_DEST_BASE_ENA … #define PACKET3_DB_DEST_BASE_ENA … #define PACKET3_DEST_BASE_2_ENA … #define PACKET3_DEST_BASE_3_ENA … #define PACKET3_TCL1_ACTION_ENA … #define PACKET3_TC_ACTION_ENA … #define PACKET3_CB_ACTION_ENA … #define PACKET3_DB_ACTION_ENA … #define PACKET3_SH_KCACHE_ACTION_ENA … #define PACKET3_SH_ICACHE_ACTION_ENA … #define PACKET3_ME_INITIALIZE … #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) … #define PACKET3_COND_WRITE … #define PACKET3_EVENT_WRITE … #define PACKET3_EVENT_WRITE_EOP … #define PACKET3_EVENT_WRITE_EOS … #define PACKET3_PREAMBLE_CNTL … #define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE … #define PACKET3_PREAMBLE_END_CLEAR_STATE … #define PACKET3_ONE_REG_WRITE … #define PACKET3_LOAD_CONFIG_REG … #define PACKET3_LOAD_CONTEXT_REG … #define PACKET3_LOAD_SH_REG … #define PACKET3_SET_CONFIG_REG … #define PACKET3_SET_CONFIG_REG_START … #define PACKET3_SET_CONFIG_REG_END … #define PACKET3_SET_CONTEXT_REG … #define PACKET3_SET_CONTEXT_REG_START … #define PACKET3_SET_CONTEXT_REG_END … #define PACKET3_SET_CONTEXT_REG_INDIRECT … #define PACKET3_SET_RESOURCE_INDIRECT … #define PACKET3_SET_SH_REG … #define PACKET3_SET_SH_REG_START … #define PACKET3_SET_SH_REG_END … #define PACKET3_SET_SH_REG_OFFSET … #define PACKET3_ME_WRITE … #define PACKET3_SCRATCH_RAM_WRITE … #define PACKET3_SCRATCH_RAM_READ … #define PACKET3_CE_WRITE … #define PACKET3_LOAD_CONST_RAM … #define PACKET3_WRITE_CONST_RAM … #define PACKET3_WRITE_CONST_RAM_OFFSET … #define PACKET3_DUMP_CONST_RAM … #define PACKET3_INCREMENT_CE_COUNTER … #define PACKET3_INCREMENT_DE_COUNTER … #define PACKET3_WAIT_ON_CE_COUNTER … #define PACKET3_WAIT_ON_DE_COUNTER … #define PACKET3_WAIT_ON_DE_COUNTER_DIFF … #define PACKET3_SET_CE_DE_COUNTERS … #define PACKET3_WAIT_ON_AVAIL_BUFFER … #define PACKET3_SWITCH_BUFFER … #define PACKET3_SEM_WAIT_ON_SIGNAL … #define PACKET3_SEM_SEL_SIGNAL … #define PACKET3_SEM_SEL_WAIT … #endif
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