linux/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h

/*
 * OSS_3_0 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef OSS_3_0_D_H
#define OSS_3_0_D_H

#define mmIH_VMID_0_LUT
#define mmIH_VMID_1_LUT
#define mmIH_VMID_2_LUT
#define mmIH_VMID_3_LUT
#define mmIH_VMID_4_LUT
#define mmIH_VMID_5_LUT
#define mmIH_VMID_6_LUT
#define mmIH_VMID_7_LUT
#define mmIH_VMID_8_LUT
#define mmIH_VMID_9_LUT
#define mmIH_VMID_10_LUT
#define mmIH_VMID_11_LUT
#define mmIH_VMID_12_LUT
#define mmIH_VMID_13_LUT
#define mmIH_VMID_14_LUT
#define mmIH_VMID_15_LUT
#define mmIH_RB_CNTL
#define mmIH_RB_BASE
#define mmIH_RB_RPTR
#define mmIH_RB_WPTR
#define mmIH_RB_WPTR_ADDR_HI
#define mmIH_RB_WPTR_ADDR_LO
#define mmIH_CNTL
#define mmIH_LEVEL_STATUS
#define mmIH_STATUS
#define mmIH_PERFMON_CNTL
#define mmIH_PERFCOUNTER0_RESULT
#define mmIH_PERFCOUNTER1_RESULT
#define mmIH_DEBUG
#define mmIH_DSM_MATCH_VALUE_BIT_31_0
#define mmIH_DSM_MATCH_VALUE_BIT_63_32
#define mmIH_DSM_MATCH_VALUE_BIT_95_64
#define mmIH_DSM_MATCH_FIELD_CONTROL
#define mmIH_DSM_MATCH_DATA_CONTROL
#define mmIH_DOORBELL_RPTR
#define mmIH_ACTIVE_FCN_ID
#define mmIH_VF_RB_STATUS
#define mmIH_VF_ENABLE
#define mmIH_VIRT_RESET_REQ
#define mmIH_VF_RB_BIF_STATUS
#define mmIH_VERSION
#define mmIH_LEVEL_INTR_MASK
#define mmIH_RESET_INCOMPLETE_INT_CNTL
#define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT
#define mmSEM_MCIF_CONFIG
#define mmSDMA_CONFIG
#define mmSDMA1_CONFIG
#define mmUVD_CONFIG
#define mmVCE_CONFIG
#define mmSEM_VF_ENABLE
#define mmCP_CONFIG
#define mmSEM_ACTIVE_FCN_ID
#define mmSEM_VIRT_RESET_REQ
#define mmSEM_STATUS
#define mmSEM_EDC_CONFIG
#define mmSEM_MAILBOX_CLIENTCONFIG
#define mmSEM_MAILBOX
#define mmSEM_MAILBOX_CONTROL
#define mmSEM_CHICKEN_BITS
#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA
#define mmSRBM_CNTL
#define mmSRBM_GFX_CNTL
#define mmSRBM_READ_CNTL
#define mmSRBM_STATUS2
#define mmSRBM_STATUS
#define mmSRBM_STATUS3
#define mmSRBM_SOFT_RESET
#define mmSRBM_DEBUG_CNTL
#define mmSRBM_DEBUG_DATA
#define mmSRBM_CHIP_REVISION
#define mmSRBM_CREDIT_RECOVER_CNTL
#define mmSRBM_CREDIT_RECOVER
#define mmSRBM_CREDIT_RESET
#define mmCC_SYS_RB_REDUNDANCY
#define mmCC_SYS_RB_BACKEND_DISABLE
#define mmGC_USER_SYS_RB_BACKEND_DISABLE
#define mmSRBM_MC_CLKEN_CNTL
#define mmSRBM_SYS_CLKEN_CNTL
#define mmSRBM_VCE_CLKEN_CNTL
#define mmSRBM_UVD_CLKEN_CNTL
#define mmSRBM_SDMA_CLKEN_CNTL
#define mmSRBM_SAM_CLKEN_CNTL
#define mmSRBM_ISP_CLKEN_CNTL
#define mmSRBM_VP8_CLKEN_CNTL
#define mmSRBM_DEBUG
#define mmSRBM_DEBUG_SNAPSHOT
#define mmSRBM_DEBUG_SNAPSHOT2
#define mmSRBM_READ_ERROR
#define mmSRBM_READ_ERROR2
#define mmSRBM_INT_CNTL
#define mmSRBM_INT_STATUS
#define mmSRBM_INT_ACK
#define mmSRBM_FIREWALL_ERROR_SRC
#define mmSRBM_FIREWALL_ERROR_ADDR
#define mmSRBM_DSM_TRIG_CNTL0
#define mmSRBM_DSM_TRIG_CNTL1
#define mmSRBM_DSM_TRIG_MASK0
#define mmSRBM_DSM_TRIG_MASK1
#define mmSRBM_PERFMON_CNTL
#define mmSRBM_PERFCOUNTER0_SELECT
#define mmSRBM_PERFCOUNTER1_SELECT
#define mmSRBM_PERFCOUNTER0_LO
#define mmSRBM_PERFCOUNTER0_HI
#define mmSRBM_PERFCOUNTER1_LO
#define mmSRBM_PERFCOUNTER1_HI
#define mmSRBM_CAM_INDEX
#define mmSRBM_CAM_DATA
#define mmSRBM_MC_DOMAIN_ADDR0
#define mmSRBM_MC_DOMAIN_ADDR1
#define mmSRBM_MC_DOMAIN_ADDR2
#define mmSRBM_MC_DOMAIN_ADDR3
#define mmSRBM_MC_DOMAIN_ADDR4
#define mmSRBM_MC_DOMAIN_ADDR5
#define mmSRBM_MC_DOMAIN_ADDR6
#define mmSRBM_SYS_DOMAIN_ADDR0
#define mmSRBM_SYS_DOMAIN_ADDR1
#define mmSRBM_SYS_DOMAIN_ADDR2
#define mmSRBM_SYS_DOMAIN_ADDR3
#define mmSRBM_SYS_DOMAIN_ADDR4
#define mmSRBM_SYS_DOMAIN_ADDR5
#define mmSRBM_SYS_DOMAIN_ADDR6
#define mmSRBM_SDMA_DOMAIN_ADDR0
#define mmSRBM_SDMA_DOMAIN_ADDR1
#define mmSRBM_SDMA_DOMAIN_ADDR2
#define mmSRBM_SDMA_DOMAIN_ADDR3
#define mmSRBM_UVD_DOMAIN_ADDR0
#define mmSRBM_UVD_DOMAIN_ADDR1
#define mmSRBM_UVD_DOMAIN_ADDR2
#define mmSRBM_VCE_DOMAIN_ADDR0
#define mmSRBM_VCE_DOMAIN_ADDR1
#define mmSRBM_VCE_DOMAIN_ADDR2
#define mmSRBM_SAM_DOMAIN_ADDR0
#define mmSRBM_SAM_DOMAIN_ADDR1
#define mmSRBM_SAM_DOMAIN_ADDR2
#define mmSRBM_ISP_DOMAIN_ADDR0
#define mmSRBM_ISP_DOMAIN_ADDR1
#define mmSRBM_ISP_DOMAIN_ADDR2
#define mmSRBM_VP8_DOMAIN_ADDR0
#define mmSYS_GRBM_GFX_INDEX_SELECT
#define mmSYS_GRBM_GFX_INDEX_DATA
#define mmSRBM_GFX_CNTL_SELECT
#define mmSRBM_GFX_CNTL_DATA
#define mmSRBM_VF_ENABLE
#define mmSRBM_VIRT_CNTL
#define mmSRBM_VIRT_RESET_REQ
#define mmCC_DRM_ID_STRAPS
#define mmCGTT_DRM_CLK_CTRL0
#define ixDH_TEST
#define ixKHFS0
#define ixKHFS1
#define ixKHFS2
#define ixKHFS3
#define ixKSESSION0
#define ixKSESSION1
#define ixKSESSION2
#define ixKSESSION3
#define ixKSIG0
#define ixKSIG1
#define ixKSIG2
#define ixKSIG3
#define ixEXP0
#define ixEXP1
#define ixEXP2
#define ixEXP3
#define ixEXP4
#define ixEXP5
#define ixEXP6
#define ixEXP7
#define ixLX0
#define ixLX1
#define ixLX2
#define ixLX3
#define ixCLIENT2_K0
#define ixCLIENT2_K1
#define ixCLIENT2_K2
#define ixCLIENT2_K3
#define ixCLIENT2_CK0
#define ixCLIENT2_CK1
#define ixCLIENT2_CK2
#define ixCLIENT2_CK3
#define ixCLIENT2_CD0
#define ixCLIENT2_CD1
#define ixCLIENT2_CD2
#define ixCLIENT2_CD3
#define ixCLIENT2_BM
#define ixCLIENT2_OFFSET
#define ixCLIENT2_STATUS
#define ixCLIENT0_K0
#define ixCLIENT0_K1
#define ixCLIENT0_K2
#define ixCLIENT0_K3
#define ixCLIENT0_CK0
#define ixCLIENT0_CK1
#define ixCLIENT0_CK2
#define ixCLIENT0_CK3
#define ixCLIENT0_CD0
#define ixCLIENT0_CD1
#define ixCLIENT0_CD2
#define ixCLIENT0_CD3
#define ixCLIENT0_BM
#define ixCLIENT0_OFFSET
#define ixCLIENT0_STATUS
#define ixCLIENT1_K0
#define ixCLIENT1_K1
#define ixCLIENT1_K2
#define ixCLIENT1_K3
#define ixCLIENT1_CK0
#define ixCLIENT1_CK1
#define ixCLIENT1_CK2
#define ixCLIENT1_CK3
#define ixCLIENT1_CD0
#define ixCLIENT1_CD1
#define ixCLIENT1_CD2
#define ixCLIENT1_CD3
#define ixCLIENT1_BM
#define ixCLIENT1_OFFSET
#define ixCLIENT1_PORT_STATUS
#define ixKEFUSE0
#define ixKEFUSE1
#define ixKEFUSE2
#define ixKEFUSE3
#define ixHFS_SEED0
#define ixHFS_SEED1
#define ixHFS_SEED2
#define ixHFS_SEED3
#define ixRINGOSC_MASK
#define ixCLIENT0_OFFSET_HI
#define ixCLIENT1_OFFSET_HI
#define ixCLIENT2_OFFSET_HI
#define ixSPU_PORT_STATUS
#define ixCLIENT3_OFFSET_HI
#define ixCLIENT3_K0
#define ixCLIENT3_K1
#define ixCLIENT3_K2
#define ixCLIENT3_K3
#define ixCLIENT3_CK0
#define ixCLIENT3_CK1
#define ixCLIENT3_CK2
#define ixCLIENT3_CK3
#define ixCLIENT3_CD0
#define ixCLIENT3_CD1
#define ixCLIENT3_CD2
#define ixCLIENT3_CD3
#define ixCLIENT3_BM
#define ixCLIENT3_OFFSET
#define ixCLIENT3_STATUS
#define ixCLIENT4_OFFSET_HI
#define ixCLIENT4_K0
#define ixCLIENT4_K1
#define ixCLIENT4_K2
#define ixCLIENT4_K3
#define ixCLIENT4_CK0
#define ixCLIENT4_CK1
#define ixCLIENT4_CK2
#define ixCLIENT4_CK3
#define ixCLIENT4_CD0
#define ixCLIENT4_CD1
#define ixCLIENT4_CD2
#define ixCLIENT4_CD3
#define ixCLIENT4_BM
#define ixCLIENT4_OFFSET
#define ixCLIENT4_STATUS
#define mmDC_TEST_DEBUG_INDEX
#define mmDC_TEST_DEBUG_DATA
#define mmSDMA0_UCODE_ADDR
#define mmSDMA0_UCODE_DATA
#define mmSDMA0_POWER_CNTL
#define mmSDMA0_CLK_CTRL
#define mmSDMA0_CNTL
#define mmSDMA0_CHICKEN_BITS
#define mmSDMA0_TILING_CONFIG
#define mmSDMA0_HASH
#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
#define mmSDMA0_RB_RPTR_FETCH
#define mmSDMA0_IB_OFFSET_FETCH
#define mmSDMA0_PROGRAM
#define mmSDMA0_STATUS_REG
#define mmSDMA0_STATUS1_REG
#define mmSDMA0_RD_BURST_CNTL
#define mmSDMA0_PERFMON_CNTL
#define mmSDMA0_PERFCOUNTER0_RESULT
#define mmSDMA0_PERFCOUNTER1_RESULT
#define mmSDMA0_F32_CNTL
#define mmSDMA0_FREEZE
#define mmSDMA0_PHASE0_QUANTUM
#define mmSDMA0_PHASE1_QUANTUM
#define mmSDMA_POWER_GATING
#define mmSDMA_PGFSM_CONFIG
#define mmSDMA_PGFSM_WRITE
#define mmSDMA_PGFSM_READ
#define mmSDMA0_EDC_CONFIG
#define mmSDMA0_VM_CNTL
#define mmSDMA0_VM_CTX_LO
#define mmSDMA0_VM_CTX_HI
#define mmSDMA0_STATUS2_REG
#define mmSDMA0_ACTIVE_FCN_ID
#define mmSDMA0_VM_CTX_CNTL
#define mmSDMA0_VIRT_RESET_REQ
#define mmSDMA0_VF_ENABLE
#define mmSDMA0_BA_THRESHOLD
#define mmSDMA0_ID
#define mmSDMA0_VERSION
#define mmSDMA0_ATOMIC_CNTL
#define mmSDMA0_ATOMIC_PREOP_LO
#define mmSDMA0_ATOMIC_PREOP_HI
#define mmSDMA0_POWER_CNTL_IDLE
#define mmSDMA0_PERF_REG_TYPE0
#define mmSDMA0_CONTEXT_REG_TYPE0
#define mmSDMA0_CONTEXT_REG_TYPE1
#define mmSDMA0_CONTEXT_REG_TYPE2
#define mmSDMA0_PUB_REG_TYPE0
#define mmSDMA0_PUB_REG_TYPE1
#define mmSDMA0_GFX_RB_CNTL
#define mmSDMA0_GFX_RB_BASE
#define mmSDMA0_GFX_RB_BASE_HI
#define mmSDMA0_GFX_RB_RPTR
#define mmSDMA0_GFX_RB_WPTR
#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_GFX_RB_RPTR_ADDR_HI
#define mmSDMA0_GFX_RB_RPTR_ADDR_LO
#define mmSDMA0_GFX_IB_CNTL
#define mmSDMA0_GFX_IB_RPTR
#define mmSDMA0_GFX_IB_OFFSET
#define mmSDMA0_GFX_IB_BASE_LO
#define mmSDMA0_GFX_IB_BASE_HI
#define mmSDMA0_GFX_IB_SIZE
#define mmSDMA0_GFX_SKIP_CNTL
#define mmSDMA0_GFX_CONTEXT_STATUS
#define mmSDMA0_GFX_DOORBELL
#define mmSDMA0_GFX_CONTEXT_CNTL
#define mmSDMA0_GFX_VIRTUAL_ADDR
#define mmSDMA0_GFX_APE1_CNTL
#define mmSDMA0_GFX_DOORBELL_LOG
#define mmSDMA0_GFX_WATERMARK
#define mmSDMA0_GFX_CSA_ADDR_LO
#define mmSDMA0_GFX_CSA_ADDR_HI
#define mmSDMA0_GFX_IB_SUB_REMAIN
#define mmSDMA0_GFX_PREEMPT
#define mmSDMA0_GFX_DUMMY_REG
#define mmSDMA0_GFX_MIDCMD_DATA0
#define mmSDMA0_GFX_MIDCMD_DATA1
#define mmSDMA0_GFX_MIDCMD_DATA2
#define mmSDMA0_GFX_MIDCMD_DATA3
#define mmSDMA0_GFX_MIDCMD_DATA4
#define mmSDMA0_GFX_MIDCMD_DATA5
#define mmSDMA0_GFX_MIDCMD_CNTL
#define mmSDMA0_RLC0_RB_CNTL
#define mmSDMA0_RLC0_RB_BASE
#define mmSDMA0_RLC0_RB_BASE_HI
#define mmSDMA0_RLC0_RB_RPTR
#define mmSDMA0_RLC0_RB_WPTR
#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC0_IB_CNTL
#define mmSDMA0_RLC0_IB_RPTR
#define mmSDMA0_RLC0_IB_OFFSET
#define mmSDMA0_RLC0_IB_BASE_LO
#define mmSDMA0_RLC0_IB_BASE_HI
#define mmSDMA0_RLC0_IB_SIZE
#define mmSDMA0_RLC0_SKIP_CNTL
#define mmSDMA0_RLC0_CONTEXT_STATUS
#define mmSDMA0_RLC0_DOORBELL
#define mmSDMA0_RLC0_VIRTUAL_ADDR
#define mmSDMA0_RLC0_APE1_CNTL
#define mmSDMA0_RLC0_DOORBELL_LOG
#define mmSDMA0_RLC0_WATERMARK
#define mmSDMA0_RLC0_CSA_ADDR_LO
#define mmSDMA0_RLC0_CSA_ADDR_HI
#define mmSDMA0_RLC0_IB_SUB_REMAIN
#define mmSDMA0_RLC0_PREEMPT
#define mmSDMA0_RLC0_DUMMY_REG
#define mmSDMA0_RLC0_MIDCMD_DATA0
#define mmSDMA0_RLC0_MIDCMD_DATA1
#define mmSDMA0_RLC0_MIDCMD_DATA2
#define mmSDMA0_RLC0_MIDCMD_DATA3
#define mmSDMA0_RLC0_MIDCMD_DATA4
#define mmSDMA0_RLC0_MIDCMD_DATA5
#define mmSDMA0_RLC0_MIDCMD_CNTL
#define mmSDMA0_RLC1_RB_CNTL
#define mmSDMA0_RLC1_RB_BASE
#define mmSDMA0_RLC1_RB_BASE_HI
#define mmSDMA0_RLC1_RB_RPTR
#define mmSDMA0_RLC1_RB_WPTR
#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI
#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO
#define mmSDMA0_RLC1_IB_CNTL
#define mmSDMA0_RLC1_IB_RPTR
#define mmSDMA0_RLC1_IB_OFFSET
#define mmSDMA0_RLC1_IB_BASE_LO
#define mmSDMA0_RLC1_IB_BASE_HI
#define mmSDMA0_RLC1_IB_SIZE
#define mmSDMA0_RLC1_SKIP_CNTL
#define mmSDMA0_RLC1_CONTEXT_STATUS
#define mmSDMA0_RLC1_DOORBELL
#define mmSDMA0_RLC1_VIRTUAL_ADDR
#define mmSDMA0_RLC1_APE1_CNTL
#define mmSDMA0_RLC1_DOORBELL_LOG
#define mmSDMA0_RLC1_WATERMARK
#define mmSDMA0_RLC1_CSA_ADDR_LO
#define mmSDMA0_RLC1_CSA_ADDR_HI
#define mmSDMA0_RLC1_IB_SUB_REMAIN
#define mmSDMA0_RLC1_PREEMPT
#define mmSDMA0_RLC1_DUMMY_REG
#define mmSDMA0_RLC1_MIDCMD_DATA0
#define mmSDMA0_RLC1_MIDCMD_DATA1
#define mmSDMA0_RLC1_MIDCMD_DATA2
#define mmSDMA0_RLC1_MIDCMD_DATA3
#define mmSDMA0_RLC1_MIDCMD_DATA4
#define mmSDMA0_RLC1_MIDCMD_DATA5
#define mmSDMA0_RLC1_MIDCMD_CNTL
#define mmSDMA1_UCODE_ADDR
#define mmSDMA1_UCODE_DATA
#define mmSDMA1_POWER_CNTL
#define mmSDMA1_CLK_CTRL
#define mmSDMA1_CNTL
#define mmSDMA1_CHICKEN_BITS
#define mmSDMA1_TILING_CONFIG
#define mmSDMA1_HASH
#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL
#define mmSDMA1_RB_RPTR_FETCH
#define mmSDMA1_IB_OFFSET_FETCH
#define mmSDMA1_PROGRAM
#define mmSDMA1_STATUS_REG
#define mmSDMA1_STATUS1_REG
#define mmSDMA1_RD_BURST_CNTL
#define mmSDMA1_PERFMON_CNTL
#define mmSDMA1_PERFCOUNTER0_RESULT
#define mmSDMA1_PERFCOUNTER1_RESULT
#define mmSDMA1_F32_CNTL
#define mmSDMA1_FREEZE
#define mmSDMA1_PHASE0_QUANTUM
#define mmSDMA1_PHASE1_QUANTUM
#define mmSDMA1_EDC_CONFIG
#define mmSDMA1_VM_CNTL
#define mmSDMA1_VM_CTX_LO
#define mmSDMA1_VM_CTX_HI
#define mmSDMA1_STATUS2_REG
#define mmSDMA1_ACTIVE_FCN_ID
#define mmSDMA1_VM_CTX_CNTL
#define mmSDMA1_VIRT_RESET_REQ
#define mmSDMA1_VF_ENABLE
#define mmSDMA1_BA_THRESHOLD
#define mmSDMA1_ID
#define mmSDMA1_VERSION
#define mmSDMA1_ATOMIC_CNTL
#define mmSDMA1_ATOMIC_PREOP_LO
#define mmSDMA1_ATOMIC_PREOP_HI
#define mmSDMA1_POWER_CNTL_IDLE
#define mmSDMA1_PERF_REG_TYPE0
#define mmSDMA1_CONTEXT_REG_TYPE0
#define mmSDMA1_CONTEXT_REG_TYPE1
#define mmSDMA1_CONTEXT_REG_TYPE2
#define mmSDMA1_PUB_REG_TYPE0
#define mmSDMA1_PUB_REG_TYPE1
#define mmSDMA1_GFX_RB_CNTL
#define mmSDMA1_GFX_RB_BASE
#define mmSDMA1_GFX_RB_BASE_HI
#define mmSDMA1_GFX_RB_RPTR
#define mmSDMA1_GFX_RB_WPTR
#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL
#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI
#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO
#define mmSDMA1_GFX_RB_RPTR_ADDR_HI
#define mmSDMA1_GFX_RB_RPTR_ADDR_LO
#define mmSDMA1_GFX_IB_CNTL
#define mmSDMA1_GFX_IB_RPTR
#define mmSDMA1_GFX_IB_OFFSET
#define mmSDMA1_GFX_IB_BASE_LO
#define mmSDMA1_GFX_IB_BASE_HI
#define mmSDMA1_GFX_IB_SIZE
#define mmSDMA1_GFX_SKIP_CNTL
#define mmSDMA1_GFX_CONTEXT_STATUS
#define mmSDMA1_GFX_DOORBELL
#define mmSDMA1_GFX_CONTEXT_CNTL
#define mmSDMA1_GFX_VIRTUAL_ADDR
#define mmSDMA1_GFX_APE1_CNTL
#define mmSDMA1_GFX_DOORBELL_LOG
#define mmSDMA1_GFX_WATERMARK
#define mmSDMA1_GFX_CSA_ADDR_LO
#define mmSDMA1_GFX_CSA_ADDR_HI
#define mmSDMA1_GFX_IB_SUB_REMAIN
#define mmSDMA1_GFX_PREEMPT
#define mmSDMA1_GFX_DUMMY_REG
#define mmSDMA1_GFX_MIDCMD_DATA0
#define mmSDMA1_GFX_MIDCMD_DATA1
#define mmSDMA1_GFX_MIDCMD_DATA2
#define mmSDMA1_GFX_MIDCMD_DATA3
#define mmSDMA1_GFX_MIDCMD_DATA4
#define mmSDMA1_GFX_MIDCMD_DATA5
#define mmSDMA1_GFX_MIDCMD_CNTL
#define mmSDMA1_RLC0_RB_CNTL
#define mmSDMA1_RLC0_RB_BASE
#define mmSDMA1_RLC0_RB_BASE_HI
#define mmSDMA1_RLC0_RB_RPTR
#define mmSDMA1_RLC0_RB_WPTR
#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL
#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI
#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO
#define mmSDMA1_RLC0_IB_CNTL
#define mmSDMA1_RLC0_IB_RPTR
#define mmSDMA1_RLC0_IB_OFFSET
#define mmSDMA1_RLC0_IB_BASE_LO
#define mmSDMA1_RLC0_IB_BASE_HI
#define mmSDMA1_RLC0_IB_SIZE
#define mmSDMA1_RLC0_SKIP_CNTL
#define mmSDMA1_RLC0_CONTEXT_STATUS
#define mmSDMA1_RLC0_DOORBELL
#define mmSDMA1_RLC0_VIRTUAL_ADDR
#define mmSDMA1_RLC0_APE1_CNTL
#define mmSDMA1_RLC0_DOORBELL_LOG
#define mmSDMA1_RLC0_WATERMARK
#define mmSDMA1_RLC0_CSA_ADDR_LO
#define mmSDMA1_RLC0_CSA_ADDR_HI
#define mmSDMA1_RLC0_IB_SUB_REMAIN
#define mmSDMA1_RLC0_PREEMPT
#define mmSDMA1_RLC0_DUMMY_REG
#define mmSDMA1_RLC0_MIDCMD_DATA0
#define mmSDMA1_RLC0_MIDCMD_DATA1
#define mmSDMA1_RLC0_MIDCMD_DATA2
#define mmSDMA1_RLC0_MIDCMD_DATA3
#define mmSDMA1_RLC0_MIDCMD_DATA4
#define mmSDMA1_RLC0_MIDCMD_DATA5
#define mmSDMA1_RLC0_MIDCMD_CNTL
#define mmSDMA1_RLC1_RB_CNTL
#define mmSDMA1_RLC1_RB_BASE
#define mmSDMA1_RLC1_RB_BASE_HI
#define mmSDMA1_RLC1_RB_RPTR
#define mmSDMA1_RLC1_RB_WPTR
#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL
#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI
#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO
#define mmSDMA1_RLC1_IB_CNTL
#define mmSDMA1_RLC1_IB_RPTR
#define mmSDMA1_RLC1_IB_OFFSET
#define mmSDMA1_RLC1_IB_BASE_LO
#define mmSDMA1_RLC1_IB_BASE_HI
#define mmSDMA1_RLC1_IB_SIZE
#define mmSDMA1_RLC1_SKIP_CNTL
#define mmSDMA1_RLC1_CONTEXT_STATUS
#define mmSDMA1_RLC1_DOORBELL
#define mmSDMA1_RLC1_VIRTUAL_ADDR
#define mmSDMA1_RLC1_APE1_CNTL
#define mmSDMA1_RLC1_DOORBELL_LOG
#define mmSDMA1_RLC1_WATERMARK
#define mmSDMA1_RLC1_CSA_ADDR_LO
#define mmSDMA1_RLC1_CSA_ADDR_HI
#define mmSDMA1_RLC1_IB_SUB_REMAIN
#define mmSDMA1_RLC1_PREEMPT
#define mmSDMA1_RLC1_DUMMY_REG
#define mmSDMA1_RLC1_MIDCMD_DATA0
#define mmSDMA1_RLC1_MIDCMD_DATA1
#define mmSDMA1_RLC1_MIDCMD_DATA2
#define mmSDMA1_RLC1_MIDCMD_DATA3
#define mmSDMA1_RLC1_MIDCMD_DATA4
#define mmSDMA1_RLC1_MIDCMD_DATA5
#define mmSDMA1_RLC1_MIDCMD_CNTL
#define mmHDP_HOST_PATH_CNTL
#define mmHDP_NONSURFACE_BASE
#define mmHDP_NONSURFACE_INFO
#define mmHDP_NONSURFACE_SIZE
#define mmHDP_NONSURF_FLAGS
#define mmHDP_NONSURF_FLAGS_CLR
#define mmHDP_SW_SEMAPHORE
#define mmHDP_DEBUG0
#define mmHDP_DEBUG1
#define mmHDP_LAST_SURFACE_HIT
#define mmHDP_TILING_CONFIG
#define mmHDP_SC_MULTI_CHIP_CNTL
#define mmHDP_OUTSTANDING_REQ
#define mmHDP_ADDR_CONFIG
#define mmHDP_MISC_CNTL
#define mmHDP_MEM_POWER_LS
#define mmHDP_NONSURFACE_PREFETCH
#define mmHDP_MEMIO_CNTL
#define mmHDP_MEMIO_ADDR
#define mmHDP_MEMIO_STATUS
#define mmHDP_MEMIO_WR_DATA
#define mmHDP_MEMIO_RD_DATA
#define mmHDP_VF_ENABLE
#define mmHDP_XDP_DIRECT2HDP_FIRST
#define mmHDP_XDP_D2H_FLUSH
#define mmHDP_XDP_D2H_BAR_UPDATE
#define mmHDP_XDP_D2H_RSVD_3
#define mmHDP_XDP_D2H_RSVD_4
#define mmHDP_XDP_D2H_RSVD_5
#define mmHDP_XDP_D2H_RSVD_6
#define mmHDP_XDP_D2H_RSVD_7
#define mmHDP_XDP_D2H_RSVD_8
#define mmHDP_XDP_D2H_RSVD_9
#define mmHDP_XDP_D2H_RSVD_10
#define mmHDP_XDP_D2H_RSVD_11
#define mmHDP_XDP_D2H_RSVD_12
#define mmHDP_XDP_D2H_RSVD_13
#define mmHDP_XDP_D2H_RSVD_14
#define mmHDP_XDP_D2H_RSVD_15
#define mmHDP_XDP_D2H_RSVD_16
#define mmHDP_XDP_D2H_RSVD_17
#define mmHDP_XDP_D2H_RSVD_18
#define mmHDP_XDP_D2H_RSVD_19
#define mmHDP_XDP_D2H_RSVD_20
#define mmHDP_XDP_D2H_RSVD_21
#define mmHDP_XDP_D2H_RSVD_22
#define mmHDP_XDP_D2H_RSVD_23
#define mmHDP_XDP_D2H_RSVD_24
#define mmHDP_XDP_D2H_RSVD_25
#define mmHDP_XDP_D2H_RSVD_26
#define mmHDP_XDP_D2H_RSVD_27
#define mmHDP_XDP_D2H_RSVD_28
#define mmHDP_XDP_D2H_RSVD_29
#define mmHDP_XDP_D2H_RSVD_30
#define mmHDP_XDP_D2H_RSVD_31
#define mmHDP_XDP_D2H_RSVD_32
#define mmHDP_XDP_D2H_RSVD_33
#define mmHDP_XDP_D2H_RSVD_34
#define mmHDP_XDP_DIRECT2HDP_LAST
#define mmHDP_XDP_P2P_BAR_CFG
#define mmHDP_XDP_P2P_MBX_OFFSET
#define mmHDP_XDP_P2P_MBX_ADDR0
#define mmHDP_XDP_P2P_MBX_ADDR1
#define mmHDP_XDP_P2P_MBX_ADDR2
#define mmHDP_XDP_P2P_MBX_ADDR3
#define mmHDP_XDP_P2P_MBX_ADDR4
#define mmHDP_XDP_P2P_MBX_ADDR5
#define mmHDP_XDP_P2P_MBX_ADDR6
#define mmHDP_XDP_HDP_MBX_MC_CFG
#define mmHDP_XDP_HDP_MC_CFG
#define mmHDP_XDP_HST_CFG
#define mmHDP_XDP_SID_CFG
#define mmHDP_XDP_HDP_IPH_CFG
#define mmHDP_XDP_SRBM_CFG
#define mmHDP_XDP_CGTT_BLK_CTRL
#define mmHDP_XDP_P2P_BAR0
#define mmHDP_XDP_P2P_BAR1
#define mmHDP_XDP_P2P_BAR2
#define mmHDP_XDP_P2P_BAR3
#define mmHDP_XDP_P2P_BAR4
#define mmHDP_XDP_P2P_BAR5
#define mmHDP_XDP_P2P_BAR6
#define mmHDP_XDP_P2P_BAR7
#define mmHDP_XDP_FLUSH_ARMED_STS
#define mmHDP_XDP_FLUSH_CNTR0_STS
#define mmHDP_XDP_BUSY_STS
#define mmHDP_XDP_STICKY
#define mmHDP_XDP_CHKN
#define mmHDP_XDP_DBG_ADDR
#define mmHDP_XDP_DBG_DATA
#define mmHDP_XDP_DBG_MASK
#define mmHDP_XDP_BARS_ADDR_39_36

#endif /* OSS_3_0_D_H */