/* * Copyright (C) 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _gc_10_1_0_OFFSET_HEADER #define _gc_10_1_0_OFFSET_HEADER #define mmSQ_DEBUG_STS_GLOBAL … #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX … #define mmSQ_DEBUG_STS_GLOBAL2 … #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX … // addressBlock: gc_sdma0_sdma0dec // base address: 0x4980 #define mmSDMA0_DEC_START … #define mmSDMA0_DEC_START_BASE_IDX … #define mmSDMA0_PG_CNTL … #define mmSDMA0_PG_CNTL_BASE_IDX … #define mmSDMA0_PG_CTX_LO … #define mmSDMA0_PG_CTX_LO_BASE_IDX … #define mmSDMA0_PG_CTX_HI … #define mmSDMA0_PG_CTX_HI_BASE_IDX … #define mmSDMA0_PG_CTX_CNTL … #define mmSDMA0_PG_CTX_CNTL_BASE_IDX … #define mmSDMA0_POWER_CNTL … #define mmSDMA0_POWER_CNTL_BASE_IDX … #define mmSDMA0_CLK_CTRL … #define mmSDMA0_CLK_CTRL_BASE_IDX … #define mmSDMA0_CNTL … #define mmSDMA0_CNTL_BASE_IDX … #define mmSDMA0_CHICKEN_BITS … #define mmSDMA0_CHICKEN_BITS_BASE_IDX … #define mmSDMA0_GB_ADDR_CONFIG … #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX … #define mmSDMA0_GB_ADDR_CONFIG_READ … #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX … #define mmSDMA0_RB_RPTR_FETCH_HI … #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX … #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … #define mmSDMA0_RB_RPTR_FETCH … #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX … #define mmSDMA0_IB_OFFSET_FETCH … #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX … #define mmSDMA0_PROGRAM … #define mmSDMA0_PROGRAM_BASE_IDX … #define mmSDMA0_STATUS_REG … #define mmSDMA0_STATUS_REG_BASE_IDX … #define mmSDMA0_STATUS1_REG … #define mmSDMA0_STATUS1_REG_BASE_IDX … #define mmSDMA0_RD_BURST_CNTL … #define mmSDMA0_RD_BURST_CNTL_BASE_IDX … #define mmSDMA0_HBM_PAGE_CONFIG … #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX … #define mmSDMA0_UCODE_CHECKSUM … #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX … #define mmSDMA0_F32_CNTL … #define mmSDMA0_F32_CNTL_BASE_IDX … #define mmSDMA0_FREEZE … #define mmSDMA0_FREEZE_BASE_IDX … #define mmSDMA0_PHASE0_QUANTUM … #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX … #define mmSDMA0_PHASE1_QUANTUM … #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX … #define mmSDMA_POWER_GATING … #define mmSDMA_POWER_GATING_BASE_IDX … #define mmSDMA_PGFSM_CONFIG … #define mmSDMA_PGFSM_CONFIG_BASE_IDX … #define mmSDMA_PGFSM_WRITE … #define mmSDMA_PGFSM_WRITE_BASE_IDX … #define mmSDMA_PGFSM_READ … #define mmSDMA_PGFSM_READ_BASE_IDX … #define mmSDMA0_EDC_CONFIG … #define mmSDMA0_EDC_CONFIG_BASE_IDX … #define mmSDMA0_BA_THRESHOLD … #define mmSDMA0_BA_THRESHOLD_BASE_IDX … #define mmSDMA0_ID … #define mmSDMA0_ID_BASE_IDX … #define mmSDMA0_VERSION … #define mmSDMA0_VERSION_BASE_IDX … #define mmSDMA0_EDC_COUNTER … #define mmSDMA0_EDC_COUNTER_BASE_IDX … #define mmSDMA0_EDC_COUNTER_CLEAR … #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX … #define mmSDMA0_STATUS2_REG … #define mmSDMA0_STATUS2_REG_BASE_IDX … #define mmSDMA0_ATOMIC_CNTL … #define mmSDMA0_ATOMIC_CNTL_BASE_IDX … #define mmSDMA0_ATOMIC_PREOP_LO … #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX … #define mmSDMA0_ATOMIC_PREOP_HI … #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX … #define mmSDMA0_UTCL1_CNTL … #define mmSDMA0_UTCL1_CNTL_BASE_IDX … #define mmSDMA0_UTCL1_WATERMK … #define mmSDMA0_UTCL1_WATERMK_BASE_IDX … #define mmSDMA0_UTCL1_RD_STATUS … #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX … #define mmSDMA0_UTCL1_WR_STATUS … #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX … #define mmSDMA0_UTCL1_INV0 … #define mmSDMA0_UTCL1_INV0_BASE_IDX … #define mmSDMA0_UTCL1_INV1 … #define mmSDMA0_UTCL1_INV1_BASE_IDX … #define mmSDMA0_UTCL1_INV2 … #define mmSDMA0_UTCL1_INV2_BASE_IDX … #define mmSDMA0_UTCL1_RD_XNACK0 … #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX … #define mmSDMA0_UTCL1_RD_XNACK1 … #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX … #define mmSDMA0_UTCL1_WR_XNACK0 … #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX … #define mmSDMA0_UTCL1_WR_XNACK1 … #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX … #define mmSDMA0_UTCL1_TIMEOUT … #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX … #define mmSDMA0_UTCL1_PAGE … #define mmSDMA0_UTCL1_PAGE_BASE_IDX … #define mmSDMA0_POWER_CNTL_IDLE … #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX … #define mmSDMA0_RELAX_ORDERING_LUT … #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX … #define mmSDMA0_CHICKEN_BITS_2 … #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX … #define mmSDMA0_STATUS3_REG … #define mmSDMA0_STATUS3_REG_BASE_IDX … #define mmSDMA0_PHYSICAL_ADDR_LO … #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX … #define mmSDMA0_PHYSICAL_ADDR_HI … #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX … #define mmSDMA0_PHASE2_QUANTUM … #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX … #define mmSDMA0_ERROR_LOG … #define mmSDMA0_ERROR_LOG_BASE_IDX … #define mmSDMA0_PUB_DUMMY_REG0 … #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX … #define mmSDMA0_F32_COUNTER … #define mmSDMA0_F32_COUNTER_BASE_IDX … #define mmSDMA0_PERFMON_CNTL … #define mmSDMA0_PERFMON_CNTL_BASE_IDX … #define mmSDMA0_PERFCOUNTER0_RESULT … #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX … #define mmSDMA0_PERFCOUNTER1_RESULT … #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX … #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE … #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX … #define mmSDMA0_CRD_CNTL … #define mmSDMA0_CRD_CNTL_BASE_IDX … #define mmSDMA0_GPU_IOV_VIOLATION_LOG … #define mmSDMA0_AQL_STATUS … #define mmSDMA0_AQL_STATUS_BASE_IDX … #define mmSDMA0_EA_DBIT_ADDR_DATA … #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX … #define mmSDMA0_EA_DBIT_ADDR_INDEX … #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX … #define mmSDMA0_TLBI_GCR_CNTL … #define mmSDMA0_TLBI_GCR_CNTL_BASE_IDX … #define mmSDMA0_TILING_CONFIG … #define mmSDMA0_TILING_CONFIG_BASE_IDX … #define mmSDMA0_HASH … #define mmSDMA0_HASH_BASE_IDX … #define mmSDMA0_PERFCOUNTER0_SELECT … #define mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX … #define mmSDMA0_PERFCOUNTER0_SELECT1 … #define mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmSDMA0_PERFCOUNTER0_LO … #define mmSDMA0_PERFCOUNTER0_LO_BASE_IDX … #define mmSDMA0_PERFCOUNTER0_HI … #define mmSDMA0_PERFCOUNTER0_HI_BASE_IDX … #define mmSDMA0_PERFCOUNTER1_SELECT … #define mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX … #define mmSDMA0_PERFCOUNTER1_SELECT1 … #define mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmSDMA0_PERFCOUNTER1_LO … #define mmSDMA0_PERFCOUNTER1_LO_BASE_IDX … #define mmSDMA0_PERFCOUNTER1_HI … #define mmSDMA0_PERFCOUNTER1_HI_BASE_IDX … #define mmSDMA0_INT_STATUS … #define mmSDMA0_INT_STATUS_BASE_IDX … #define mmSDMA0_GPU_IOV_VIOLATION_LOG2 … #define mmSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX … #define mmSDMA0_HOLE_ADDR_LO … #define mmSDMA0_HOLE_ADDR_LO_BASE_IDX … #define mmSDMA0_HOLE_ADDR_HI … #define mmSDMA0_HOLE_ADDR_HI_BASE_IDX … #define mmSDMA0_GFX_RB_CNTL … #define mmSDMA0_GFX_RB_CNTL_BASE_IDX … #define mmSDMA0_GFX_RB_BASE … #define mmSDMA0_GFX_RB_BASE_BASE_IDX … #define mmSDMA0_GFX_RB_BASE_HI … #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX … #define mmSDMA0_GFX_RB_RPTR … #define mmSDMA0_GFX_RB_RPTR_BASE_IDX … #define mmSDMA0_GFX_RB_RPTR_HI … #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_GFX_RB_WPTR … #define mmSDMA0_GFX_RB_WPTR_BASE_IDX … #define mmSDMA0_GFX_RB_WPTR_HI … #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL … #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_GFX_RB_RPTR_ADDR_HI … #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_GFX_RB_RPTR_ADDR_LO … #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_GFX_IB_CNTL … #define mmSDMA0_GFX_IB_CNTL_BASE_IDX … #define mmSDMA0_GFX_IB_RPTR … #define mmSDMA0_GFX_IB_RPTR_BASE_IDX … #define mmSDMA0_GFX_IB_OFFSET … #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX … #define mmSDMA0_GFX_IB_BASE_LO … #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX … #define mmSDMA0_GFX_IB_BASE_HI … #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX … #define mmSDMA0_GFX_IB_SIZE … #define mmSDMA0_GFX_IB_SIZE_BASE_IDX … #define mmSDMA0_GFX_SKIP_CNTL … #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX … #define mmSDMA0_GFX_CONTEXT_STATUS … #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_GFX_DOORBELL … #define mmSDMA0_GFX_DOORBELL_BASE_IDX … #define mmSDMA0_GFX_CONTEXT_CNTL … #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX … #define mmSDMA0_GFX_STATUS … #define mmSDMA0_GFX_STATUS_BASE_IDX … #define mmSDMA0_GFX_DOORBELL_LOG … #define mmSDMA0_GFX_WATERMARK … #define mmSDMA0_GFX_WATERMARK_BASE_IDX … #define mmSDMA0_GFX_DOORBELL_OFFSET … #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_GFX_CSA_ADDR_LO … #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_GFX_CSA_ADDR_HI … #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_GFX_IB_SUB_REMAIN … #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_GFX_PREEMPT … #define mmSDMA0_GFX_PREEMPT_BASE_IDX … #define mmSDMA0_GFX_DUMMY_REG … #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX … #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_GFX_RB_AQL_CNTL … #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_GFX_MINOR_PTR_UPDATE … #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA0 … #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA1 … #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA2 … #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA3 … #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA4 … #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA5 … #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA6 … #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA7 … #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_DATA8 … #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_GFX_MIDCMD_CNTL … #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_PAGE_RB_CNTL … #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX … #define mmSDMA0_PAGE_RB_BASE … #define mmSDMA0_PAGE_RB_BASE_BASE_IDX … #define mmSDMA0_PAGE_RB_BASE_HI … #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX … #define mmSDMA0_PAGE_RB_RPTR … #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX … #define mmSDMA0_PAGE_RB_RPTR_HI … #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_PAGE_RB_WPTR … #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX … #define mmSDMA0_PAGE_RB_WPTR_HI … #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL … #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI … #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO … #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_PAGE_IB_CNTL … #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX … #define mmSDMA0_PAGE_IB_RPTR … #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX … #define mmSDMA0_PAGE_IB_OFFSET … #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX … #define mmSDMA0_PAGE_IB_BASE_LO … #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX … #define mmSDMA0_PAGE_IB_BASE_HI … #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX … #define mmSDMA0_PAGE_IB_SIZE … #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX … #define mmSDMA0_PAGE_SKIP_CNTL … #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX … #define mmSDMA0_PAGE_CONTEXT_STATUS … #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_PAGE_DOORBELL … #define mmSDMA0_PAGE_DOORBELL_BASE_IDX … #define mmSDMA0_PAGE_STATUS … #define mmSDMA0_PAGE_STATUS_BASE_IDX … #define mmSDMA0_PAGE_DOORBELL_LOG … #define mmSDMA0_PAGE_WATERMARK … #define mmSDMA0_PAGE_WATERMARK_BASE_IDX … #define mmSDMA0_PAGE_DOORBELL_OFFSET … #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_PAGE_CSA_ADDR_LO … #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_PAGE_CSA_ADDR_HI … #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_PAGE_IB_SUB_REMAIN … #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_PAGE_PREEMPT … #define mmSDMA0_PAGE_PREEMPT_BASE_IDX … #define mmSDMA0_PAGE_DUMMY_REG … #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX … #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_PAGE_RB_AQL_CNTL … #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_PAGE_MINOR_PTR_UPDATE … #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA0 … #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA1 … #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA2 … #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA3 … #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA4 … #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA5 … #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA6 … #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA7 … #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_DATA8 … #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_PAGE_MIDCMD_CNTL … #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_RLC0_RB_CNTL … #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX … #define mmSDMA0_RLC0_RB_BASE … #define mmSDMA0_RLC0_RB_BASE_BASE_IDX … #define mmSDMA0_RLC0_RB_BASE_HI … #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC0_RB_RPTR … #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX … #define mmSDMA0_RLC0_RB_RPTR_HI … #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_RLC0_RB_WPTR … #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX … #define mmSDMA0_RLC0_RB_WPTR_HI … #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL … #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI … #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO … #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC0_IB_CNTL … #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX … #define mmSDMA0_RLC0_IB_RPTR … #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX … #define mmSDMA0_RLC0_IB_OFFSET … #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX … #define mmSDMA0_RLC0_IB_BASE_LO … #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX … #define mmSDMA0_RLC0_IB_BASE_HI … #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC0_IB_SIZE … #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX … #define mmSDMA0_RLC0_SKIP_CNTL … #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX … #define mmSDMA0_RLC0_CONTEXT_STATUS … #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_RLC0_DOORBELL … #define mmSDMA0_RLC0_DOORBELL_BASE_IDX … #define mmSDMA0_RLC0_STATUS … #define mmSDMA0_RLC0_STATUS_BASE_IDX … #define mmSDMA0_RLC0_DOORBELL_LOG … #define mmSDMA0_RLC0_WATERMARK … #define mmSDMA0_RLC0_WATERMARK_BASE_IDX … #define mmSDMA0_RLC0_DOORBELL_OFFSET … #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_RLC0_CSA_ADDR_LO … #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC0_CSA_ADDR_HI … #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC0_IB_SUB_REMAIN … #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_RLC0_PREEMPT … #define mmSDMA0_RLC0_PREEMPT_BASE_IDX … #define mmSDMA0_RLC0_DUMMY_REG … #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX … #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC0_RB_AQL_CNTL … #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_RLC0_MINOR_PTR_UPDATE … #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA0 … #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA1 … #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA2 … #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA3 … #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA4 … #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA5 … #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA6 … #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA7 … #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_DATA8 … #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_RLC0_MIDCMD_CNTL … #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_RLC1_RB_CNTL … #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX … #define mmSDMA0_RLC1_RB_BASE … #define mmSDMA0_RLC1_RB_BASE_BASE_IDX … #define mmSDMA0_RLC1_RB_BASE_HI … #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC1_RB_RPTR … #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX … #define mmSDMA0_RLC1_RB_RPTR_HI … #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_RLC1_RB_WPTR … #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX … #define mmSDMA0_RLC1_RB_WPTR_HI … #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL … #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI … #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO … #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC1_IB_CNTL … #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX … #define mmSDMA0_RLC1_IB_RPTR … #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX … #define mmSDMA0_RLC1_IB_OFFSET … #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX … #define mmSDMA0_RLC1_IB_BASE_LO … #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX … #define mmSDMA0_RLC1_IB_BASE_HI … #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC1_IB_SIZE … #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX … #define mmSDMA0_RLC1_SKIP_CNTL … #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX … #define mmSDMA0_RLC1_CONTEXT_STATUS … #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_RLC1_DOORBELL … #define mmSDMA0_RLC1_DOORBELL_BASE_IDX … #define mmSDMA0_RLC1_STATUS … #define mmSDMA0_RLC1_STATUS_BASE_IDX … #define mmSDMA0_RLC1_DOORBELL_LOG … #define mmSDMA0_RLC1_WATERMARK … #define mmSDMA0_RLC1_WATERMARK_BASE_IDX … #define mmSDMA0_RLC1_DOORBELL_OFFSET … #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_RLC1_CSA_ADDR_LO … #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC1_CSA_ADDR_HI … #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC1_IB_SUB_REMAIN … #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_RLC1_PREEMPT … #define mmSDMA0_RLC1_PREEMPT_BASE_IDX … #define mmSDMA0_RLC1_DUMMY_REG … #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX … #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC1_RB_AQL_CNTL … #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_RLC1_MINOR_PTR_UPDATE … #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA0 … #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA1 … #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA2 … #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA3 … #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA4 … #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA5 … #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA6 … #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA7 … #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_DATA8 … #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_RLC1_MIDCMD_CNTL … #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_RLC2_RB_CNTL … #define mmSDMA0_RLC2_RB_CNTL_BASE_IDX … #define mmSDMA0_RLC2_RB_BASE … #define mmSDMA0_RLC2_RB_BASE_BASE_IDX … #define mmSDMA0_RLC2_RB_BASE_HI … #define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC2_RB_RPTR … #define mmSDMA0_RLC2_RB_RPTR_BASE_IDX … #define mmSDMA0_RLC2_RB_RPTR_HI … #define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_RLC2_RB_WPTR … #define mmSDMA0_RLC2_RB_WPTR_BASE_IDX … #define mmSDMA0_RLC2_RB_WPTR_HI … #define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL … #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI … #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO … #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC2_IB_CNTL … #define mmSDMA0_RLC2_IB_CNTL_BASE_IDX … #define mmSDMA0_RLC2_IB_RPTR … #define mmSDMA0_RLC2_IB_RPTR_BASE_IDX … #define mmSDMA0_RLC2_IB_OFFSET … #define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX … #define mmSDMA0_RLC2_IB_BASE_LO … #define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX … #define mmSDMA0_RLC2_IB_BASE_HI … #define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC2_IB_SIZE … #define mmSDMA0_RLC2_IB_SIZE_BASE_IDX … #define mmSDMA0_RLC2_SKIP_CNTL … #define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX … #define mmSDMA0_RLC2_CONTEXT_STATUS … #define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_RLC2_DOORBELL … #define mmSDMA0_RLC2_DOORBELL_BASE_IDX … #define mmSDMA0_RLC2_STATUS … #define mmSDMA0_RLC2_STATUS_BASE_IDX … #define mmSDMA0_RLC2_DOORBELL_LOG … #define mmSDMA0_RLC2_WATERMARK … #define mmSDMA0_RLC2_WATERMARK_BASE_IDX … #define mmSDMA0_RLC2_DOORBELL_OFFSET … #define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_RLC2_CSA_ADDR_LO … #define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC2_CSA_ADDR_HI … #define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC2_IB_SUB_REMAIN … #define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_RLC2_PREEMPT … #define mmSDMA0_RLC2_PREEMPT_BASE_IDX … #define mmSDMA0_RLC2_DUMMY_REG … #define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX … #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC2_RB_AQL_CNTL … #define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_RLC2_MINOR_PTR_UPDATE … #define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA0 … #define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA1 … #define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA2 … #define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA3 … #define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA4 … #define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA5 … #define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA6 … #define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA7 … #define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_DATA8 … #define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_RLC2_MIDCMD_CNTL … #define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_RLC3_RB_CNTL … #define mmSDMA0_RLC3_RB_CNTL_BASE_IDX … #define mmSDMA0_RLC3_RB_BASE … #define mmSDMA0_RLC3_RB_BASE_BASE_IDX … #define mmSDMA0_RLC3_RB_BASE_HI … #define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC3_RB_RPTR … #define mmSDMA0_RLC3_RB_RPTR_BASE_IDX … #define mmSDMA0_RLC3_RB_RPTR_HI … #define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_RLC3_RB_WPTR … #define mmSDMA0_RLC3_RB_WPTR_BASE_IDX … #define mmSDMA0_RLC3_RB_WPTR_HI … #define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL … #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI … #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO … #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC3_IB_CNTL … #define mmSDMA0_RLC3_IB_CNTL_BASE_IDX … #define mmSDMA0_RLC3_IB_RPTR … #define mmSDMA0_RLC3_IB_RPTR_BASE_IDX … #define mmSDMA0_RLC3_IB_OFFSET … #define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX … #define mmSDMA0_RLC3_IB_BASE_LO … #define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX … #define mmSDMA0_RLC3_IB_BASE_HI … #define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC3_IB_SIZE … #define mmSDMA0_RLC3_IB_SIZE_BASE_IDX … #define mmSDMA0_RLC3_SKIP_CNTL … #define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX … #define mmSDMA0_RLC3_CONTEXT_STATUS … #define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_RLC3_DOORBELL … #define mmSDMA0_RLC3_DOORBELL_BASE_IDX … #define mmSDMA0_RLC3_STATUS … #define mmSDMA0_RLC3_STATUS_BASE_IDX … #define mmSDMA0_RLC3_DOORBELL_LOG … #define mmSDMA0_RLC3_WATERMARK … #define mmSDMA0_RLC3_WATERMARK_BASE_IDX … #define mmSDMA0_RLC3_DOORBELL_OFFSET … #define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_RLC3_CSA_ADDR_LO … #define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC3_CSA_ADDR_HI … #define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC3_IB_SUB_REMAIN … #define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_RLC3_PREEMPT … #define mmSDMA0_RLC3_PREEMPT_BASE_IDX … #define mmSDMA0_RLC3_DUMMY_REG … #define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX … #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC3_RB_AQL_CNTL … #define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_RLC3_MINOR_PTR_UPDATE … #define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA0 … #define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA1 … #define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA2 … #define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA3 … #define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA4 … #define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA5 … #define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA6 … #define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA7 … #define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_DATA8 … #define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_RLC3_MIDCMD_CNTL … #define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_RLC4_RB_CNTL … #define mmSDMA0_RLC4_RB_CNTL_BASE_IDX … #define mmSDMA0_RLC4_RB_BASE … #define mmSDMA0_RLC4_RB_BASE_BASE_IDX … #define mmSDMA0_RLC4_RB_BASE_HI … #define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC4_RB_RPTR … #define mmSDMA0_RLC4_RB_RPTR_BASE_IDX … #define mmSDMA0_RLC4_RB_RPTR_HI … #define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_RLC4_RB_WPTR … #define mmSDMA0_RLC4_RB_WPTR_BASE_IDX … #define mmSDMA0_RLC4_RB_WPTR_HI … #define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL … #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI … #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO … #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC4_IB_CNTL … #define mmSDMA0_RLC4_IB_CNTL_BASE_IDX … #define mmSDMA0_RLC4_IB_RPTR … #define mmSDMA0_RLC4_IB_RPTR_BASE_IDX … #define mmSDMA0_RLC4_IB_OFFSET … #define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX … #define mmSDMA0_RLC4_IB_BASE_LO … #define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX … #define mmSDMA0_RLC4_IB_BASE_HI … #define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC4_IB_SIZE … #define mmSDMA0_RLC4_IB_SIZE_BASE_IDX … #define mmSDMA0_RLC4_SKIP_CNTL … #define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX … #define mmSDMA0_RLC4_CONTEXT_STATUS … #define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_RLC4_DOORBELL … #define mmSDMA0_RLC4_DOORBELL_BASE_IDX … #define mmSDMA0_RLC4_STATUS … #define mmSDMA0_RLC4_STATUS_BASE_IDX … #define mmSDMA0_RLC4_DOORBELL_LOG … #define mmSDMA0_RLC4_WATERMARK … #define mmSDMA0_RLC4_WATERMARK_BASE_IDX … #define mmSDMA0_RLC4_DOORBELL_OFFSET … #define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_RLC4_CSA_ADDR_LO … #define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC4_CSA_ADDR_HI … #define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC4_IB_SUB_REMAIN … #define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_RLC4_PREEMPT … #define mmSDMA0_RLC4_PREEMPT_BASE_IDX … #define mmSDMA0_RLC4_DUMMY_REG … #define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX … #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC4_RB_AQL_CNTL … #define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_RLC4_MINOR_PTR_UPDATE … #define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA0 … #define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA1 … #define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA2 … #define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA3 … #define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA4 … #define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA5 … #define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA6 … #define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA7 … #define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_DATA8 … #define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_RLC4_MIDCMD_CNTL … #define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_RLC5_RB_CNTL … #define mmSDMA0_RLC5_RB_CNTL_BASE_IDX … #define mmSDMA0_RLC5_RB_BASE … #define mmSDMA0_RLC5_RB_BASE_BASE_IDX … #define mmSDMA0_RLC5_RB_BASE_HI … #define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC5_RB_RPTR … #define mmSDMA0_RLC5_RB_RPTR_BASE_IDX … #define mmSDMA0_RLC5_RB_RPTR_HI … #define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_RLC5_RB_WPTR … #define mmSDMA0_RLC5_RB_WPTR_BASE_IDX … #define mmSDMA0_RLC5_RB_WPTR_HI … #define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL … #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI … #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO … #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC5_IB_CNTL … #define mmSDMA0_RLC5_IB_CNTL_BASE_IDX … #define mmSDMA0_RLC5_IB_RPTR … #define mmSDMA0_RLC5_IB_RPTR_BASE_IDX … #define mmSDMA0_RLC5_IB_OFFSET … #define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX … #define mmSDMA0_RLC5_IB_BASE_LO … #define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX … #define mmSDMA0_RLC5_IB_BASE_HI … #define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC5_IB_SIZE … #define mmSDMA0_RLC5_IB_SIZE_BASE_IDX … #define mmSDMA0_RLC5_SKIP_CNTL … #define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX … #define mmSDMA0_RLC5_CONTEXT_STATUS … #define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_RLC5_DOORBELL … #define mmSDMA0_RLC5_DOORBELL_BASE_IDX … #define mmSDMA0_RLC5_STATUS … #define mmSDMA0_RLC5_STATUS_BASE_IDX … #define mmSDMA0_RLC5_DOORBELL_LOG … #define mmSDMA0_RLC5_WATERMARK … #define mmSDMA0_RLC5_WATERMARK_BASE_IDX … #define mmSDMA0_RLC5_DOORBELL_OFFSET … #define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_RLC5_CSA_ADDR_LO … #define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC5_CSA_ADDR_HI … #define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC5_IB_SUB_REMAIN … #define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_RLC5_PREEMPT … #define mmSDMA0_RLC5_PREEMPT_BASE_IDX … #define mmSDMA0_RLC5_DUMMY_REG … #define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX … #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC5_RB_AQL_CNTL … #define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_RLC5_MINOR_PTR_UPDATE … #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA0 … #define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA1 … #define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA2 … #define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA3 … #define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA4 … #define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA5 … #define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA6 … #define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA7 … #define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_DATA8 … #define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_RLC5_MIDCMD_CNTL … #define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_RLC6_RB_CNTL … #define mmSDMA0_RLC6_RB_CNTL_BASE_IDX … #define mmSDMA0_RLC6_RB_BASE … #define mmSDMA0_RLC6_RB_BASE_BASE_IDX … #define mmSDMA0_RLC6_RB_BASE_HI … #define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC6_RB_RPTR … #define mmSDMA0_RLC6_RB_RPTR_BASE_IDX … #define mmSDMA0_RLC6_RB_RPTR_HI … #define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_RLC6_RB_WPTR … #define mmSDMA0_RLC6_RB_WPTR_BASE_IDX … #define mmSDMA0_RLC6_RB_WPTR_HI … #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL … #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI … #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO … #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC6_IB_CNTL … #define mmSDMA0_RLC6_IB_CNTL_BASE_IDX … #define mmSDMA0_RLC6_IB_RPTR … #define mmSDMA0_RLC6_IB_RPTR_BASE_IDX … #define mmSDMA0_RLC6_IB_OFFSET … #define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX … #define mmSDMA0_RLC6_IB_BASE_LO … #define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX … #define mmSDMA0_RLC6_IB_BASE_HI … #define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC6_IB_SIZE … #define mmSDMA0_RLC6_IB_SIZE_BASE_IDX … #define mmSDMA0_RLC6_SKIP_CNTL … #define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX … #define mmSDMA0_RLC6_CONTEXT_STATUS … #define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_RLC6_DOORBELL … #define mmSDMA0_RLC6_DOORBELL_BASE_IDX … #define mmSDMA0_RLC6_STATUS … #define mmSDMA0_RLC6_STATUS_BASE_IDX … #define mmSDMA0_RLC6_DOORBELL_LOG … #define mmSDMA0_RLC6_WATERMARK … #define mmSDMA0_RLC6_WATERMARK_BASE_IDX … #define mmSDMA0_RLC6_DOORBELL_OFFSET … #define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_RLC6_CSA_ADDR_LO … #define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC6_CSA_ADDR_HI … #define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC6_IB_SUB_REMAIN … #define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_RLC6_PREEMPT … #define mmSDMA0_RLC6_PREEMPT_BASE_IDX … #define mmSDMA0_RLC6_DUMMY_REG … #define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX … #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC6_RB_AQL_CNTL … #define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_RLC6_MINOR_PTR_UPDATE … #define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA0 … #define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA1 … #define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA2 … #define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA3 … #define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA4 … #define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA5 … #define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA6 … #define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA7 … #define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_DATA8 … #define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_RLC6_MIDCMD_CNTL … #define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX … #define mmSDMA0_RLC7_RB_CNTL … #define mmSDMA0_RLC7_RB_CNTL_BASE_IDX … #define mmSDMA0_RLC7_RB_BASE … #define mmSDMA0_RLC7_RB_BASE_BASE_IDX … #define mmSDMA0_RLC7_RB_BASE_HI … #define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC7_RB_RPTR … #define mmSDMA0_RLC7_RB_RPTR_BASE_IDX … #define mmSDMA0_RLC7_RB_RPTR_HI … #define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX … #define mmSDMA0_RLC7_RB_WPTR … #define mmSDMA0_RLC7_RB_WPTR_BASE_IDX … #define mmSDMA0_RLC7_RB_WPTR_HI … #define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX … #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL … #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI … #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO … #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC7_IB_CNTL … #define mmSDMA0_RLC7_IB_CNTL_BASE_IDX … #define mmSDMA0_RLC7_IB_RPTR … #define mmSDMA0_RLC7_IB_RPTR_BASE_IDX … #define mmSDMA0_RLC7_IB_OFFSET … #define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX … #define mmSDMA0_RLC7_IB_BASE_LO … #define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX … #define mmSDMA0_RLC7_IB_BASE_HI … #define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX … #define mmSDMA0_RLC7_IB_SIZE … #define mmSDMA0_RLC7_IB_SIZE_BASE_IDX … #define mmSDMA0_RLC7_SKIP_CNTL … #define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX … #define mmSDMA0_RLC7_CONTEXT_STATUS … #define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX … #define mmSDMA0_RLC7_DOORBELL … #define mmSDMA0_RLC7_DOORBELL_BASE_IDX … #define mmSDMA0_RLC7_STATUS … #define mmSDMA0_RLC7_STATUS_BASE_IDX … #define mmSDMA0_RLC7_DOORBELL_LOG … #define mmSDMA0_RLC7_WATERMARK … #define mmSDMA0_RLC7_WATERMARK_BASE_IDX … #define mmSDMA0_RLC7_DOORBELL_OFFSET … #define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA0_RLC7_CSA_ADDR_LO … #define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC7_CSA_ADDR_HI … #define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC7_IB_SUB_REMAIN … #define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA0_RLC7_PREEMPT … #define mmSDMA0_RLC7_PREEMPT_BASE_IDX … #define mmSDMA0_RLC7_DUMMY_REG … #define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX … #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI … #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO … #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA0_RLC7_RB_AQL_CNTL … #define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX … #define mmSDMA0_RLC7_MINOR_PTR_UPDATE … #define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA0 … #define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA1 … #define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA2 … #define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA3 … #define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA4 … #define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA5 … #define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA6 … #define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA7 … #define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_DATA8 … #define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX … #define mmSDMA0_RLC7_MIDCMD_CNTL … #define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX … // addressBlock: gc_sdma1_sdma1dec // base address: 0x6180 #define mmSDMA1_DEC_START … #define mmSDMA1_DEC_START_BASE_IDX … #define mmSDMA1_PG_CNTL … #define mmSDMA1_PG_CNTL_BASE_IDX … #define mmSDMA1_PG_CTX_LO … #define mmSDMA1_PG_CTX_LO_BASE_IDX … #define mmSDMA1_PG_CTX_HI … #define mmSDMA1_PG_CTX_HI_BASE_IDX … #define mmSDMA1_PG_CTX_CNTL … #define mmSDMA1_PG_CTX_CNTL_BASE_IDX … #define mmSDMA1_POWER_CNTL … #define mmSDMA1_POWER_CNTL_BASE_IDX … #define mmSDMA1_CLK_CTRL … #define mmSDMA1_CLK_CTRL_BASE_IDX … #define mmSDMA1_CNTL … #define mmSDMA1_CNTL_BASE_IDX … #define mmSDMA1_CHICKEN_BITS … #define mmSDMA1_CHICKEN_BITS_BASE_IDX … #define mmSDMA1_GB_ADDR_CONFIG … #define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX … #define mmSDMA1_GB_ADDR_CONFIG_READ … #define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX … #define mmSDMA1_RB_RPTR_FETCH_HI … #define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX … #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL … #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … #define mmSDMA1_RB_RPTR_FETCH … #define mmSDMA1_RB_RPTR_FETCH_BASE_IDX … #define mmSDMA1_IB_OFFSET_FETCH … #define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX … #define mmSDMA1_PROGRAM … #define mmSDMA1_PROGRAM_BASE_IDX … #define mmSDMA1_STATUS_REG … #define mmSDMA1_STATUS_REG_BASE_IDX … #define mmSDMA1_STATUS1_REG … #define mmSDMA1_STATUS1_REG_BASE_IDX … #define mmSDMA1_RD_BURST_CNTL … #define mmSDMA1_RD_BURST_CNTL_BASE_IDX … #define mmSDMA1_HBM_PAGE_CONFIG … #define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX … #define mmSDMA1_UCODE_CHECKSUM … #define mmSDMA1_UCODE_CHECKSUM_BASE_IDX … #define mmSDMA1_F32_CNTL … #define mmSDMA1_F32_CNTL_BASE_IDX … #define mmSDMA1_FREEZE … #define mmSDMA1_FREEZE_BASE_IDX … #define mmSDMA1_PHASE0_QUANTUM … #define mmSDMA1_PHASE0_QUANTUM_BASE_IDX … #define mmSDMA1_PHASE1_QUANTUM … #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX … #define mmSDMA1_EDC_CONFIG … #define mmSDMA1_EDC_CONFIG_BASE_IDX … #define mmSDMA1_BA_THRESHOLD … #define mmSDMA1_BA_THRESHOLD_BASE_IDX … #define mmSDMA1_ID … #define mmSDMA1_ID_BASE_IDX … #define mmSDMA1_VERSION … #define mmSDMA1_VERSION_BASE_IDX … #define mmSDMA1_EDC_COUNTER … #define mmSDMA1_EDC_COUNTER_BASE_IDX … #define mmSDMA1_EDC_COUNTER_CLEAR … #define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX … #define mmSDMA1_STATUS2_REG … #define mmSDMA1_STATUS2_REG_BASE_IDX … #define mmSDMA1_ATOMIC_CNTL … #define mmSDMA1_ATOMIC_CNTL_BASE_IDX … #define mmSDMA1_ATOMIC_PREOP_LO … #define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX … #define mmSDMA1_ATOMIC_PREOP_HI … #define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX … #define mmSDMA1_UTCL1_CNTL … #define mmSDMA1_UTCL1_CNTL_BASE_IDX … #define mmSDMA1_UTCL1_WATERMK … #define mmSDMA1_UTCL1_WATERMK_BASE_IDX … #define mmSDMA1_UTCL1_RD_STATUS … #define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX … #define mmSDMA1_UTCL1_WR_STATUS … #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX … #define mmSDMA1_UTCL1_INV0 … #define mmSDMA1_UTCL1_INV0_BASE_IDX … #define mmSDMA1_UTCL1_INV1 … #define mmSDMA1_UTCL1_INV1_BASE_IDX … #define mmSDMA1_UTCL1_INV2 … #define mmSDMA1_UTCL1_INV2_BASE_IDX … #define mmSDMA1_UTCL1_RD_XNACK0 … #define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX … #define mmSDMA1_UTCL1_RD_XNACK1 … #define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX … #define mmSDMA1_UTCL1_WR_XNACK0 … #define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX … #define mmSDMA1_UTCL1_WR_XNACK1 … #define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX … #define mmSDMA1_UTCL1_TIMEOUT … #define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX … #define mmSDMA1_UTCL1_PAGE … #define mmSDMA1_UTCL1_PAGE_BASE_IDX … #define mmSDMA1_POWER_CNTL_IDLE … #define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX … #define mmSDMA1_RELAX_ORDERING_LUT … #define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX … #define mmSDMA1_CHICKEN_BITS_2 … #define mmSDMA1_CHICKEN_BITS_2_BASE_IDX … #define mmSDMA1_STATUS3_REG … #define mmSDMA1_STATUS3_REG_BASE_IDX … #define mmSDMA1_PHYSICAL_ADDR_LO … #define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX … #define mmSDMA1_PHYSICAL_ADDR_HI … #define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX … #define mmSDMA1_PHASE2_QUANTUM … #define mmSDMA1_PHASE2_QUANTUM_BASE_IDX … #define mmSDMA1_ERROR_LOG … #define mmSDMA1_ERROR_LOG_BASE_IDX … #define mmSDMA1_PUB_DUMMY_REG0 … #define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX … #define mmSDMA1_F32_COUNTER … #define mmSDMA1_F32_COUNTER_BASE_IDX … #define mmSDMA1_PERFMON_CNTL … #define mmSDMA1_PERFMON_CNTL_BASE_IDX … #define mmSDMA1_PERFCOUNTER0_RESULT … #define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX … #define mmSDMA1_PERFCOUNTER1_RESULT … #define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX … #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE … #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX … #define mmSDMA1_CRD_CNTL … #define mmSDMA1_CRD_CNTL_BASE_IDX … #define mmSDMA1_GPU_IOV_VIOLATION_LOG … #define mmSDMA1_AQL_STATUS … #define mmSDMA1_AQL_STATUS_BASE_IDX … #define mmSDMA1_EA_DBIT_ADDR_DATA … #define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX … #define mmSDMA1_EA_DBIT_ADDR_INDEX … #define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX … #define mmSDMA1_TLBI_GCR_CNTL … #define mmSDMA1_TLBI_GCR_CNTL_BASE_IDX … #define mmSDMA1_TILING_CONFIG … #define mmSDMA1_TILING_CONFIG_BASE_IDX … #define mmSDMA1_HASH … #define mmSDMA1_HASH_BASE_IDX … #define mmSDMA1_PERFCOUNTER0_SELECT … #define mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX … #define mmSDMA1_PERFCOUNTER0_SELECT1 … #define mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmSDMA1_PERFCOUNTER0_LO … #define mmSDMA1_PERFCOUNTER0_LO_BASE_IDX … #define mmSDMA1_PERFCOUNTER0_HI … #define mmSDMA1_PERFCOUNTER0_HI_BASE_IDX … #define mmSDMA1_PERFCOUNTER1_SELECT … #define mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX … #define mmSDMA1_PERFCOUNTER1_SELECT1 … #define mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmSDMA1_PERFCOUNTER1_LO … #define mmSDMA1_PERFCOUNTER1_LO_BASE_IDX … #define mmSDMA1_PERFCOUNTER1_HI … #define mmSDMA1_PERFCOUNTER1_HI_BASE_IDX … #define mmSDMA1_INT_STATUS … #define mmSDMA1_INT_STATUS_BASE_IDX … #define mmSDMA1_GPU_IOV_VIOLATION_LOG2 … #define mmSDMA1_GPU_IOV_VIOLATION_LOG2_BASE_IDX … #define mmSDMA1_HOLE_ADDR_LO … #define mmSDMA1_HOLE_ADDR_LO_BASE_IDX … #define mmSDMA1_HOLE_ADDR_HI … #define mmSDMA1_HOLE_ADDR_HI_BASE_IDX … #define mmSDMA1_GFX_RB_CNTL … #define mmSDMA1_GFX_RB_CNTL_BASE_IDX … #define mmSDMA1_GFX_RB_BASE … #define mmSDMA1_GFX_RB_BASE_BASE_IDX … #define mmSDMA1_GFX_RB_BASE_HI … #define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX … #define mmSDMA1_GFX_RB_RPTR … #define mmSDMA1_GFX_RB_RPTR_BASE_IDX … #define mmSDMA1_GFX_RB_RPTR_HI … #define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_GFX_RB_WPTR … #define mmSDMA1_GFX_RB_WPTR_BASE_IDX … #define mmSDMA1_GFX_RB_WPTR_HI … #define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL … #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_GFX_RB_RPTR_ADDR_HI … #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_GFX_RB_RPTR_ADDR_LO … #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_GFX_IB_CNTL … #define mmSDMA1_GFX_IB_CNTL_BASE_IDX … #define mmSDMA1_GFX_IB_RPTR … #define mmSDMA1_GFX_IB_RPTR_BASE_IDX … #define mmSDMA1_GFX_IB_OFFSET … #define mmSDMA1_GFX_IB_OFFSET_BASE_IDX … #define mmSDMA1_GFX_IB_BASE_LO … #define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX … #define mmSDMA1_GFX_IB_BASE_HI … #define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX … #define mmSDMA1_GFX_IB_SIZE … #define mmSDMA1_GFX_IB_SIZE_BASE_IDX … #define mmSDMA1_GFX_SKIP_CNTL … #define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX … #define mmSDMA1_GFX_CONTEXT_STATUS … #define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_GFX_DOORBELL … #define mmSDMA1_GFX_DOORBELL_BASE_IDX … #define mmSDMA1_GFX_CONTEXT_CNTL … #define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX … #define mmSDMA1_GFX_STATUS … #define mmSDMA1_GFX_STATUS_BASE_IDX … #define mmSDMA1_GFX_DOORBELL_LOG … #define mmSDMA1_GFX_WATERMARK … #define mmSDMA1_GFX_WATERMARK_BASE_IDX … #define mmSDMA1_GFX_DOORBELL_OFFSET … #define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_GFX_CSA_ADDR_LO … #define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_GFX_CSA_ADDR_HI … #define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_GFX_IB_SUB_REMAIN … #define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_GFX_PREEMPT … #define mmSDMA1_GFX_PREEMPT_BASE_IDX … #define mmSDMA1_GFX_DUMMY_REG … #define mmSDMA1_GFX_DUMMY_REG_BASE_IDX … #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_GFX_RB_AQL_CNTL … #define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_GFX_MINOR_PTR_UPDATE … #define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA0 … #define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA1 … #define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA2 … #define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA3 … #define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA4 … #define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA5 … #define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA6 … #define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA7 … #define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_DATA8 … #define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_GFX_MIDCMD_CNTL … #define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_PAGE_RB_CNTL … #define mmSDMA1_PAGE_RB_CNTL_BASE_IDX … #define mmSDMA1_PAGE_RB_BASE … #define mmSDMA1_PAGE_RB_BASE_BASE_IDX … #define mmSDMA1_PAGE_RB_BASE_HI … #define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX … #define mmSDMA1_PAGE_RB_RPTR … #define mmSDMA1_PAGE_RB_RPTR_BASE_IDX … #define mmSDMA1_PAGE_RB_RPTR_HI … #define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_PAGE_RB_WPTR … #define mmSDMA1_PAGE_RB_WPTR_BASE_IDX … #define mmSDMA1_PAGE_RB_WPTR_HI … #define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL … #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI … #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO … #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_PAGE_IB_CNTL … #define mmSDMA1_PAGE_IB_CNTL_BASE_IDX … #define mmSDMA1_PAGE_IB_RPTR … #define mmSDMA1_PAGE_IB_RPTR_BASE_IDX … #define mmSDMA1_PAGE_IB_OFFSET … #define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX … #define mmSDMA1_PAGE_IB_BASE_LO … #define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX … #define mmSDMA1_PAGE_IB_BASE_HI … #define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX … #define mmSDMA1_PAGE_IB_SIZE … #define mmSDMA1_PAGE_IB_SIZE_BASE_IDX … #define mmSDMA1_PAGE_SKIP_CNTL … #define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX … #define mmSDMA1_PAGE_CONTEXT_STATUS … #define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_PAGE_DOORBELL … #define mmSDMA1_PAGE_DOORBELL_BASE_IDX … #define mmSDMA1_PAGE_STATUS … #define mmSDMA1_PAGE_STATUS_BASE_IDX … #define mmSDMA1_PAGE_DOORBELL_LOG … #define mmSDMA1_PAGE_WATERMARK … #define mmSDMA1_PAGE_WATERMARK_BASE_IDX … #define mmSDMA1_PAGE_DOORBELL_OFFSET … #define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_PAGE_CSA_ADDR_LO … #define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_PAGE_CSA_ADDR_HI … #define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_PAGE_IB_SUB_REMAIN … #define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_PAGE_PREEMPT … #define mmSDMA1_PAGE_PREEMPT_BASE_IDX … #define mmSDMA1_PAGE_DUMMY_REG … #define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX … #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_PAGE_RB_AQL_CNTL … #define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_PAGE_MINOR_PTR_UPDATE … #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA0 … #define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA1 … #define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA2 … #define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA3 … #define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA4 … #define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA5 … #define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA6 … #define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA7 … #define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_DATA8 … #define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_PAGE_MIDCMD_CNTL … #define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_RLC0_RB_CNTL … #define mmSDMA1_RLC0_RB_CNTL_BASE_IDX … #define mmSDMA1_RLC0_RB_BASE … #define mmSDMA1_RLC0_RB_BASE_BASE_IDX … #define mmSDMA1_RLC0_RB_BASE_HI … #define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC0_RB_RPTR … #define mmSDMA1_RLC0_RB_RPTR_BASE_IDX … #define mmSDMA1_RLC0_RB_RPTR_HI … #define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_RLC0_RB_WPTR … #define mmSDMA1_RLC0_RB_WPTR_BASE_IDX … #define mmSDMA1_RLC0_RB_WPTR_HI … #define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL … #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI … #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO … #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC0_IB_CNTL … #define mmSDMA1_RLC0_IB_CNTL_BASE_IDX … #define mmSDMA1_RLC0_IB_RPTR … #define mmSDMA1_RLC0_IB_RPTR_BASE_IDX … #define mmSDMA1_RLC0_IB_OFFSET … #define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX … #define mmSDMA1_RLC0_IB_BASE_LO … #define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX … #define mmSDMA1_RLC0_IB_BASE_HI … #define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC0_IB_SIZE … #define mmSDMA1_RLC0_IB_SIZE_BASE_IDX … #define mmSDMA1_RLC0_SKIP_CNTL … #define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX … #define mmSDMA1_RLC0_CONTEXT_STATUS … #define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_RLC0_DOORBELL … #define mmSDMA1_RLC0_DOORBELL_BASE_IDX … #define mmSDMA1_RLC0_STATUS … #define mmSDMA1_RLC0_STATUS_BASE_IDX … #define mmSDMA1_RLC0_DOORBELL_LOG … #define mmSDMA1_RLC0_WATERMARK … #define mmSDMA1_RLC0_WATERMARK_BASE_IDX … #define mmSDMA1_RLC0_DOORBELL_OFFSET … #define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_RLC0_CSA_ADDR_LO … #define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC0_CSA_ADDR_HI … #define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC0_IB_SUB_REMAIN … #define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_RLC0_PREEMPT … #define mmSDMA1_RLC0_PREEMPT_BASE_IDX … #define mmSDMA1_RLC0_DUMMY_REG … #define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX … #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC0_RB_AQL_CNTL … #define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_RLC0_MINOR_PTR_UPDATE … #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA0 … #define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA1 … #define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA2 … #define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA3 … #define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA4 … #define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA5 … #define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA6 … #define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA7 … #define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_DATA8 … #define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_RLC0_MIDCMD_CNTL … #define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_RLC1_RB_CNTL … #define mmSDMA1_RLC1_RB_CNTL_BASE_IDX … #define mmSDMA1_RLC1_RB_BASE … #define mmSDMA1_RLC1_RB_BASE_BASE_IDX … #define mmSDMA1_RLC1_RB_BASE_HI … #define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC1_RB_RPTR … #define mmSDMA1_RLC1_RB_RPTR_BASE_IDX … #define mmSDMA1_RLC1_RB_RPTR_HI … #define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_RLC1_RB_WPTR … #define mmSDMA1_RLC1_RB_WPTR_BASE_IDX … #define mmSDMA1_RLC1_RB_WPTR_HI … #define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL … #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI … #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO … #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC1_IB_CNTL … #define mmSDMA1_RLC1_IB_CNTL_BASE_IDX … #define mmSDMA1_RLC1_IB_RPTR … #define mmSDMA1_RLC1_IB_RPTR_BASE_IDX … #define mmSDMA1_RLC1_IB_OFFSET … #define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX … #define mmSDMA1_RLC1_IB_BASE_LO … #define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX … #define mmSDMA1_RLC1_IB_BASE_HI … #define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC1_IB_SIZE … #define mmSDMA1_RLC1_IB_SIZE_BASE_IDX … #define mmSDMA1_RLC1_SKIP_CNTL … #define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX … #define mmSDMA1_RLC1_CONTEXT_STATUS … #define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_RLC1_DOORBELL … #define mmSDMA1_RLC1_DOORBELL_BASE_IDX … #define mmSDMA1_RLC1_STATUS … #define mmSDMA1_RLC1_STATUS_BASE_IDX … #define mmSDMA1_RLC1_DOORBELL_LOG … #define mmSDMA1_RLC1_WATERMARK … #define mmSDMA1_RLC1_WATERMARK_BASE_IDX … #define mmSDMA1_RLC1_DOORBELL_OFFSET … #define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_RLC1_CSA_ADDR_LO … #define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC1_CSA_ADDR_HI … #define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC1_IB_SUB_REMAIN … #define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_RLC1_PREEMPT … #define mmSDMA1_RLC1_PREEMPT_BASE_IDX … #define mmSDMA1_RLC1_DUMMY_REG … #define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX … #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC1_RB_AQL_CNTL … #define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_RLC1_MINOR_PTR_UPDATE … #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA0 … #define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA1 … #define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA2 … #define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA3 … #define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA4 … #define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA5 … #define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA6 … #define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA7 … #define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_DATA8 … #define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_RLC1_MIDCMD_CNTL … #define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_RLC2_RB_CNTL … #define mmSDMA1_RLC2_RB_CNTL_BASE_IDX … #define mmSDMA1_RLC2_RB_BASE … #define mmSDMA1_RLC2_RB_BASE_BASE_IDX … #define mmSDMA1_RLC2_RB_BASE_HI … #define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC2_RB_RPTR … #define mmSDMA1_RLC2_RB_RPTR_BASE_IDX … #define mmSDMA1_RLC2_RB_RPTR_HI … #define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_RLC2_RB_WPTR … #define mmSDMA1_RLC2_RB_WPTR_BASE_IDX … #define mmSDMA1_RLC2_RB_WPTR_HI … #define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL … #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI … #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO … #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC2_IB_CNTL … #define mmSDMA1_RLC2_IB_CNTL_BASE_IDX … #define mmSDMA1_RLC2_IB_RPTR … #define mmSDMA1_RLC2_IB_RPTR_BASE_IDX … #define mmSDMA1_RLC2_IB_OFFSET … #define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX … #define mmSDMA1_RLC2_IB_BASE_LO … #define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX … #define mmSDMA1_RLC2_IB_BASE_HI … #define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC2_IB_SIZE … #define mmSDMA1_RLC2_IB_SIZE_BASE_IDX … #define mmSDMA1_RLC2_SKIP_CNTL … #define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX … #define mmSDMA1_RLC2_CONTEXT_STATUS … #define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_RLC2_DOORBELL … #define mmSDMA1_RLC2_DOORBELL_BASE_IDX … #define mmSDMA1_RLC2_STATUS … #define mmSDMA1_RLC2_STATUS_BASE_IDX … #define mmSDMA1_RLC2_DOORBELL_LOG … #define mmSDMA1_RLC2_WATERMARK … #define mmSDMA1_RLC2_WATERMARK_BASE_IDX … #define mmSDMA1_RLC2_DOORBELL_OFFSET … #define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_RLC2_CSA_ADDR_LO … #define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC2_CSA_ADDR_HI … #define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC2_IB_SUB_REMAIN … #define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_RLC2_PREEMPT … #define mmSDMA1_RLC2_PREEMPT_BASE_IDX … #define mmSDMA1_RLC2_DUMMY_REG … #define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX … #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC2_RB_AQL_CNTL … #define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_RLC2_MINOR_PTR_UPDATE … #define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA0 … #define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA1 … #define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA2 … #define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA3 … #define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA4 … #define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA5 … #define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA6 … #define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA7 … #define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_DATA8 … #define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_RLC2_MIDCMD_CNTL … #define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_RLC3_RB_CNTL … #define mmSDMA1_RLC3_RB_CNTL_BASE_IDX … #define mmSDMA1_RLC3_RB_BASE … #define mmSDMA1_RLC3_RB_BASE_BASE_IDX … #define mmSDMA1_RLC3_RB_BASE_HI … #define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC3_RB_RPTR … #define mmSDMA1_RLC3_RB_RPTR_BASE_IDX … #define mmSDMA1_RLC3_RB_RPTR_HI … #define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_RLC3_RB_WPTR … #define mmSDMA1_RLC3_RB_WPTR_BASE_IDX … #define mmSDMA1_RLC3_RB_WPTR_HI … #define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL … #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI … #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO … #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC3_IB_CNTL … #define mmSDMA1_RLC3_IB_CNTL_BASE_IDX … #define mmSDMA1_RLC3_IB_RPTR … #define mmSDMA1_RLC3_IB_RPTR_BASE_IDX … #define mmSDMA1_RLC3_IB_OFFSET … #define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX … #define mmSDMA1_RLC3_IB_BASE_LO … #define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX … #define mmSDMA1_RLC3_IB_BASE_HI … #define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC3_IB_SIZE … #define mmSDMA1_RLC3_IB_SIZE_BASE_IDX … #define mmSDMA1_RLC3_SKIP_CNTL … #define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX … #define mmSDMA1_RLC3_CONTEXT_STATUS … #define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_RLC3_DOORBELL … #define mmSDMA1_RLC3_DOORBELL_BASE_IDX … #define mmSDMA1_RLC3_STATUS … #define mmSDMA1_RLC3_STATUS_BASE_IDX … #define mmSDMA1_RLC3_DOORBELL_LOG … #define mmSDMA1_RLC3_WATERMARK … #define mmSDMA1_RLC3_WATERMARK_BASE_IDX … #define mmSDMA1_RLC3_DOORBELL_OFFSET … #define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_RLC3_CSA_ADDR_LO … #define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC3_CSA_ADDR_HI … #define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC3_IB_SUB_REMAIN … #define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_RLC3_PREEMPT … #define mmSDMA1_RLC3_PREEMPT_BASE_IDX … #define mmSDMA1_RLC3_DUMMY_REG … #define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX … #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC3_RB_AQL_CNTL … #define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_RLC3_MINOR_PTR_UPDATE … #define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA0 … #define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA1 … #define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA2 … #define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA3 … #define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA4 … #define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA5 … #define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA6 … #define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA7 … #define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_DATA8 … #define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_RLC3_MIDCMD_CNTL … #define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_RLC4_RB_CNTL … #define mmSDMA1_RLC4_RB_CNTL_BASE_IDX … #define mmSDMA1_RLC4_RB_BASE … #define mmSDMA1_RLC4_RB_BASE_BASE_IDX … #define mmSDMA1_RLC4_RB_BASE_HI … #define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC4_RB_RPTR … #define mmSDMA1_RLC4_RB_RPTR_BASE_IDX … #define mmSDMA1_RLC4_RB_RPTR_HI … #define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_RLC4_RB_WPTR … #define mmSDMA1_RLC4_RB_WPTR_BASE_IDX … #define mmSDMA1_RLC4_RB_WPTR_HI … #define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL … #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI … #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO … #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC4_IB_CNTL … #define mmSDMA1_RLC4_IB_CNTL_BASE_IDX … #define mmSDMA1_RLC4_IB_RPTR … #define mmSDMA1_RLC4_IB_RPTR_BASE_IDX … #define mmSDMA1_RLC4_IB_OFFSET … #define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX … #define mmSDMA1_RLC4_IB_BASE_LO … #define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX … #define mmSDMA1_RLC4_IB_BASE_HI … #define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC4_IB_SIZE … #define mmSDMA1_RLC4_IB_SIZE_BASE_IDX … #define mmSDMA1_RLC4_SKIP_CNTL … #define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX … #define mmSDMA1_RLC4_CONTEXT_STATUS … #define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_RLC4_DOORBELL … #define mmSDMA1_RLC4_DOORBELL_BASE_IDX … #define mmSDMA1_RLC4_STATUS … #define mmSDMA1_RLC4_STATUS_BASE_IDX … #define mmSDMA1_RLC4_DOORBELL_LOG … #define mmSDMA1_RLC4_WATERMARK … #define mmSDMA1_RLC4_WATERMARK_BASE_IDX … #define mmSDMA1_RLC4_DOORBELL_OFFSET … #define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_RLC4_CSA_ADDR_LO … #define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC4_CSA_ADDR_HI … #define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC4_IB_SUB_REMAIN … #define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_RLC4_PREEMPT … #define mmSDMA1_RLC4_PREEMPT_BASE_IDX … #define mmSDMA1_RLC4_DUMMY_REG … #define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX … #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC4_RB_AQL_CNTL … #define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_RLC4_MINOR_PTR_UPDATE … #define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA0 … #define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA1 … #define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA2 … #define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA3 … #define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA4 … #define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA5 … #define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA6 … #define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA7 … #define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_DATA8 … #define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_RLC4_MIDCMD_CNTL … #define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_RLC5_RB_CNTL … #define mmSDMA1_RLC5_RB_CNTL_BASE_IDX … #define mmSDMA1_RLC5_RB_BASE … #define mmSDMA1_RLC5_RB_BASE_BASE_IDX … #define mmSDMA1_RLC5_RB_BASE_HI … #define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC5_RB_RPTR … #define mmSDMA1_RLC5_RB_RPTR_BASE_IDX … #define mmSDMA1_RLC5_RB_RPTR_HI … #define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_RLC5_RB_WPTR … #define mmSDMA1_RLC5_RB_WPTR_BASE_IDX … #define mmSDMA1_RLC5_RB_WPTR_HI … #define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL … #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI … #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO … #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC5_IB_CNTL … #define mmSDMA1_RLC5_IB_CNTL_BASE_IDX … #define mmSDMA1_RLC5_IB_RPTR … #define mmSDMA1_RLC5_IB_RPTR_BASE_IDX … #define mmSDMA1_RLC5_IB_OFFSET … #define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX … #define mmSDMA1_RLC5_IB_BASE_LO … #define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX … #define mmSDMA1_RLC5_IB_BASE_HI … #define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC5_IB_SIZE … #define mmSDMA1_RLC5_IB_SIZE_BASE_IDX … #define mmSDMA1_RLC5_SKIP_CNTL … #define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX … #define mmSDMA1_RLC5_CONTEXT_STATUS … #define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_RLC5_DOORBELL … #define mmSDMA1_RLC5_DOORBELL_BASE_IDX … #define mmSDMA1_RLC5_STATUS … #define mmSDMA1_RLC5_STATUS_BASE_IDX … #define mmSDMA1_RLC5_DOORBELL_LOG … #define mmSDMA1_RLC5_WATERMARK … #define mmSDMA1_RLC5_WATERMARK_BASE_IDX … #define mmSDMA1_RLC5_DOORBELL_OFFSET … #define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_RLC5_CSA_ADDR_LO … #define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC5_CSA_ADDR_HI … #define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC5_IB_SUB_REMAIN … #define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_RLC5_PREEMPT … #define mmSDMA1_RLC5_PREEMPT_BASE_IDX … #define mmSDMA1_RLC5_DUMMY_REG … #define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX … #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC5_RB_AQL_CNTL … #define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_RLC5_MINOR_PTR_UPDATE … #define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA0 … #define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA1 … #define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA2 … #define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA3 … #define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA4 … #define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA5 … #define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA6 … #define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA7 … #define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_DATA8 … #define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_RLC5_MIDCMD_CNTL … #define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_RLC6_RB_CNTL … #define mmSDMA1_RLC6_RB_CNTL_BASE_IDX … #define mmSDMA1_RLC6_RB_BASE … #define mmSDMA1_RLC6_RB_BASE_BASE_IDX … #define mmSDMA1_RLC6_RB_BASE_HI … #define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC6_RB_RPTR … #define mmSDMA1_RLC6_RB_RPTR_BASE_IDX … #define mmSDMA1_RLC6_RB_RPTR_HI … #define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_RLC6_RB_WPTR … #define mmSDMA1_RLC6_RB_WPTR_BASE_IDX … #define mmSDMA1_RLC6_RB_WPTR_HI … #define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL … #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI … #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO … #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC6_IB_CNTL … #define mmSDMA1_RLC6_IB_CNTL_BASE_IDX … #define mmSDMA1_RLC6_IB_RPTR … #define mmSDMA1_RLC6_IB_RPTR_BASE_IDX … #define mmSDMA1_RLC6_IB_OFFSET … #define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX … #define mmSDMA1_RLC6_IB_BASE_LO … #define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX … #define mmSDMA1_RLC6_IB_BASE_HI … #define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC6_IB_SIZE … #define mmSDMA1_RLC6_IB_SIZE_BASE_IDX … #define mmSDMA1_RLC6_SKIP_CNTL … #define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX … #define mmSDMA1_RLC6_CONTEXT_STATUS … #define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_RLC6_DOORBELL … #define mmSDMA1_RLC6_DOORBELL_BASE_IDX … #define mmSDMA1_RLC6_STATUS … #define mmSDMA1_RLC6_STATUS_BASE_IDX … #define mmSDMA1_RLC6_DOORBELL_LOG … #define mmSDMA1_RLC6_WATERMARK … #define mmSDMA1_RLC6_WATERMARK_BASE_IDX … #define mmSDMA1_RLC6_DOORBELL_OFFSET … #define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_RLC6_CSA_ADDR_LO … #define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC6_CSA_ADDR_HI … #define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC6_IB_SUB_REMAIN … #define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_RLC6_PREEMPT … #define mmSDMA1_RLC6_PREEMPT_BASE_IDX … #define mmSDMA1_RLC6_DUMMY_REG … #define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX … #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC6_RB_AQL_CNTL … #define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_RLC6_MINOR_PTR_UPDATE … #define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA0 … #define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA1 … #define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA2 … #define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA3 … #define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA4 … #define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA5 … #define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA6 … #define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA7 … #define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_DATA8 … #define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_RLC6_MIDCMD_CNTL … #define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX … #define mmSDMA1_RLC7_RB_CNTL … #define mmSDMA1_RLC7_RB_CNTL_BASE_IDX … #define mmSDMA1_RLC7_RB_BASE … #define mmSDMA1_RLC7_RB_BASE_BASE_IDX … #define mmSDMA1_RLC7_RB_BASE_HI … #define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC7_RB_RPTR … #define mmSDMA1_RLC7_RB_RPTR_BASE_IDX … #define mmSDMA1_RLC7_RB_RPTR_HI … #define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX … #define mmSDMA1_RLC7_RB_WPTR … #define mmSDMA1_RLC7_RB_WPTR_BASE_IDX … #define mmSDMA1_RLC7_RB_WPTR_HI … #define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX … #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL … #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI … #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO … #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC7_IB_CNTL … #define mmSDMA1_RLC7_IB_CNTL_BASE_IDX … #define mmSDMA1_RLC7_IB_RPTR … #define mmSDMA1_RLC7_IB_RPTR_BASE_IDX … #define mmSDMA1_RLC7_IB_OFFSET … #define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX … #define mmSDMA1_RLC7_IB_BASE_LO … #define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX … #define mmSDMA1_RLC7_IB_BASE_HI … #define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX … #define mmSDMA1_RLC7_IB_SIZE … #define mmSDMA1_RLC7_IB_SIZE_BASE_IDX … #define mmSDMA1_RLC7_SKIP_CNTL … #define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX … #define mmSDMA1_RLC7_CONTEXT_STATUS … #define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX … #define mmSDMA1_RLC7_DOORBELL … #define mmSDMA1_RLC7_DOORBELL_BASE_IDX … #define mmSDMA1_RLC7_STATUS … #define mmSDMA1_RLC7_STATUS_BASE_IDX … #define mmSDMA1_RLC7_DOORBELL_LOG … #define mmSDMA1_RLC7_WATERMARK … #define mmSDMA1_RLC7_WATERMARK_BASE_IDX … #define mmSDMA1_RLC7_DOORBELL_OFFSET … #define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX … #define mmSDMA1_RLC7_CSA_ADDR_LO … #define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC7_CSA_ADDR_HI … #define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC7_IB_SUB_REMAIN … #define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX … #define mmSDMA1_RLC7_PREEMPT … #define mmSDMA1_RLC7_PREEMPT_BASE_IDX … #define mmSDMA1_RLC7_DUMMY_REG … #define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX … #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI … #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO … #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmSDMA1_RLC7_RB_AQL_CNTL … #define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX … #define mmSDMA1_RLC7_MINOR_PTR_UPDATE … #define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA0 … #define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA1 … #define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA2 … #define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA3 … #define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA4 … #define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA5 … #define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA6 … #define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA7 … #define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_DATA8 … #define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX … #define mmSDMA1_RLC7_MIDCMD_CNTL … #define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX … // addressBlock: gc_grbmdec // base address: 0x8000 #define mmGRBM_CNTL … #define mmGRBM_CNTL_BASE_IDX … #define mmGRBM_SKEW_CNTL … #define mmGRBM_SKEW_CNTL_BASE_IDX … #define mmGRBM_STATUS2 … #define mmGRBM_STATUS2_BASE_IDX … #define mmGRBM_PWR_CNTL … #define mmGRBM_PWR_CNTL_BASE_IDX … #define mmGRBM_STATUS … #define mmGRBM_STATUS_BASE_IDX … #define mmGRBM_STATUS_SE0 … #define mmGRBM_STATUS_SE0_BASE_IDX … #define mmGRBM_STATUS_SE1 … #define mmGRBM_STATUS_SE1_BASE_IDX … #define mmGRBM_STATUS3 … #define mmGRBM_STATUS3_BASE_IDX … #define mmGRBM_SOFT_RESET … #define mmGRBM_SOFT_RESET_BASE_IDX … #define mmGRBM_GFX_CLKEN_CNTL … #define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX … #define mmGRBM_WAIT_IDLE_CLOCKS … #define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX … #define mmGRBM_STATUS_SE2 … #define mmGRBM_STATUS_SE2_BASE_IDX … #define mmGRBM_STATUS_SE3 … #define mmGRBM_STATUS_SE3_BASE_IDX … #define mmGRBM_PM_CNTL … #define mmGRBM_PM_CNTL_BASE_IDX … #define mmGRBM_READ_ERROR … #define mmGRBM_READ_ERROR_BASE_IDX … #define mmGRBM_READ_ERROR2 … #define mmGRBM_READ_ERROR2_BASE_IDX … #define mmGRBM_INT_CNTL … #define mmGRBM_INT_CNTL_BASE_IDX … #define mmGRBM_TRAP_OP … #define mmGRBM_TRAP_OP_BASE_IDX … #define mmGRBM_TRAP_ADDR … #define mmGRBM_TRAP_ADDR_BASE_IDX … #define mmGRBM_TRAP_ADDR_MSK … #define mmGRBM_TRAP_ADDR_MSK_BASE_IDX … #define mmGRBM_TRAP_WD … #define mmGRBM_TRAP_WD_BASE_IDX … #define mmGRBM_TRAP_WD_MSK … #define mmGRBM_TRAP_WD_MSK_BASE_IDX … #define mmGRBM_DSM_BYPASS … #define mmGRBM_DSM_BYPASS_BASE_IDX … #define mmGRBM_WRITE_ERROR … #define mmGRBM_WRITE_ERROR_BASE_IDX … #define mmGRBM_IOV_ERROR … #define mmGRBM_IOV_ERROR_BASE_IDX … #define mmGRBM_CHIP_REVISION … #define mmGRBM_CHIP_REVISION_BASE_IDX … #define mmGRBM_GFX_CNTL … #define mmGRBM_GFX_CNTL_BASE_IDX … #define mmGRBM_IH_CREDIT … #define mmGRBM_IH_CREDIT_BASE_IDX … #define mmGRBM_PWR_CNTL2 … #define mmGRBM_PWR_CNTL2_BASE_IDX … #define mmGRBM_UTCL2_INVAL_RANGE_START … #define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX … #define mmGRBM_UTCL2_INVAL_RANGE_END … #define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX … #define mmGRBM_IOV_READ_ERROR … #define mmGRBM_IOV_READ_ERROR_BASE_IDX … #define mmGRBM_FENCE_RANGE0 … #define mmGRBM_FENCE_RANGE0_BASE_IDX … #define mmGRBM_FENCE_RANGE1 … #define mmGRBM_FENCE_RANGE1_BASE_IDX … #define mmGRBM_NOWHERE … #define mmGRBM_NOWHERE_BASE_IDX … #define mmGRBM_SCRATCH_REG0 … #define mmGRBM_SCRATCH_REG0_BASE_IDX … #define mmGRBM_SCRATCH_REG1 … #define mmGRBM_SCRATCH_REG1_BASE_IDX … #define mmGRBM_SCRATCH_REG2 … #define mmGRBM_SCRATCH_REG2_BASE_IDX … #define mmGRBM_SCRATCH_REG3 … #define mmGRBM_SCRATCH_REG3_BASE_IDX … #define mmGRBM_SCRATCH_REG4 … #define mmGRBM_SCRATCH_REG4_BASE_IDX … #define mmGRBM_SCRATCH_REG5 … #define mmGRBM_SCRATCH_REG5_BASE_IDX … #define mmGRBM_SCRATCH_REG6 … #define mmGRBM_SCRATCH_REG6_BASE_IDX … #define mmGRBM_SCRATCH_REG7 … #define mmGRBM_SCRATCH_REG7_BASE_IDX … // addressBlock: gc_cpdec // base address: 0x8200 #define mmCP_CPC_STATUS … #define mmCP_CPC_STATUS_BASE_IDX … #define mmCP_CPC_BUSY_STAT … #define mmCP_CPC_BUSY_STAT_BASE_IDX … #define mmCP_CPC_STALLED_STAT1 … #define mmCP_CPC_STALLED_STAT1_BASE_IDX … #define mmCP_CPF_STATUS … #define mmCP_CPF_STATUS_BASE_IDX … #define mmCP_CPF_BUSY_STAT … #define mmCP_CPF_BUSY_STAT_BASE_IDX … #define mmCP_CPF_STALLED_STAT1 … #define mmCP_CPF_STALLED_STAT1_BASE_IDX … #define mmCP_CPC_BUSY_STAT2 … #define mmCP_CPC_BUSY_STAT2_BASE_IDX … #define mmCP_CPC_GRBM_FREE_COUNT … #define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX … #define mmCP_MEC_CNTL … #define mmCP_MEC_CNTL_BASE_IDX … #define mmCP_MEC_ME1_HEADER_DUMP … #define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX … #define mmCP_MEC_ME2_HEADER_DUMP … #define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX … #define mmCP_CPC_SCRATCH_INDEX … #define mmCP_CPC_SCRATCH_INDEX_BASE_IDX … #define mmCP_CPC_SCRATCH_DATA … #define mmCP_CPC_SCRATCH_DATA_BASE_IDX … #define mmCP_CPF_GRBM_FREE_COUNT … #define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX … #define mmCP_CPF_BUSY_STAT2 … #define mmCP_CPF_BUSY_STAT2_BASE_IDX … #define mmCP_CPC_HALT_HYST_COUNT … #define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX … #define mmCP_CE_COMPARE_COUNT … #define mmCP_CE_COMPARE_COUNT_BASE_IDX … #define mmCP_CE_DE_COUNT … #define mmCP_CE_DE_COUNT_BASE_IDX … #define mmCP_DE_CE_COUNT … #define mmCP_DE_CE_COUNT_BASE_IDX … #define mmCP_DE_LAST_INVAL_COUNT … #define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX … #define mmCP_DE_DE_COUNT … #define mmCP_DE_DE_COUNT_BASE_IDX … #define mmCP_STALLED_STAT3 … #define mmCP_STALLED_STAT3_BASE_IDX … #define mmCP_STALLED_STAT1 … #define mmCP_STALLED_STAT1_BASE_IDX … #define mmCP_STALLED_STAT2 … #define mmCP_STALLED_STAT2_BASE_IDX … #define mmCP_BUSY_STAT … #define mmCP_BUSY_STAT_BASE_IDX … #define mmCP_STAT … #define mmCP_STAT_BASE_IDX … #define mmCP_ME_HEADER_DUMP … #define mmCP_ME_HEADER_DUMP_BASE_IDX … #define mmCP_PFP_HEADER_DUMP … #define mmCP_PFP_HEADER_DUMP_BASE_IDX … #define mmCP_GRBM_FREE_COUNT … #define mmCP_GRBM_FREE_COUNT_BASE_IDX … #define mmCP_CE_HEADER_DUMP … #define mmCP_CE_HEADER_DUMP_BASE_IDX … #define mmCP_PFP_INSTR_PNTR … #define mmCP_PFP_INSTR_PNTR_BASE_IDX … #define mmCP_ME_INSTR_PNTR … #define mmCP_ME_INSTR_PNTR_BASE_IDX … #define mmCP_CE_INSTR_PNTR … #define mmCP_CE_INSTR_PNTR_BASE_IDX … #define mmCP_MEC1_INSTR_PNTR … #define mmCP_MEC1_INSTR_PNTR_BASE_IDX … #define mmCP_MEC2_INSTR_PNTR … #define mmCP_MEC2_INSTR_PNTR_BASE_IDX … #define mmCP_CSF_STAT … #define mmCP_CSF_STAT_BASE_IDX … #define mmCP_ME_CNTL … #define mmCP_ME_CNTL_BASE_IDX … #define mmCP_CNTX_STAT … #define mmCP_CNTX_STAT_BASE_IDX … #define mmCP_ME_PREEMPTION … #define mmCP_ME_PREEMPTION_BASE_IDX … #define mmCP_ROQ_THRESHOLDS … #define mmCP_ROQ_THRESHOLDS_BASE_IDX … #define mmCP_MEQ_STQ_THRESHOLD … #define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX … #define mmCP_RB2_RPTR … #define mmCP_RB2_RPTR_BASE_IDX … #define mmCP_RB1_RPTR … #define mmCP_RB1_RPTR_BASE_IDX … #define mmCP_RB0_RPTR … #define mmCP_RB0_RPTR_BASE_IDX … #define mmCP_RB_RPTR … #define mmCP_RB_RPTR_BASE_IDX … #define mmCP_RB_WPTR_DELAY … #define mmCP_RB_WPTR_DELAY_BASE_IDX … #define mmCP_RB_WPTR_POLL_CNTL … #define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX … #define mmCP_ROQ1_THRESHOLDS … #define mmCP_ROQ1_THRESHOLDS_BASE_IDX … #define mmCP_ROQ2_THRESHOLDS … #define mmCP_ROQ2_THRESHOLDS_BASE_IDX … #define mmCP_STQ_THRESHOLDS … #define mmCP_STQ_THRESHOLDS_BASE_IDX … #define mmCP_QUEUE_THRESHOLDS … #define mmCP_QUEUE_THRESHOLDS_BASE_IDX … #define mmCP_MEQ_THRESHOLDS … #define mmCP_MEQ_THRESHOLDS_BASE_IDX … #define mmCP_ROQ_AVAIL … #define mmCP_ROQ_AVAIL_BASE_IDX … #define mmCP_STQ_AVAIL … #define mmCP_STQ_AVAIL_BASE_IDX … #define mmCP_ROQ2_AVAIL … #define mmCP_ROQ2_AVAIL_BASE_IDX … #define mmCP_MEQ_AVAIL … #define mmCP_MEQ_AVAIL_BASE_IDX … #define mmCP_CMD_INDEX … #define mmCP_CMD_INDEX_BASE_IDX … #define mmCP_CMD_DATA … #define mmCP_CMD_DATA_BASE_IDX … #define mmCP_ROQ_RB_STAT … #define mmCP_ROQ_RB_STAT_BASE_IDX … #define mmCP_ROQ_IB1_STAT … #define mmCP_ROQ_IB1_STAT_BASE_IDX … #define mmCP_ROQ_IB2_STAT … #define mmCP_ROQ_IB2_STAT_BASE_IDX … #define mmCP_STQ_STAT … #define mmCP_STQ_STAT_BASE_IDX … #define mmCP_STQ_WR_STAT … #define mmCP_STQ_WR_STAT_BASE_IDX … #define mmCP_MEQ_STAT … #define mmCP_MEQ_STAT_BASE_IDX … #define mmCP_CEQ1_AVAIL … #define mmCP_CEQ1_AVAIL_BASE_IDX … #define mmCP_CEQ2_AVAIL … #define mmCP_CEQ2_AVAIL_BASE_IDX … #define mmCP_CE_ROQ_RB_STAT … #define mmCP_CE_ROQ_RB_STAT_BASE_IDX … #define mmCP_CE_ROQ_IB1_STAT … #define mmCP_CE_ROQ_IB1_STAT_BASE_IDX … #define mmCP_CE_ROQ_IB2_STAT … #define mmCP_CE_ROQ_IB2_STAT_BASE_IDX … #define mmCP_CE_ROQ_DB_STAT … #define mmCP_CE_ROQ_DB_STAT_BASE_IDX … #define mmCP_ROQ3_THRESHOLDS … #define mmCP_ROQ3_THRESHOLDS_BASE_IDX … #define mmCP_ROQ_DB_STAT … #define mmCP_ROQ_DB_STAT_BASE_IDX … // addressBlock: gc_padec // base address: 0x8800 #define mmVGT_VTX_VECT_EJECT_REG … #define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX … #define mmVGT_DMA_DATA_FIFO_DEPTH … #define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX … #define mmVGT_DMA_REQ_FIFO_DEPTH … #define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX … #define mmVGT_DRAW_INIT_FIFO_DEPTH … #define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX … #define mmVGT_LAST_COPY_STATE … #define mmVGT_LAST_COPY_STATE_BASE_IDX … #define mmVGT_CACHE_INVALIDATION … #define mmVGT_CACHE_INVALIDATION_BASE_IDX … #define mmVGT_ESGS_RING_SIZE … #define mmVGT_ESGS_RING_SIZE_BASE_IDX … #define mmVGT_GSVS_RING_SIZE … #define mmVGT_GSVS_RING_SIZE_BASE_IDX … #define mmVGT_FIFO_DEPTHS … #define mmVGT_FIFO_DEPTHS_BASE_IDX … #define mmVGT_GS_VERTEX_REUSE … #define mmVGT_GS_VERTEX_REUSE_BASE_IDX … #define mmVGT_MC_LAT_CNTL … #define mmVGT_MC_LAT_CNTL_BASE_IDX … #define mmIA_UTCL1_STATUS_2 … #define mmIA_UTCL1_STATUS_2_BASE_IDX … #define mmVGT_CNTL_STATUS … #define mmVGT_CNTL_STATUS_BASE_IDX … #define mmWD_CNTL_STATUS … #define mmWD_CNTL_STATUS_BASE_IDX … #define mmCC_GC_PRIM_CONFIG … #define mmCC_GC_PRIM_CONFIG_BASE_IDX … #define mmGC_USER_PRIM_CONFIG … #define mmGC_USER_PRIM_CONFIG_BASE_IDX … #define mmWD_QOS … #define mmWD_QOS_BASE_IDX … #define mmWD_UTCL1_CNTL … #define mmWD_UTCL1_CNTL_BASE_IDX … #define mmWD_UTCL1_STATUS … #define mmWD_UTCL1_STATUS_BASE_IDX … #define mmGE_PC_CNTL … #define mmGE_PC_CNTL_BASE_IDX … #define mmIA_UTCL1_CNTL … #define mmIA_UTCL1_CNTL_BASE_IDX … #define mmIA_UTCL1_STATUS … #define mmIA_UTCL1_STATUS_BASE_IDX … #define mmGE_FAST_CLKS … #define mmGE_FAST_CLKS_BASE_IDX … #define mmVGT_TF_RING_SIZE … #define mmVGT_TF_RING_SIZE_BASE_IDX … #define mmVGT_SYS_CONFIG … #define mmVGT_SYS_CONFIG_BASE_IDX … #define mmGE_PRIV_CONTROL … #define mmGE_PRIV_CONTROL_BASE_IDX … #define mmGE_STATUS … #define mmGE_STATUS_BASE_IDX … #define mmVGT_VS_MAX_WAVE_ID … #define mmVGT_VS_MAX_WAVE_ID_BASE_IDX … #define mmVGT_GS_MAX_WAVE_ID … #define mmVGT_GS_MAX_WAVE_ID_BASE_IDX … #define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0 … #define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX … #define mmVGT_HS_OFFCHIP_PARAM … #define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX … #define mmGFX_PIPE_CONTROL … #define mmGFX_PIPE_CONTROL_BASE_IDX … #define mmVGT_TF_MEMORY_BASE … #define mmVGT_TF_MEMORY_BASE_BASE_IDX … #define mmCC_GC_SHADER_ARRAY_CONFIG … #define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX … #define mmGC_USER_SHADER_ARRAY_CONFIG … #define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX … #define mmVGT_DMA_PRIMITIVE_TYPE … #define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX … #define mmVGT_DMA_CONTROL … #define mmVGT_DMA_CONTROL_BASE_IDX … #define mmVGT_DMA_LS_HS_CONFIG … #define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX … #define mmVGT_STRMOUT_DELAY … #define mmVGT_STRMOUT_DELAY_BASE_IDX … #define mmWD_BUF_RESOURCE_1 … #define mmWD_BUF_RESOURCE_1_BASE_IDX … #define mmWD_BUF_RESOURCE_2 … #define mmWD_BUF_RESOURCE_2_BASE_IDX … #define mmVGT_TF_MEMORY_BASE_HI … #define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX … #define mmPA_CL_CNTL_STATUS … #define mmPA_CL_CNTL_STATUS_BASE_IDX … #define mmPA_CL_ENHANCE … #define mmPA_CL_ENHANCE_BASE_IDX … #define mmPA_SU_CNTL_STATUS … #define mmPA_SU_CNTL_STATUS_BASE_IDX … #define mmPA_SC_FIFO_DEPTH_CNTL … #define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX … #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK … #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK … #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define mmPA_SC_TRAP_SCREEN_HV_LOCK … #define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define mmPA_SC_FORCE_EOV_MAX_CNTS … #define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX … #define mmPA_SC_BINNER_EVENT_CNTL_0 … #define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX … #define mmPA_SC_BINNER_EVENT_CNTL_1 … #define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX … #define mmPA_SC_BINNER_EVENT_CNTL_2 … #define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX … #define mmPA_SC_BINNER_EVENT_CNTL_3 … #define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX … #define mmPA_SC_BINNER_TIMEOUT_COUNTER … #define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX … #define mmPA_SC_BINNER_PERF_CNTL_0 … #define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX … #define mmPA_SC_BINNER_PERF_CNTL_1 … #define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX … #define mmPA_SC_BINNER_PERF_CNTL_2 … #define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX … #define mmPA_SC_BINNER_PERF_CNTL_3 … #define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX … #define mmPA_SC_ENHANCE_2 … #define mmPA_SC_ENHANCE_2_BASE_IDX … #define mmPA_SC_ENHANCE_INTERNAL … #define mmPA_SC_ENHANCE_INTERNAL_BASE_IDX … #define mmPA_SC_BINNER_CNTL_OVERRIDE … #define mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX … #define mmPA_SC_PBB_OVERRIDE_FLAG … #define mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX … #define mmPA_PH_INTERFACE_FIFO_SIZE … #define mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX … #define mmPA_PH_ENHANCE … #define mmPA_PH_ENHANCE_BASE_IDX … #define mmPA_SC_BC_WAVE_BREAK … #define mmPA_SC_BC_WAVE_BREAK_BASE_IDX … #define mmPA_SC_FIFO_SIZE … #define mmPA_SC_FIFO_SIZE_BASE_IDX … #define mmPA_SC_IF_FIFO_SIZE … #define mmPA_SC_IF_FIFO_SIZE_BASE_IDX … #define mmPA_SC_PKR_WAVE_TABLE_CNTL … #define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX … #define mmPA_SIDEBAND_REQUEST_DELAYS … #define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX … #define mmPA_SC_ENHANCE … #define mmPA_SC_ENHANCE_BASE_IDX … #define mmPA_SC_ENHANCE_1 … #define mmPA_SC_ENHANCE_1_BASE_IDX … #define mmPA_SC_DSM_CNTL … #define mmPA_SC_DSM_CNTL_BASE_IDX … #define mmPA_SC_TILE_STEERING_CREST_OVERRIDE … #define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX … // addressBlock: gc_sqdec // base address: 0x8c00 #define mmSQ_CONFIG … #define mmSQ_CONFIG_BASE_IDX … #define mmSQC_CONFIG … #define mmSQC_CONFIG_BASE_IDX … #define mmLDS_CONFIG … #define mmLDS_CONFIG_BASE_IDX … #define mmSQ_RANDOM_WAVE_PRI … #define mmSQ_RANDOM_WAVE_PRI_BASE_IDX … #define mmSQG_STATUS … #define mmSQG_STATUS_BASE_IDX … #define mmSQ_FIFO_SIZES … #define mmSQ_FIFO_SIZES_BASE_IDX … #define mmSQ_DSM_CNTL … #define mmSQ_DSM_CNTL_BASE_IDX … #define mmSQ_DSM_CNTL2 … #define mmSQ_DSM_CNTL2_BASE_IDX … #define mmSQ_RUNTIME_CONFIG … #define mmSQ_RUNTIME_CONFIG_BASE_IDX … #define mmSH_MEM_BASES … #define mmSH_MEM_BASES_BASE_IDX … #define mmSP_CONFIG … #define mmSP_CONFIG_BASE_IDX … #define mmSQ_ARB_CONFIG … #define mmSQ_ARB_CONFIG_BASE_IDX … #define mmSH_MEM_CONFIG … #define mmSH_MEM_CONFIG_BASE_IDX … #define mmCC_GC_SHADER_RATE_CONFIG … #define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX … #define mmGC_USER_SHADER_RATE_CONFIG … #define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX … #define mmSQ_INTERRUPT_AUTO_MASK … #define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX … #define mmSQ_INTERRUPT_MSG_CTRL … #define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX … #define mmSQG_UTCL0_CNTL1 … #define mmSQG_UTCL0_CNTL1_BASE_IDX … #define mmSQG_UTCL0_CNTL2 … #define mmSQG_UTCL0_CNTL2_BASE_IDX … #define mmSQG_UTCL0_STATUS … #define mmSQG_UTCL0_STATUS_BASE_IDX … #define mmSQG_CONFIG … #define mmSQG_CONFIG_BASE_IDX … #define mmSQ_SHADER_TBA_LO … #define mmSQ_SHADER_TBA_LO_BASE_IDX … #define mmSQ_SHADER_TBA_HI … #define mmSQ_SHADER_TBA_HI_BASE_IDX … #define mmSQ_SHADER_TMA_LO … #define mmSQ_SHADER_TMA_LO_BASE_IDX … #define mmSQ_SHADER_TMA_HI … #define mmSQ_SHADER_TMA_HI_BASE_IDX … #define mmSQ_WATCH0_ADDR_H … #define mmSQ_WATCH0_ADDR_H_BASE_IDX … #define mmSQ_WATCH0_ADDR_L … #define mmSQ_WATCH0_ADDR_L_BASE_IDX … #define mmSQ_WATCH0_CNTL … #define mmSQ_WATCH0_CNTL_BASE_IDX … #define mmSQ_WATCH1_ADDR_H … #define mmSQ_WATCH1_ADDR_H_BASE_IDX … #define mmSQ_WATCH1_ADDR_L … #define mmSQ_WATCH1_ADDR_L_BASE_IDX … #define mmSQ_WATCH1_CNTL … #define mmSQ_WATCH1_CNTL_BASE_IDX … #define mmSQ_WATCH2_ADDR_H … #define mmSQ_WATCH2_ADDR_H_BASE_IDX … #define mmSQ_WATCH2_ADDR_L … #define mmSQ_WATCH2_ADDR_L_BASE_IDX … #define mmSQ_WATCH2_CNTL … #define mmSQ_WATCH2_CNTL_BASE_IDX … #define mmSQ_WATCH3_ADDR_H … #define mmSQ_WATCH3_ADDR_H_BASE_IDX … #define mmSQ_WATCH3_ADDR_L … #define mmSQ_WATCH3_ADDR_L_BASE_IDX … #define mmSQ_WATCH3_CNTL … #define mmSQ_WATCH3_CNTL_BASE_IDX … #define mmSQ_THREAD_TRACE_BUF0_BASE … #define mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX … #define mmSQ_THREAD_TRACE_BUF0_SIZE … #define mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX … #define mmSQ_THREAD_TRACE_BUF1_BASE … #define mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX … #define mmSQ_THREAD_TRACE_BUF1_SIZE … #define mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX … #define mmSQ_THREAD_TRACE_WPTR … #define mmSQ_THREAD_TRACE_WPTR_BASE_IDX … #define mmSQ_THREAD_TRACE_MASK … #define mmSQ_THREAD_TRACE_MASK_BASE_IDX … #define mmSQ_THREAD_TRACE_TOKEN_MASK … #define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX … #define mmSQ_THREAD_TRACE_CTRL … #define mmSQ_THREAD_TRACE_CTRL_BASE_IDX … #define mmSQ_THREAD_TRACE_STATUS … #define mmSQ_THREAD_TRACE_STATUS_BASE_IDX … #define mmSQ_THREAD_TRACE_DROPPED_CNTR … #define mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX … #define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR … #define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX … #define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR … #define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX … #define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR … #define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX … #define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR … #define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX … #define mmSQ_IND_INDEX … #define mmSQ_IND_INDEX_BASE_IDX … #define mmSQ_IND_DATA … #define mmSQ_IND_DATA_BASE_IDX … #define mmSQ_CMD … #define mmSQ_CMD_BASE_IDX … #define mmSQ_TIME_HI … #define mmSQ_TIME_HI_BASE_IDX … #define mmSQ_TIME_LO … #define mmSQ_TIME_LO_BASE_IDX … #define mmSQ_LB_CTR_CTRL … #define mmSQ_LB_CTR_CTRL_BASE_IDX … #define mmSQ_LB_DATA0 … #define mmSQ_LB_DATA0_BASE_IDX … #define mmSQ_LB_DATA1 … #define mmSQ_LB_DATA1_BASE_IDX … #define mmSQ_LB_DATA2 … #define mmSQ_LB_DATA2_BASE_IDX … #define mmSQ_LB_DATA3 … #define mmSQ_LB_DATA3_BASE_IDX … #define mmSQ_LB_CTR_SEL0 … #define mmSQ_LB_CTR_SEL0_BASE_IDX … #define mmSQ_LB_CTR_SEL1 … #define mmSQ_LB_CTR_SEL1_BASE_IDX … #define mmSQ_EDC_CNT … #define mmSQ_EDC_CNT_BASE_IDX … #define mmSQ_EDC_FUE_CNTL … #define mmSQ_EDC_FUE_CNTL_BASE_IDX … #define mmSQ_WREXEC_EXEC_HI … #define mmSQ_WREXEC_EXEC_HI_BASE_IDX … #define mmSQ_WREXEC_EXEC_LO … #define mmSQ_WREXEC_EXEC_LO_BASE_IDX … #define mmSQC_ICACHE_UTCL0_CNTL1 … #define mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX … #define mmSQC_ICACHE_UTCL0_CNTL2 … #define mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX … #define mmSQC_DCACHE_UTCL0_CNTL1 … #define mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX … #define mmSQC_DCACHE_UTCL0_CNTL2 … #define mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX … #define mmSQC_ICACHE_UTCL0_STATUS … #define mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX … #define mmSQC_DCACHE_UTCL0_STATUS … #define mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX … #define mmSQC_MISC_CONFIG … #define mmSQC_MISC_CONFIG_BASE_IDX … // addressBlock: gc_shsdec // base address: 0x9000 #define mmSX_DEBUG_1 … #define mmSX_DEBUG_1_BASE_IDX … #define mmSPI_PS_MAX_WAVE_ID … #define mmSPI_PS_MAX_WAVE_ID_BASE_IDX … #define mmSPI_START_PHASE … #define mmSPI_START_PHASE_BASE_IDX … #define mmSPI_GFX_CNTL … #define mmSPI_GFX_CNTL_BASE_IDX … #define mmSPI_USER_ACCUM_VMID_CNTL … #define mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX … #define mmSPI_CONFIG_CNTL … #define mmSPI_CONFIG_CNTL_BASE_IDX … #define mmSPI_DSM_CNTL … #define mmSPI_DSM_CNTL_BASE_IDX … #define mmSPI_DSM_CNTL2 … #define mmSPI_DSM_CNTL2_BASE_IDX … #define mmSPI_EDC_CNT … #define mmSPI_EDC_CNT_BASE_IDX … #define mmSPI_WAVE_LIMIT_CNTL … #define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX … #define mmSPI_CONFIG_CNTL_2 … #define mmSPI_CONFIG_CNTL_2_BASE_IDX … #define mmSPI_CONFIG_CNTL_1 … #define mmSPI_CONFIG_CNTL_1_BASE_IDX … #define mmSPI_WF_LIFETIME_CNTL … #define mmSPI_WF_LIFETIME_CNTL_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_0 … #define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_1 … #define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_2 … #define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_3 … #define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_4 … #define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_5 … #define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_6 … #define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_7 … #define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_8 … #define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX … #define mmSPI_WF_LIFETIME_LIMIT_9 … #define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_0 … #define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_1 … #define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_2 … #define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_3 … #define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_4 … #define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_5 … #define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_6 … #define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_7 … #define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_8 … #define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_9 … #define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_10 … #define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_11 … #define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_12 … #define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_13 … #define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_14 … #define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_15 … #define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_16 … #define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_17 … #define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_18 … #define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_19 … #define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX … #define mmSPI_WF_LIFETIME_STATUS_20 … #define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX … #define mmSPI_LB_CTR_CTRL … #define mmSPI_LB_CTR_CTRL_BASE_IDX … #define mmSPI_LB_WGP_MASK … #define mmSPI_LB_WGP_MASK_BASE_IDX … #define mmSPI_LB_DATA_REG … #define mmSPI_LB_DATA_REG_BASE_IDX … #define mmSPI_PG_ENABLE_STATIC_WGP_MASK … #define mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX … #define mmSPI_GDS_CREDITS … #define mmSPI_GDS_CREDITS_BASE_IDX … #define mmSPI_SX_EXPORT_BUFFER_SIZES … #define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX … #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES … #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_STATUS … #define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_COUNT_0 … #define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_COUNT_1 … #define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_COUNT_2 … #define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_COUNT_3 … #define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_COUNT_4 … #define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_COUNT_5 … #define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_COUNT_6 … #define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX … #define mmSPI_CSQ_WF_ACTIVE_COUNT_7 … #define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX … #define mmSPI_LB_DATA_WAVES … #define mmSPI_LB_DATA_WAVES_BASE_IDX … #define mmSPI_LB_DATA_PERWGP_WAVE_HSGS … #define mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX … #define mmSPI_LB_DATA_PERWGP_WAVE_VSPS … #define mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX … #define mmSPI_LB_DATA_PERWGP_WAVE_CS … #define mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX … #define mmSPI_P0_TRAP_SCREEN_PSBA_LO … #define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX … #define mmSPI_P0_TRAP_SCREEN_PSBA_HI … #define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX … #define mmSPI_P0_TRAP_SCREEN_PSMA_LO … #define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX … #define mmSPI_P0_TRAP_SCREEN_PSMA_HI … #define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX … #define mmSPI_P0_TRAP_SCREEN_GPR_MIN … #define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX … #define mmSPI_P1_TRAP_SCREEN_PSBA_LO … #define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX … #define mmSPI_P1_TRAP_SCREEN_PSBA_HI … #define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX … #define mmSPI_P1_TRAP_SCREEN_PSMA_LO … #define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX … #define mmSPI_P1_TRAP_SCREEN_PSMA_HI … #define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX … #define mmSPI_P1_TRAP_SCREEN_GPR_MIN … #define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX … // addressBlock: gc_tpdec // base address: 0x9400 #define mmTD_CNTL … #define mmTD_CNTL_BASE_IDX … #define mmTD_STATUS … #define mmTD_STATUS_BASE_IDX … #define mmTD_POWER_CNTL … #define mmTD_POWER_CNTL_BASE_IDX … #define mmTD_DSM_CNTL … #define mmTD_DSM_CNTL_BASE_IDX … #define mmTD_DSM_CNTL2 … #define mmTD_DSM_CNTL2_BASE_IDX … #define mmTD_SCRATCH … #define mmTD_SCRATCH_BASE_IDX … #define mmTA_POWER_CNTL … #define mmTA_POWER_CNTL_BASE_IDX … #define mmTA_CNTL … #define mmTA_CNTL_BASE_IDX … #define mmTA_CNTL_AUX … #define mmTA_CNTL_AUX_BASE_IDX … #define mmTA_RESERVED_010C … #define mmTA_RESERVED_010C_BASE_IDX … #define mmTA_STATUS … #define mmTA_STATUS_BASE_IDX … #define mmTA_SCRATCH … #define mmTA_SCRATCH_BASE_IDX … // addressBlock: gc_gdsdec // base address: 0x9700 #define mmGDS_CONFIG … #define mmGDS_CONFIG_BASE_IDX … #define mmGDS_CNTL_STATUS … #define mmGDS_CNTL_STATUS_BASE_IDX … #define mmGDS_ENHANCE … #define mmGDS_ENHANCE_BASE_IDX … #define mmGDS_PROTECTION_FAULT … #define mmGDS_PROTECTION_FAULT_BASE_IDX … #define mmGDS_VM_PROTECTION_FAULT … #define mmGDS_VM_PROTECTION_FAULT_BASE_IDX … #define mmGDS_EDC_CNT … #define mmGDS_EDC_CNT_BASE_IDX … #define mmGDS_EDC_GRBM_CNT … #define mmGDS_EDC_GRBM_CNT_BASE_IDX … #define mmGDS_EDC_OA_DED … #define mmGDS_EDC_OA_DED_BASE_IDX … #define mmGDS_DSM_CNTL … #define mmGDS_DSM_CNTL_BASE_IDX … #define mmGDS_EDC_OA_PHY_CNT … #define mmGDS_EDC_OA_PHY_CNT_BASE_IDX … #define mmGDS_EDC_OA_PIPE_CNT … #define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX … #define mmGDS_DSM_CNTL2 … #define mmGDS_DSM_CNTL2_BASE_IDX … #define mmGDS_WD_GDS_CSB … #define mmGDS_WD_GDS_CSB_BASE_IDX … // addressBlock: gc_rbdec // base address: 0x9800 #define mmDB_DEBUG … #define mmDB_DEBUG_BASE_IDX … #define mmDB_DEBUG2 … #define mmDB_DEBUG2_BASE_IDX … #define mmDB_DEBUG3 … #define mmDB_DEBUG3_BASE_IDX … #define mmDB_DEBUG4 … #define mmDB_DEBUG4_BASE_IDX … #define mmDB_ETILE_STUTTER_CONTROL … #define mmDB_ETILE_STUTTER_CONTROL_BASE_IDX … #define mmDB_LTILE_STUTTER_CONTROL … #define mmDB_LTILE_STUTTER_CONTROL_BASE_IDX … #define mmDB_EQUAD_STUTTER_CONTROL … #define mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX … #define mmDB_LQUAD_STUTTER_CONTROL … #define mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX … #define mmDB_CREDIT_LIMIT … #define mmDB_CREDIT_LIMIT_BASE_IDX … #define mmDB_WATERMARKS … #define mmDB_WATERMARKS_BASE_IDX … #define mmDB_SUBTILE_CONTROL … #define mmDB_SUBTILE_CONTROL_BASE_IDX … #define mmDB_FREE_CACHELINES … #define mmDB_FREE_CACHELINES_BASE_IDX … #define mmDB_FIFO_DEPTH1 … #define mmDB_FIFO_DEPTH1_BASE_IDX … #define mmDB_FIFO_DEPTH2 … #define mmDB_FIFO_DEPTH2_BASE_IDX … #define mmDB_LAST_OF_BURST_CONFIG … #define mmDB_LAST_OF_BURST_CONFIG_BASE_IDX … #define mmDB_RING_CONTROL … #define mmDB_RING_CONTROL_BASE_IDX … #define mmDB_MEM_ARB_WATERMARKS … #define mmDB_MEM_ARB_WATERMARKS_BASE_IDX … #define mmDB_FIFO_DEPTH3 … #define mmDB_FIFO_DEPTH3_BASE_IDX … #define mmDB_RMI_BC_GL2_CACHE_CONTROL … #define mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX … #define mmDB_EXCEPTION_CONTROL … #define mmDB_EXCEPTION_CONTROL_BASE_IDX … #define mmDB_DFSM_CONFIG … #define mmDB_DFSM_CONFIG_BASE_IDX … #define mmDB_DFSM_TILES_IN_FLIGHT … #define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX … #define mmDB_DFSM_PRIMS_IN_FLIGHT … #define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX … #define mmDB_DFSM_WATCHDOG … #define mmDB_DFSM_WATCHDOG_BASE_IDX … #define mmDB_DFSM_FLUSH_ENABLE … #define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX … #define mmDB_DFSM_FLUSH_AUX_EVENT … #define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX … #define mmDB_FGCG_SRAMS_CLK_CTRL … #define mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX … #define mmDB_FGCG_INTERFACES_CLK_CTRL … #define mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX … #define mmCC_RB_REDUNDANCY … #define mmCC_RB_REDUNDANCY_BASE_IDX … #define mmCC_RB_BACKEND_DISABLE … #define mmCC_RB_BACKEND_DISABLE_BASE_IDX … #define mmGB_ADDR_CONFIG … #define mmGB_ADDR_CONFIG_BASE_IDX … #define mmGB_BACKEND_MAP … #define mmGB_BACKEND_MAP_BASE_IDX … #define mmGB_GPU_ID … #define mmGB_GPU_ID_BASE_IDX … #define mmCC_RB_DAISY_CHAIN … #define mmCC_RB_DAISY_CHAIN_BASE_IDX … #define mmGB_ADDR_CONFIG_READ … #define mmGB_ADDR_CONFIG_READ_BASE_IDX … #define mmGB_TILE_MODE0 … #define mmGB_TILE_MODE0_BASE_IDX … #define mmGB_TILE_MODE1 … #define mmGB_TILE_MODE1_BASE_IDX … #define mmGB_TILE_MODE2 … #define mmGB_TILE_MODE2_BASE_IDX … #define mmGB_TILE_MODE3 … #define mmGB_TILE_MODE3_BASE_IDX … #define mmGB_TILE_MODE4 … #define mmGB_TILE_MODE4_BASE_IDX … #define mmGB_TILE_MODE5 … #define mmGB_TILE_MODE5_BASE_IDX … #define mmGB_TILE_MODE6 … #define mmGB_TILE_MODE6_BASE_IDX … #define mmGB_TILE_MODE7 … #define mmGB_TILE_MODE7_BASE_IDX … #define mmGB_TILE_MODE8 … #define mmGB_TILE_MODE8_BASE_IDX … #define mmGB_TILE_MODE9 … #define mmGB_TILE_MODE9_BASE_IDX … #define mmGB_TILE_MODE10 … #define mmGB_TILE_MODE10_BASE_IDX … #define mmGB_TILE_MODE11 … #define mmGB_TILE_MODE11_BASE_IDX … #define mmGB_TILE_MODE12 … #define mmGB_TILE_MODE12_BASE_IDX … #define mmGB_TILE_MODE13 … #define mmGB_TILE_MODE13_BASE_IDX … #define mmGB_TILE_MODE14 … #define mmGB_TILE_MODE14_BASE_IDX … #define mmGB_TILE_MODE15 … #define mmGB_TILE_MODE15_BASE_IDX … #define mmGB_TILE_MODE16 … #define mmGB_TILE_MODE16_BASE_IDX … #define mmGB_TILE_MODE17 … #define mmGB_TILE_MODE17_BASE_IDX … #define mmGB_TILE_MODE18 … #define mmGB_TILE_MODE18_BASE_IDX … #define mmGB_TILE_MODE19 … #define mmGB_TILE_MODE19_BASE_IDX … #define mmGB_TILE_MODE20 … #define mmGB_TILE_MODE20_BASE_IDX … #define mmGB_TILE_MODE21 … #define mmGB_TILE_MODE21_BASE_IDX … #define mmGB_TILE_MODE22 … #define mmGB_TILE_MODE22_BASE_IDX … #define mmGB_TILE_MODE23 … #define mmGB_TILE_MODE23_BASE_IDX … #define mmGB_TILE_MODE24 … #define mmGB_TILE_MODE24_BASE_IDX … #define mmGB_TILE_MODE25 … #define mmGB_TILE_MODE25_BASE_IDX … #define mmGB_TILE_MODE26 … #define mmGB_TILE_MODE26_BASE_IDX … #define mmGB_TILE_MODE27 … #define mmGB_TILE_MODE27_BASE_IDX … #define mmGB_TILE_MODE28 … #define mmGB_TILE_MODE28_BASE_IDX … #define mmGB_TILE_MODE29 … #define mmGB_TILE_MODE29_BASE_IDX … #define mmGB_TILE_MODE30 … #define mmGB_TILE_MODE30_BASE_IDX … #define mmGB_TILE_MODE31 … #define mmGB_TILE_MODE31_BASE_IDX … #define mmGB_MACROTILE_MODE0 … #define mmGB_MACROTILE_MODE0_BASE_IDX … #define mmGB_MACROTILE_MODE1 … #define mmGB_MACROTILE_MODE1_BASE_IDX … #define mmGB_MACROTILE_MODE2 … #define mmGB_MACROTILE_MODE2_BASE_IDX … #define mmGB_MACROTILE_MODE3 … #define mmGB_MACROTILE_MODE3_BASE_IDX … #define mmGB_MACROTILE_MODE4 … #define mmGB_MACROTILE_MODE4_BASE_IDX … #define mmGB_MACROTILE_MODE5 … #define mmGB_MACROTILE_MODE5_BASE_IDX … #define mmGB_MACROTILE_MODE6 … #define mmGB_MACROTILE_MODE6_BASE_IDX … #define mmGB_MACROTILE_MODE7 … #define mmGB_MACROTILE_MODE7_BASE_IDX … #define mmGB_MACROTILE_MODE8 … #define mmGB_MACROTILE_MODE8_BASE_IDX … #define mmGB_MACROTILE_MODE9 … #define mmGB_MACROTILE_MODE9_BASE_IDX … #define mmGB_MACROTILE_MODE10 … #define mmGB_MACROTILE_MODE10_BASE_IDX … #define mmGB_MACROTILE_MODE11 … #define mmGB_MACROTILE_MODE11_BASE_IDX … #define mmGB_MACROTILE_MODE12 … #define mmGB_MACROTILE_MODE12_BASE_IDX … #define mmGB_MACROTILE_MODE13 … #define mmGB_MACROTILE_MODE13_BASE_IDX … #define mmGB_MACROTILE_MODE14 … #define mmGB_MACROTILE_MODE14_BASE_IDX … #define mmGB_MACROTILE_MODE15 … #define mmGB_MACROTILE_MODE15_BASE_IDX … #define mmCB_HW_CONTROL_4 … #define mmCB_HW_CONTROL_4_BASE_IDX … #define mmCB_HW_CONTROL_3 … #define mmCB_HW_CONTROL_3_BASE_IDX … #define mmCB_HW_CONTROL … #define mmCB_HW_CONTROL_BASE_IDX … #define mmCB_HW_CONTROL_1 … #define mmCB_HW_CONTROL_1_BASE_IDX … #define mmCB_HW_CONTROL_2 … #define mmCB_HW_CONTROL_2_BASE_IDX … #define mmCB_DCC_CONFIG … #define mmCB_DCC_CONFIG_BASE_IDX … #define mmCB_HW_MEM_ARBITER_RD … #define mmCB_HW_MEM_ARBITER_RD_BASE_IDX … #define mmCB_HW_MEM_ARBITER_WR … #define mmCB_HW_MEM_ARBITER_WR_BASE_IDX … #define mmCB_RMI_BC_GL2_CACHE_CONTROL … #define mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX … #define mmCB_STUTTER_CONTROL_CMASK_RDLAT … #define mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX … #define mmCB_STUTTER_CONTROL_FMASK_RDLAT … #define mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX … #define mmCB_STUTTER_CONTROL_COLOR_RDLAT … #define mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX … #define mmCB_CACHE_EVICT_POINTS … #define mmCB_CACHE_EVICT_POINTS_BASE_IDX … #define mmGC_USER_RB_REDUNDANCY … #define mmGC_USER_RB_REDUNDANCY_BASE_IDX … #define mmGC_USER_RB_BACKEND_DISABLE … #define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX … // addressBlock: gc_gceadec2 // base address: 0x9c00 #define mmGCEA_SDP_VCD_RESERVE1 … #define mmGCEA_SDP_VCD_RESERVE1_BASE_IDX … #define mmGCEA_SDP_REQ_CNTL … #define mmGCEA_SDP_REQ_CNTL_BASE_IDX … #define mmGCEA_MISC … #define mmGCEA_MISC_BASE_IDX … #define mmGCEA_LATENCY_SAMPLING … #define mmGCEA_LATENCY_SAMPLING_BASE_IDX … #define mmGCEA_PERFCOUNTER_LO … #define mmGCEA_PERFCOUNTER_LO_BASE_IDX … #define mmGCEA_PERFCOUNTER_HI … #define mmGCEA_PERFCOUNTER_HI_BASE_IDX … #define mmGCEA_PERFCOUNTER0_CFG … #define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX … #define mmGCEA_PERFCOUNTER1_CFG … #define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX … #define mmGCEA_PERFCOUNTER_RSLT_CNTL … #define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmGCEA_EDC_CNT … #define mmGCEA_EDC_CNT_BASE_IDX … #define mmGCEA_EDC_CNT2 … #define mmGCEA_EDC_CNT2_BASE_IDX … #define mmGCEA_DSM_CNTL … #define mmGCEA_DSM_CNTL_BASE_IDX … #define mmGCEA_DSM_CNTLA … #define mmGCEA_DSM_CNTLA_BASE_IDX … #define mmGCEA_DSM_CNTLB … #define mmGCEA_DSM_CNTLB_BASE_IDX … #define mmGCEA_DSM_CNTL2 … #define mmGCEA_DSM_CNTL2_BASE_IDX … #define mmGCEA_DSM_CNTL2A … #define mmGCEA_DSM_CNTL2A_BASE_IDX … #define mmGCEA_DSM_CNTL2B … #define mmGCEA_DSM_CNTL2B_BASE_IDX … #define mmGCEA_GL2C_XBR_CREDITS … #define mmGCEA_GL2C_XBR_CREDITS_BASE_IDX … #define mmGCEA_GL2C_XBR_MAXBURST … #define mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX … #define mmGCEA_PROBE_CNTL … #define mmGCEA_PROBE_CNTL_BASE_IDX … #define mmGCEA_PROBE_MAP … #define mmGCEA_PROBE_MAP_BASE_IDX … #define mmGCEA_ERR_STATUS … #define mmGCEA_ERR_STATUS_BASE_IDX … #define mmGCEA_MISC2 … #define mmGCEA_MISC2_BASE_IDX … // addressBlock: gc_spipdec2 // base address: 0x9c80 #define mmSPI_PQEV_CTRL … #define mmSPI_PQEV_CTRL_BASE_IDX … #define mmSPI_SYS_COMPUTE … #define mmSPI_SYS_COMPUTE_BASE_IDX … #define mmSPI_SYS_WIF_CNTL … #define mmSPI_SYS_WIF_CNTL_BASE_IDX … // addressBlock: gc_gceadec3 // base address: 0x9dc0 #define mmGCEA_DRAM_BANK_ARB … #define mmGCEA_DRAM_BANK_ARB_BASE_IDX … #define mmGCEA_DRAM_BANK_ARB_RFSH … #define mmGCEA_DRAM_BANK_ARB_RFSH_BASE_IDX … #define mmGCEA_SDP_BACKDOOR_CMDCREDITS0 … #define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX … #define mmGCEA_SDP_BACKDOOR_CMDCREDITS1 … #define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX … #define mmGCEA_SDP_BACKDOOR_DATACREDITS0 … #define mmGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX … #define mmGCEA_SDP_BACKDOOR_DATACREDITS1 … #define mmGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX … #define mmGCEA_SDP_BACKDOOR_MISCCREDITS … #define mmGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PACH … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PACH_BASE_IDX … #define mmGCEA_RRET_MEM_RESERVE … #define mmGCEA_RRET_MEM_RESERVE_BASE_IDX … #define mmGCEA_ADDRDEC_SELECT … #define mmGCEA_ADDRDEC_SELECT_BASE_IDX … #define mmGCEA_SDP_ENABLE … #define mmGCEA_SDP_ENABLE_BASE_IDX … // addressBlock: gc_rmi_rmidec // base address: 0x9e00 #define mmRMI_GENERAL_CNTL … #define mmRMI_GENERAL_CNTL_BASE_IDX … #define mmRMI_GENERAL_CNTL1 … #define mmRMI_GENERAL_CNTL1_BASE_IDX … #define mmRMI_GENERAL_STATUS … #define mmRMI_GENERAL_STATUS_BASE_IDX … #define mmRMI_SUBBLOCK_STATUS0 … #define mmRMI_SUBBLOCK_STATUS0_BASE_IDX … #define mmRMI_SUBBLOCK_STATUS1 … #define mmRMI_SUBBLOCK_STATUS1_BASE_IDX … #define mmRMI_SUBBLOCK_STATUS2 … #define mmRMI_SUBBLOCK_STATUS2_BASE_IDX … #define mmRMI_SUBBLOCK_STATUS3 … #define mmRMI_SUBBLOCK_STATUS3_BASE_IDX … #define mmRMI_XBAR_CONFIG … #define mmRMI_XBAR_CONFIG_BASE_IDX … #define mmRMI_PROBE_POP_LOGIC_CNTL … #define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX … #define mmRMI_UTC_XNACK_N_MISC_CNTL … #define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX … #define mmRMI_DEMUX_CNTL … #define mmRMI_DEMUX_CNTL_BASE_IDX … #define mmRMI_UTCL1_CNTL1 … #define mmRMI_UTCL1_CNTL1_BASE_IDX … #define mmRMI_UTCL1_CNTL2 … #define mmRMI_UTCL1_CNTL2_BASE_IDX … #define mmRMI_UTC_UNIT_CONFIG … #define mmRMI_UTC_UNIT_CONFIG_BASE_IDX … #define mmRMI_TCIW_FORMATTER0_CNTL … #define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX … #define mmRMI_TCIW_FORMATTER1_CNTL … #define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX … #define mmRMI_SCOREBOARD_CNTL … #define mmRMI_SCOREBOARD_CNTL_BASE_IDX … #define mmRMI_SCOREBOARD_STATUS0 … #define mmRMI_SCOREBOARD_STATUS0_BASE_IDX … #define mmRMI_SCOREBOARD_STATUS1 … #define mmRMI_SCOREBOARD_STATUS1_BASE_IDX … #define mmRMI_SCOREBOARD_STATUS2 … #define mmRMI_SCOREBOARD_STATUS2_BASE_IDX … #define mmRMI_XBAR_ARBITER_CONFIG … #define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX … #define mmRMI_XBAR_ARBITER_CONFIG_1 … #define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX … #define mmRMI_CLOCK_CNTRL … #define mmRMI_CLOCK_CNTRL_BASE_IDX … #define mmRMI_UTCL1_STATUS … #define mmRMI_UTCL1_STATUS_BASE_IDX … #define mmRMI_RB_GLX_CID_MAP … #define mmRMI_RB_GLX_CID_MAP_BASE_IDX … #define mmRMI_SPARE … #define mmRMI_SPARE_BASE_IDX … #define mmRMI_SPARE_1 … #define mmRMI_SPARE_1_BASE_IDX … #define mmRMI_SPARE_2 … #define mmRMI_SPARE_2_BASE_IDX … #define mmCC_RMI_REDUNDANCY … #define mmCC_RMI_REDUNDANCY_BASE_IDX … #define mmGC_USER_RMI_REDUNDANCY … #define mmGC_USER_RMI_REDUNDANCY_BASE_IDX … // addressBlock: gc_pmmdec // base address: 0x9f80 #define mmPMM_GENERAL_CNTL … #define mmPMM_GENERAL_CNTL_BASE_IDX … #define mmGCR_PIO_CNTL … #define mmGCR_PIO_CNTL_BASE_IDX … #define mmGCR_PIO_DATA … #define mmGCR_PIO_DATA_BASE_IDX … #define mmGCR_GENERAL_CNTL … #define mmGCR_GENERAL_CNTL_BASE_IDX … #define mmGCR_TARGET_DISABLE … #define mmGCR_TARGET_DISABLE_BASE_IDX … #define mmGCR_CMD_STATUS … #define mmGCR_CMD_STATUS_BASE_IDX … #define mmGCR_SPARE … #define mmGCR_SPARE_BASE_IDX … // addressBlock: gc_utcl1dec // base address: 0x9fa0 #define mmUTCL1_CTRL … #define mmUTCL1_CTRL_BASE_IDX … #define mmUTCL1_ALOG … #define mmUTCL1_ALOG_BASE_IDX … #define mmUTCL1_UTCL0_INVREQ_DISABLE … #define mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX … #define mmGCRD_SA_TARGETS_DISABLE … #define mmGCRD_SA_TARGETS_DISABLE_BASE_IDX … // addressBlock: gc_gcatcl2dec // base address: 0xa000 #define mmGC_ATC_L2_CNTL … #define mmGC_ATC_L2_CNTL_BASE_IDX … #define mmGC_ATC_L2_CNTL2 … #define mmGC_ATC_L2_CNTL2_BASE_IDX … #define mmGC_ATC_L2_CACHE_DATA0 … #define mmGC_ATC_L2_CACHE_DATA0_BASE_IDX … #define mmGC_ATC_L2_CACHE_DATA1 … #define mmGC_ATC_L2_CACHE_DATA1_BASE_IDX … #define mmGC_ATC_L2_CACHE_DATA2 … #define mmGC_ATC_L2_CACHE_DATA2_BASE_IDX … #define mmGC_ATC_L2_CNTL3 … #define mmGC_ATC_L2_CNTL3_BASE_IDX … #define mmGC_ATC_L2_STATUS … #define mmGC_ATC_L2_STATUS_BASE_IDX … #define mmGC_ATC_L2_STATUS2 … #define mmGC_ATC_L2_STATUS2_BASE_IDX … #define mmGC_ATC_L2_MISC_CG … #define mmGC_ATC_L2_MISC_CG_BASE_IDX … #define mmGC_ATC_L2_MEM_POWER_LS … #define mmGC_ATC_L2_MEM_POWER_LS_BASE_IDX … #define mmGC_ATC_L2_CGTT_CLK_CTRL … #define mmGC_ATC_L2_CGTT_CLK_CTRL_BASE_IDX … #define mmGC_ATC_L2_SDPPORT_CTRL … #define mmGC_ATC_L2_SDPPORT_CTRL_BASE_IDX … // addressBlock: gc_gcvml2pfdec // base address: 0xa100 #define mmGCVM_L2_CNTL … #define mmGCVM_L2_CNTL_BASE_IDX … #define mmGCVM_L2_CNTL2 … #define mmGCVM_L2_CNTL2_BASE_IDX … #define mmGCVM_L2_CNTL3 … #define mmGCVM_L2_CNTL3_BASE_IDX … #define mmGCVM_L2_STATUS … #define mmGCVM_L2_STATUS_BASE_IDX … #define mmGCVM_DUMMY_PAGE_FAULT_CNTL … #define mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_CNTL … #define mmGCVM_INVALIDATE_CNTL_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_CNTL … #define mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_CNTL2 … #define mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3 … #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4 … #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_STATUS … #define mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32 … #define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32 … #define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define mmGCVM_L2_CNTL4 … #define mmGCVM_L2_CNTL4_BASE_IDX … #define mmGCVM_L2_MM_GROUP_RT_CLASSES … #define mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define mmGCVM_L2_BANK_SELECT_RESERVED_CID … #define mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2 … #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define mmGCVM_L2_CACHE_PARITY_CNTL … #define mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define mmGCVM_L2_CGTT_CLK_CTRL … #define mmGCVM_L2_CGTT_CLK_CTRL_BASE_IDX … #define mmGCVM_L2_CNTL5 … #define mmGCVM_L2_CNTL5_BASE_IDX … #define mmGCVM_L2_GCR_CNTL … #define mmGCVM_L2_GCR_CNTL_BASE_IDX … #define mmGCVML2_WALKER_MACRO_THROTTLE_TIME … #define mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX … #define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT … #define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX … #define mmGCVML2_WALKER_MICRO_THROTTLE_TIME … #define mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX … #define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT … #define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX … // addressBlock: gc_gcvml2vcdec // base address: 0xa200 #define mmGCVM_CONTEXT0_CNTL … #define mmGCVM_CONTEXT0_CNTL_BASE_IDX … #define mmGCVM_CONTEXT1_CNTL … #define mmGCVM_CONTEXT1_CNTL_BASE_IDX … #define mmGCVM_CONTEXT2_CNTL … #define mmGCVM_CONTEXT2_CNTL_BASE_IDX … #define mmGCVM_CONTEXT3_CNTL … #define mmGCVM_CONTEXT3_CNTL_BASE_IDX … #define mmGCVM_CONTEXT4_CNTL … #define mmGCVM_CONTEXT4_CNTL_BASE_IDX … #define mmGCVM_CONTEXT5_CNTL … #define mmGCVM_CONTEXT5_CNTL_BASE_IDX … #define mmGCVM_CONTEXT6_CNTL … #define mmGCVM_CONTEXT6_CNTL_BASE_IDX … #define mmGCVM_CONTEXT7_CNTL … #define mmGCVM_CONTEXT7_CNTL_BASE_IDX … #define mmGCVM_CONTEXT8_CNTL … #define mmGCVM_CONTEXT8_CNTL_BASE_IDX … #define mmGCVM_CONTEXT9_CNTL … #define mmGCVM_CONTEXT9_CNTL_BASE_IDX … #define mmGCVM_CONTEXT10_CNTL … #define mmGCVM_CONTEXT10_CNTL_BASE_IDX … #define mmGCVM_CONTEXT11_CNTL … #define mmGCVM_CONTEXT11_CNTL_BASE_IDX … #define mmGCVM_CONTEXT12_CNTL … #define mmGCVM_CONTEXT12_CNTL_BASE_IDX … #define mmGCVM_CONTEXT13_CNTL … #define mmGCVM_CONTEXT13_CNTL_BASE_IDX … #define mmGCVM_CONTEXT14_CNTL … #define mmGCVM_CONTEXT14_CNTL_BASE_IDX … #define mmGCVM_CONTEXT15_CNTL … #define mmGCVM_CONTEXT15_CNTL_BASE_IDX … #define mmGCVM_CONTEXTS_DISABLE … #define mmGCVM_CONTEXTS_DISABLE_BASE_IDX … #define mmGCVM_INVALIDATE_ENG0_SEM … #define mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG1_SEM … #define mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG2_SEM … #define mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG3_SEM … #define mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG4_SEM … #define mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG5_SEM … #define mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG6_SEM … #define mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG7_SEM … #define mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG8_SEM … #define mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG9_SEM … #define mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG10_SEM … #define mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG11_SEM … #define mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG12_SEM … #define mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG13_SEM … #define mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG14_SEM … #define mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG15_SEM … #define mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG16_SEM … #define mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG17_SEM … #define mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX … #define mmGCVM_INVALIDATE_ENG0_REQ … #define mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG1_REQ … #define mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG2_REQ … #define mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG3_REQ … #define mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG4_REQ … #define mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG5_REQ … #define mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG6_REQ … #define mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG7_REQ … #define mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG8_REQ … #define mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG9_REQ … #define mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG10_REQ … #define mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG11_REQ … #define mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG12_REQ … #define mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG13_REQ … #define mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG14_REQ … #define mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG15_REQ … #define mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG16_REQ … #define mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG17_REQ … #define mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX … #define mmGCVM_INVALIDATE_ENG0_ACK … #define mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG1_ACK … #define mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG2_ACK … #define mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG3_ACK … #define mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG4_ACK … #define mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG5_ACK … #define mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG6_ACK … #define mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG7_ACK … #define mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG8_ACK … #define mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG9_ACK … #define mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG10_ACK … #define mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG11_ACK … #define mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG12_ACK … #define mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG13_ACK … #define mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG14_ACK … #define mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG15_ACK … #define mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG16_ACK … #define mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG17_ACK … #define mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX … #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … // addressBlock: gc_gcvmsharedpfdec // base address: 0xa590 #define mmGCMC_VM_NB_MMIOBASE … #define mmGCMC_VM_NB_MMIOBASE_BASE_IDX … #define mmGCMC_VM_NB_MMIOLIMIT … #define mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX … #define mmGCMC_VM_NB_PCI_CTRL … #define mmGCMC_VM_NB_PCI_CTRL_BASE_IDX … #define mmGCMC_VM_NB_PCI_ARB … #define mmGCMC_VM_NB_PCI_ARB_BASE_IDX … #define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1 … #define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2 … #define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2 … #define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define mmGCMC_VM_FB_OFFSET … #define mmGCMC_VM_FB_OFFSET_BASE_IDX … #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmGCMC_VM_STEERING … #define mmGCMC_VM_STEERING_BASE_IDX … #define mmGCMC_SHARED_VIRT_RESET_REQ … #define mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define mmGCMC_MEM_POWER_LS … #define mmGCMC_MEM_POWER_LS_BASE_IDX … #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START … #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END … #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define mmGCMC_VM_APT_CNTL … #define mmGCMC_VM_APT_CNTL_BASE_IDX … #define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL … #define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX … #define mmGCMC_VM_LOCAL_HBM_ADDRESS_START … #define mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX … #define mmGCMC_VM_LOCAL_HBM_ADDRESS_END … #define mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX … #define mmGCMC_SHARED_VIRT_RESET_REQ2 … #define mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX … // addressBlock: gc_gcvmsharedvcdec // base address: 0xa600 #define mmGCMC_VM_FB_LOCATION_BASE … #define mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX … #define mmGCMC_VM_FB_LOCATION_TOP … #define mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX … #define mmGCMC_VM_AGP_TOP … #define mmGCMC_VM_AGP_TOP_BASE_IDX … #define mmGCMC_VM_AGP_BOT … #define mmGCMC_VM_AGP_BOT_BASE_IDX … #define mmGCMC_VM_AGP_BASE … #define mmGCMC_VM_AGP_BASE_BASE_IDX … #define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR … #define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define mmGCMC_VM_MX_L1_TLB_CNTL … #define mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: gc_gceadec // base address: 0xa800 #define mmGCEA_DRAM_RD_CLI2GRP_MAP0 … #define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmGCEA_DRAM_RD_CLI2GRP_MAP1 … #define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmGCEA_DRAM_WR_CLI2GRP_MAP0 … #define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmGCEA_DRAM_WR_CLI2GRP_MAP1 … #define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmGCEA_DRAM_RD_GRP2VC_MAP … #define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmGCEA_DRAM_WR_GRP2VC_MAP … #define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmGCEA_DRAM_RD_LAZY … #define mmGCEA_DRAM_RD_LAZY_BASE_IDX … #define mmGCEA_DRAM_WR_LAZY … #define mmGCEA_DRAM_WR_LAZY_BASE_IDX … #define mmGCEA_DRAM_RD_CAM_CNTL … #define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmGCEA_DRAM_WR_CAM_CNTL … #define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmGCEA_DRAM_PAGE_BURST … #define mmGCEA_DRAM_PAGE_BURST_BASE_IDX … #define mmGCEA_DRAM_RD_PRI_AGE … #define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX … #define mmGCEA_DRAM_WR_PRI_AGE … #define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX … #define mmGCEA_DRAM_RD_PRI_QUEUING … #define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmGCEA_DRAM_WR_PRI_QUEUING … #define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmGCEA_DRAM_RD_PRI_FIXED … #define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmGCEA_DRAM_WR_PRI_FIXED … #define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmGCEA_DRAM_RD_PRI_URGENCY … #define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmGCEA_DRAM_WR_PRI_URGENCY … #define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 … #define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 … #define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 … #define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 … #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 … #define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 … #define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmGCEA_ADDRNORM_BASE_ADDR0 … #define mmGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmGCEA_ADDRNORM_LIMIT_ADDR0 … #define mmGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmGCEA_ADDRNORM_BASE_ADDR1 … #define mmGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmGCEA_ADDRNORM_LIMIT_ADDR1 … #define mmGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmGCEA_ADDRNORM_OFFSET_ADDR1 … #define mmGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmGCEA_ADDRNORMDRAM_HOLE_CNTL … #define mmGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmGCEA_ADDRDEC_BANK_CFG … #define mmGCEA_ADDRDEC_BANK_CFG_BASE_IDX … #define mmGCEA_ADDRDEC_MISC_CFG … #define mmGCEA_ADDRDEC_MISC_CFG_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE … #define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START0 … #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX … #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END0 … #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX … #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START1 … #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX … #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END1 … #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX … #define mmGCEA_ADDRDEC0_BASE_ADDR_CS0 … #define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmGCEA_ADDRDEC0_BASE_ADDR_CS1 … #define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmGCEA_ADDRDEC0_BASE_ADDR_CS2 … #define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmGCEA_ADDRDEC0_BASE_ADDR_CS3 … #define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmGCEA_ADDRDEC0_ADDR_MASK_CS01 … #define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmGCEA_ADDRDEC0_ADDR_MASK_CS23 … #define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmGCEA_ADDRDEC0_ADDR_CFG_CS01 … #define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmGCEA_ADDRDEC0_ADDR_CFG_CS23 … #define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmGCEA_ADDRDEC0_ADDR_SEL_CS01 … #define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmGCEA_ADDRDEC0_ADDR_SEL_CS23 … #define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01 … #define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23 … #define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01 … #define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23 … #define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmGCEA_ADDRDEC0_RM_SEL_CS01 … #define mmGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmGCEA_ADDRDEC0_RM_SEL_CS23 … #define mmGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmGCEA_ADDRDEC0_RM_SEL_SECCS01 … #define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmGCEA_ADDRDEC0_RM_SEL_SECCS23 … #define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmGCEA_ADDRDEC1_BASE_ADDR_CS0 … #define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmGCEA_ADDRDEC1_BASE_ADDR_CS1 … #define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmGCEA_ADDRDEC1_BASE_ADDR_CS2 … #define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmGCEA_ADDRDEC1_BASE_ADDR_CS3 … #define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmGCEA_ADDRDEC1_ADDR_MASK_CS01 … #define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmGCEA_ADDRDEC1_ADDR_MASK_CS23 … #define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmGCEA_ADDRDEC1_ADDR_CFG_CS01 … #define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmGCEA_ADDRDEC1_ADDR_CFG_CS23 … #define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmGCEA_ADDRDEC1_ADDR_SEL_CS01 … #define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmGCEA_ADDRDEC1_ADDR_SEL_CS23 … #define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01 … #define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23 … #define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01 … #define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23 … #define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmGCEA_ADDRDEC1_RM_SEL_CS01 … #define mmGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmGCEA_ADDRDEC1_RM_SEL_CS23 … #define mmGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmGCEA_ADDRDEC1_RM_SEL_SECCS01 … #define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmGCEA_ADDRDEC1_RM_SEL_SECCS23 … #define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmGCEA_IO_RD_CLI2GRP_MAP0 … #define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmGCEA_IO_RD_CLI2GRP_MAP1 … #define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmGCEA_IO_WR_CLI2GRP_MAP0 … #define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmGCEA_IO_WR_CLI2GRP_MAP1 … #define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmGCEA_IO_RD_COMBINE_FLUSH … #define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmGCEA_IO_WR_COMBINE_FLUSH … #define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmGCEA_IO_GROUP_BURST … #define mmGCEA_IO_GROUP_BURST_BASE_IDX … #define mmGCEA_IO_RD_PRI_AGE … #define mmGCEA_IO_RD_PRI_AGE_BASE_IDX … #define mmGCEA_IO_WR_PRI_AGE … #define mmGCEA_IO_WR_PRI_AGE_BASE_IDX … #define mmGCEA_IO_RD_PRI_QUEUING … #define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX … #define mmGCEA_IO_WR_PRI_QUEUING … #define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX … #define mmGCEA_IO_RD_PRI_FIXED … #define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX … #define mmGCEA_IO_WR_PRI_FIXED … #define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX … #define mmGCEA_IO_RD_PRI_URGENCY … #define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX … #define mmGCEA_IO_WR_PRI_URGENCY … #define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX … #define mmGCEA_IO_RD_PRI_URGENCY_MASKING … #define mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmGCEA_IO_WR_PRI_URGENCY_MASKING … #define mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmGCEA_IO_RD_PRI_QUANT_PRI1 … #define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmGCEA_IO_RD_PRI_QUANT_PRI2 … #define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmGCEA_IO_RD_PRI_QUANT_PRI3 … #define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmGCEA_IO_WR_PRI_QUANT_PRI1 … #define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmGCEA_IO_WR_PRI_QUANT_PRI2 … #define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmGCEA_IO_WR_PRI_QUANT_PRI3 … #define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmGCEA_SDP_ARB_DRAM … #define mmGCEA_SDP_ARB_DRAM_BASE_IDX … #define mmGCEA_SDP_ARB_FINAL … #define mmGCEA_SDP_ARB_FINAL_BASE_IDX … #define mmGCEA_SDP_DRAM_PRIORITY … #define mmGCEA_SDP_DRAM_PRIORITY_BASE_IDX … #define mmGCEA_SDP_IO_PRIORITY … #define mmGCEA_SDP_IO_PRIORITY_BASE_IDX … #define mmGCEA_SDP_CREDITS … #define mmGCEA_SDP_CREDITS_BASE_IDX … #define mmGCEA_SDP_TAG_RESERVE0 … #define mmGCEA_SDP_TAG_RESERVE0_BASE_IDX … #define mmGCEA_SDP_TAG_RESERVE1 … #define mmGCEA_SDP_TAG_RESERVE1_BASE_IDX … #define mmGCEA_SDP_VCC_RESERVE0 … #define mmGCEA_SDP_VCC_RESERVE0_BASE_IDX … #define mmGCEA_SDP_VCC_RESERVE1 … #define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX … #define mmGCEA_SDP_VCD_RESERVE0 … #define mmGCEA_SDP_VCD_RESERVE0_BASE_IDX … // addressBlock: gc_tcdec // base address: 0xac00 #define mmTCP_INVALIDATE … #define mmTCP_INVALIDATE_BASE_IDX … #define mmTCP_STATUS … #define mmTCP_STATUS_BASE_IDX … #define mmTCP_CNTL … #define mmTCP_CNTL_BASE_IDX … #define mmTCP_CREDIT … #define mmTCP_CREDIT_BASE_IDX … #define mmTCP_BUFFER_ADDR_HASH_CNTL … #define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX … #define mmTCP_EDC_CNT … #define mmTCP_EDC_CNT_BASE_IDX … #define mmTCI_STATUS … #define mmTCI_STATUS_BASE_IDX … #define mmTCI_CNTL_1 … #define mmTCI_CNTL_1_BASE_IDX … #define mmTCI_CNTL_2 … #define mmTCI_CNTL_2_BASE_IDX … // addressBlock: gc_shdec // base address: 0xb000 #define mmSPI_SHADER_PGM_RSRC4_PS … #define mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX … #define mmSPI_SHADER_PGM_CHKSUM_PS … #define mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC3_PS … #define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX … #define mmSPI_SHADER_PGM_LO_PS … #define mmSPI_SHADER_PGM_LO_PS_BASE_IDX … #define mmSPI_SHADER_PGM_HI_PS … #define mmSPI_SHADER_PGM_HI_PS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC1_PS … #define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_PS … #define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_0 … #define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_1 … #define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_2 … #define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_3 … #define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_4 … #define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_5 … #define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_6 … #define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_7 … #define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_8 … #define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_9 … #define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_10 … #define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_11 … #define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_12 … #define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_13 … #define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_14 … #define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_15 … #define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_16 … #define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_17 … #define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_18 … #define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_19 … #define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_20 … #define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_21 … #define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_22 … #define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_23 … #define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_24 … #define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_25 … #define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_26 … #define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_27 … #define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_28 … #define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_29 … #define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_30 … #define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX … #define mmSPI_SHADER_USER_DATA_PS_31 … #define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX … #define mmSPI_SHADER_REQ_CTRL_PS … #define mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_PS … #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_PS_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_0 … #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_0_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_PS_0 … #define mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_1 … #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_1_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_PS_1 … #define mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_2 … #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_2_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_PS_2 … #define mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_3 … #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_3_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_PS_3 … #define mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC4_VS … #define mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX … #define mmSPI_SHADER_PGM_CHKSUM_VS … #define mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC3_VS … #define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX … #define mmSPI_SHADER_LATE_ALLOC_VS … #define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX … #define mmSPI_SHADER_PGM_LO_VS … #define mmSPI_SHADER_PGM_LO_VS_BASE_IDX … #define mmSPI_SHADER_PGM_HI_VS … #define mmSPI_SHADER_PGM_HI_VS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC1_VS … #define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_VS … #define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_0 … #define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_1 … #define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_2 … #define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_3 … #define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_4 … #define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_5 … #define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_6 … #define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_7 … #define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_8 … #define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_9 … #define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_10 … #define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_11 … #define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_12 … #define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_13 … #define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_14 … #define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_15 … #define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_16 … #define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_17 … #define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_18 … #define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_19 … #define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_20 … #define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_21 … #define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_22 … #define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_23 … #define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_24 … #define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_25 … #define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_26 … #define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_27 … #define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_28 … #define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_29 … #define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_30 … #define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX … #define mmSPI_SHADER_USER_DATA_VS_31 … #define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX … #define mmSPI_SHADER_REQ_CTRL_VS … #define mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_VS … #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_VS_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_0 … #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_0_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_VS_0 … #define mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_1 … #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_1_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_VS_1 … #define mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_2 … #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_2_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_VS_2 … #define mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_3 … #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_3_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_VS_3 … #define mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_GS_VS … #define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_ES_VS … #define mmSPI_SHADER_PGM_RSRC2_ES_VS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_LS_VS … #define mmSPI_SHADER_PGM_RSRC2_LS_VS_BASE_IDX … #define mmSPI_SHADER_PGM_CHKSUM_GS … #define mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC4_GS … #define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ADDR_LO_GS … #define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ADDR_HI_GS … #define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX … #define mmSPI_SHADER_PGM_LO_ES_GS … #define mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX … #define mmSPI_SHADER_PGM_HI_ES_GS … #define mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC3_GS … #define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX … #define mmSPI_SHADER_PGM_LO_GS … #define mmSPI_SHADER_PGM_LO_GS_BASE_IDX … #define mmSPI_SHADER_PGM_HI_GS … #define mmSPI_SHADER_PGM_HI_GS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC1_GS … #define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_GS … #define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_0 … #define mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_1 … #define mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_2 … #define mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_3 … #define mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_4 … #define mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_5 … #define mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_6 … #define mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_7 … #define mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_8 … #define mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_9 … #define mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_10 … #define mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_11 … #define mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_12 … #define mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_13 … #define mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_14 … #define mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_15 … #define mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_16 … #define mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_17 … #define mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_18 … #define mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_19 … #define mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_20 … #define mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_21 … #define mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_22 … #define mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_23 … #define mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_24 … #define mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_25 … #define mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_26 … #define mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_27 … #define mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_28 … #define mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_29 … #define mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_30 … #define mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX … #define mmSPI_SHADER_USER_DATA_GS_31 … #define mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX … #define mmSPI_SHADER_REQ_CTRL_ESGS … #define mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS … #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_0 … #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_0_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_ESGS_0 … #define mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_1 … #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_1_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_ESGS_1 … #define mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_2 … #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_2_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_ESGS_2 … #define mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_3 … #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_3_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_ESGS_3 … #define mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_ES_GS … #define mmSPI_SHADER_PGM_RSRC2_ES_GS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC3_ES … #define mmSPI_SHADER_PGM_RSRC3_ES_BASE_IDX … #define mmSPI_SHADER_PGM_LO_ES … #define mmSPI_SHADER_PGM_LO_ES_BASE_IDX … #define mmSPI_SHADER_PGM_HI_ES … #define mmSPI_SHADER_PGM_HI_ES_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC1_ES … #define mmSPI_SHADER_PGM_RSRC1_ES_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_ES … #define mmSPI_SHADER_PGM_RSRC2_ES_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_0 … #define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_1 … #define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_2 … #define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_3 … #define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_4 … #define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_5 … #define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_6 … #define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_7 … #define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_8 … #define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_9 … #define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_10 … #define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_11 … #define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_12 … #define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_13 … #define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_14 … #define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ES_15 … #define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_LS_ES … #define mmSPI_SHADER_PGM_RSRC2_LS_ES_BASE_IDX … #define mmSPI_SHADER_PGM_CHKSUM_HS … #define mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC4_HS … #define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ADDR_LO_HS … #define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_ADDR_HI_HS … #define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX … #define mmSPI_SHADER_PGM_LO_LS_HS … #define mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX … #define mmSPI_SHADER_PGM_HI_LS_HS … #define mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC3_HS … #define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX … #define mmSPI_SHADER_PGM_LO_HS … #define mmSPI_SHADER_PGM_LO_HS_BASE_IDX … #define mmSPI_SHADER_PGM_HI_HS … #define mmSPI_SHADER_PGM_HI_HS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC1_HS … #define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_HS … #define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_0 … #define mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_1 … #define mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_2 … #define mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_3 … #define mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_4 … #define mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_5 … #define mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_6 … #define mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_7 … #define mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_8 … #define mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_9 … #define mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_10 … #define mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_11 … #define mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_12 … #define mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_13 … #define mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_14 … #define mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_15 … #define mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_16 … #define mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_17 … #define mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_18 … #define mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_19 … #define mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_20 … #define mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_21 … #define mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_22 … #define mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_23 … #define mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_24 … #define mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_25 … #define mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_26 … #define mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_27 … #define mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_28 … #define mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_29 … #define mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_30 … #define mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX … #define mmSPI_SHADER_USER_DATA_HS_31 … #define mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX … #define mmSPI_SHADER_REQ_CTRL_LSHS … #define mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS … #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_0 … #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_0_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_LSHS_0 … #define mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_1 … #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_1_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_LSHS_1 … #define mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_2 … #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_2_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_LSHS_2 … #define mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX … #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_3 … #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_3_BASE_IDX … #define mmSPI_SHADER_USER_ACCUM_LSHS_3 … #define mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_LS_HS … #define mmSPI_SHADER_PGM_RSRC2_LS_HS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC3_LS … #define mmSPI_SHADER_PGM_RSRC3_LS_BASE_IDX … #define mmSPI_SHADER_PGM_LO_LS … #define mmSPI_SHADER_PGM_LO_LS_BASE_IDX … #define mmSPI_SHADER_PGM_HI_LS … #define mmSPI_SHADER_PGM_HI_LS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC1_LS … #define mmSPI_SHADER_PGM_RSRC1_LS_BASE_IDX … #define mmSPI_SHADER_PGM_RSRC2_LS … #define mmSPI_SHADER_PGM_RSRC2_LS_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_0 … #define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_1 … #define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_2 … #define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_3 … #define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_4 … #define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_5 … #define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_6 … #define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_7 … #define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_8 … #define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_9 … #define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_10 … #define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_11 … #define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_12 … #define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_13 … #define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_14 … #define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX … #define mmSPI_SHADER_USER_DATA_LS_15 … #define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX … #define mmCOMPUTE_DISPATCH_INITIATOR … #define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX … #define mmCOMPUTE_DIM_X … #define mmCOMPUTE_DIM_X_BASE_IDX … #define mmCOMPUTE_DIM_Y … #define mmCOMPUTE_DIM_Y_BASE_IDX … #define mmCOMPUTE_DIM_Z … #define mmCOMPUTE_DIM_Z_BASE_IDX … #define mmCOMPUTE_START_X … #define mmCOMPUTE_START_X_BASE_IDX … #define mmCOMPUTE_START_Y … #define mmCOMPUTE_START_Y_BASE_IDX … #define mmCOMPUTE_START_Z … #define mmCOMPUTE_START_Z_BASE_IDX … #define mmCOMPUTE_NUM_THREAD_X … #define mmCOMPUTE_NUM_THREAD_X_BASE_IDX … #define mmCOMPUTE_NUM_THREAD_Y … #define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX … #define mmCOMPUTE_NUM_THREAD_Z … #define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX … #define mmCOMPUTE_PIPELINESTAT_ENABLE … #define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX … #define mmCOMPUTE_PERFCOUNT_ENABLE … #define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX … #define mmCOMPUTE_PGM_LO … #define mmCOMPUTE_PGM_LO_BASE_IDX … #define mmCOMPUTE_PGM_HI … #define mmCOMPUTE_PGM_HI_BASE_IDX … #define mmCOMPUTE_DISPATCH_PKT_ADDR_LO … #define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX … #define mmCOMPUTE_DISPATCH_PKT_ADDR_HI … #define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX … #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO … #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX … #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI … #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX … #define mmCOMPUTE_PGM_RSRC1 … #define mmCOMPUTE_PGM_RSRC1_BASE_IDX … #define mmCOMPUTE_PGM_RSRC2 … #define mmCOMPUTE_PGM_RSRC2_BASE_IDX … #define mmCOMPUTE_VMID … #define mmCOMPUTE_VMID_BASE_IDX … #define mmCOMPUTE_RESOURCE_LIMITS … #define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX … #define mmCOMPUTE_DESTINATION_EN_SE0 … #define mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX … #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 … #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX … #define mmCOMPUTE_DESTINATION_EN_SE1 … #define mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX … #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 … #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX … #define mmCOMPUTE_TMPRING_SIZE … #define mmCOMPUTE_TMPRING_SIZE_BASE_IDX … #define mmCOMPUTE_DESTINATION_EN_SE2 … #define mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX … #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 … #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX … #define mmCOMPUTE_DESTINATION_EN_SE3 … #define mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX … #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 … #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX … #define mmCOMPUTE_RESTART_X … #define mmCOMPUTE_RESTART_X_BASE_IDX … #define mmCOMPUTE_RESTART_Y … #define mmCOMPUTE_RESTART_Y_BASE_IDX … #define mmCOMPUTE_RESTART_Z … #define mmCOMPUTE_RESTART_Z_BASE_IDX … #define mmCOMPUTE_THREAD_TRACE_ENABLE … #define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX … #define mmCOMPUTE_MISC_RESERVED … #define mmCOMPUTE_MISC_RESERVED_BASE_IDX … #define mmCOMPUTE_DISPATCH_ID … #define mmCOMPUTE_DISPATCH_ID_BASE_IDX … #define mmCOMPUTE_THREADGROUP_ID … #define mmCOMPUTE_THREADGROUP_ID_BASE_IDX … #define mmCOMPUTE_REQ_CTRL … #define mmCOMPUTE_REQ_CTRL_BASE_IDX … #define mmCOMPUTE_PREF_PRI_ACCUM_0 … #define mmCOMPUTE_PREF_PRI_ACCUM_0_BASE_IDX … #define mmCOMPUTE_USER_ACCUM_0 … #define mmCOMPUTE_USER_ACCUM_0_BASE_IDX … #define mmCOMPUTE_PREF_PRI_ACCUM_1 … #define mmCOMPUTE_PREF_PRI_ACCUM_1_BASE_IDX … #define mmCOMPUTE_USER_ACCUM_1 … #define mmCOMPUTE_USER_ACCUM_1_BASE_IDX … #define mmCOMPUTE_PREF_PRI_ACCUM_2 … #define mmCOMPUTE_PREF_PRI_ACCUM_2_BASE_IDX … #define mmCOMPUTE_USER_ACCUM_2 … #define mmCOMPUTE_USER_ACCUM_2_BASE_IDX … #define mmCOMPUTE_PREF_PRI_ACCUM_3 … #define mmCOMPUTE_PREF_PRI_ACCUM_3_BASE_IDX … #define mmCOMPUTE_USER_ACCUM_3 … #define mmCOMPUTE_USER_ACCUM_3_BASE_IDX … #define mmCOMPUTE_PGM_RSRC3 … #define mmCOMPUTE_PGM_RSRC3_BASE_IDX … #define mmCOMPUTE_DDID_INDEX … #define mmCOMPUTE_DDID_INDEX_BASE_IDX … #define mmCOMPUTE_SHADER_CHKSUM … #define mmCOMPUTE_SHADER_CHKSUM_BASE_IDX … #define mmCOMPUTE_RELAUNCH … #define mmCOMPUTE_RELAUNCH_BASE_IDX … #define mmCOMPUTE_WAVE_RESTORE_ADDR_LO … #define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX … #define mmCOMPUTE_WAVE_RESTORE_ADDR_HI … #define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX … #define mmCOMPUTE_RELAUNCH2 … #define mmCOMPUTE_RELAUNCH2_BASE_IDX … #define mmCOMPUTE_USER_DATA_0 … #define mmCOMPUTE_USER_DATA_0_BASE_IDX … #define mmCOMPUTE_USER_DATA_1 … #define mmCOMPUTE_USER_DATA_1_BASE_IDX … #define mmCOMPUTE_USER_DATA_2 … #define mmCOMPUTE_USER_DATA_2_BASE_IDX … #define mmCOMPUTE_USER_DATA_3 … #define mmCOMPUTE_USER_DATA_3_BASE_IDX … #define mmCOMPUTE_USER_DATA_4 … #define mmCOMPUTE_USER_DATA_4_BASE_IDX … #define mmCOMPUTE_USER_DATA_5 … #define mmCOMPUTE_USER_DATA_5_BASE_IDX … #define mmCOMPUTE_USER_DATA_6 … #define mmCOMPUTE_USER_DATA_6_BASE_IDX … #define mmCOMPUTE_USER_DATA_7 … #define mmCOMPUTE_USER_DATA_7_BASE_IDX … #define mmCOMPUTE_USER_DATA_8 … #define mmCOMPUTE_USER_DATA_8_BASE_IDX … #define mmCOMPUTE_USER_DATA_9 … #define mmCOMPUTE_USER_DATA_9_BASE_IDX … #define mmCOMPUTE_USER_DATA_10 … #define mmCOMPUTE_USER_DATA_10_BASE_IDX … #define mmCOMPUTE_USER_DATA_11 … #define mmCOMPUTE_USER_DATA_11_BASE_IDX … #define mmCOMPUTE_USER_DATA_12 … #define mmCOMPUTE_USER_DATA_12_BASE_IDX … #define mmCOMPUTE_USER_DATA_13 … #define mmCOMPUTE_USER_DATA_13_BASE_IDX … #define mmCOMPUTE_USER_DATA_14 … #define mmCOMPUTE_USER_DATA_14_BASE_IDX … #define mmCOMPUTE_USER_DATA_15 … #define mmCOMPUTE_USER_DATA_15_BASE_IDX … #define mmCOMPUTE_DISPATCH_TUNNEL … #define mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX … #define mmCOMPUTE_DISPATCH_END … #define mmCOMPUTE_DISPATCH_END_BASE_IDX … #define mmCOMPUTE_NOWHERE … #define mmCOMPUTE_NOWHERE_BASE_IDX … // addressBlock: gc_cppdec // base address: 0xc080 #define mmCP_EOPQ_WAIT_TIME … #define mmCP_EOPQ_WAIT_TIME_BASE_IDX … #define mmCP_CPC_MGCG_SYNC_CNTL … #define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX … #define mmCPC_INT_INFO … #define mmCPC_INT_INFO_BASE_IDX … #define mmCP_VIRT_STATUS … #define mmCP_VIRT_STATUS_BASE_IDX … #define mmCPC_INT_ADDR … #define mmCPC_INT_ADDR_BASE_IDX … #define mmCPC_INT_PASID … #define mmCPC_INT_PASID_BASE_IDX … #define mmCP_GFX_ERROR … #define mmCP_GFX_ERROR_BASE_IDX … #define mmCPG_UTCL1_CNTL … #define mmCPG_UTCL1_CNTL_BASE_IDX … #define mmCPC_UTCL1_CNTL … #define mmCPC_UTCL1_CNTL_BASE_IDX … #define mmCPF_UTCL1_CNTL … #define mmCPF_UTCL1_CNTL_BASE_IDX … #define mmCP_AQL_SMM_STATUS … #define mmCP_AQL_SMM_STATUS_BASE_IDX … #define mmCP_RB0_BASE … #define mmCP_RB0_BASE_BASE_IDX … #define mmCP_RB_BASE … #define mmCP_RB_BASE_BASE_IDX … #define mmCP_RB0_CNTL … #define mmCP_RB0_CNTL_BASE_IDX … #define mmCP_RB_CNTL … #define mmCP_RB_CNTL_BASE_IDX … #define mmCP_RB_RPTR_WR … #define mmCP_RB_RPTR_WR_BASE_IDX … #define mmCP_RB0_RPTR_ADDR … #define mmCP_RB0_RPTR_ADDR_BASE_IDX … #define mmCP_RB_RPTR_ADDR … #define mmCP_RB_RPTR_ADDR_BASE_IDX … #define mmCP_RB0_RPTR_ADDR_HI … #define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX … #define mmCP_RB_RPTR_ADDR_HI … #define mmCP_RB_RPTR_ADDR_HI_BASE_IDX … #define mmCP_RB0_BUFSZ_MASK … #define mmCP_RB0_BUFSZ_MASK_BASE_IDX … #define mmCP_RB_BUFSZ_MASK … #define mmCP_RB_BUFSZ_MASK_BASE_IDX … #define mmGC_PRIV_MODE … #define mmGC_PRIV_MODE_BASE_IDX … #define mmCP_INT_CNTL … #define mmCP_INT_CNTL_BASE_IDX … #define mmCP_INT_STATUS … #define mmCP_INT_STATUS_BASE_IDX … #define mmCP_DEVICE_ID … #define mmCP_DEVICE_ID_BASE_IDX … #define mmCP_ME0_PIPE_PRIORITY_CNTS … #define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX … #define mmCP_RING_PRIORITY_CNTS … #define mmCP_RING_PRIORITY_CNTS_BASE_IDX … #define mmCP_ME0_PIPE0_PRIORITY … #define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX … #define mmCP_RING0_PRIORITY … #define mmCP_RING0_PRIORITY_BASE_IDX … #define mmCP_ME0_PIPE1_PRIORITY … #define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX … #define mmCP_RING1_PRIORITY … #define mmCP_RING1_PRIORITY_BASE_IDX … #define mmCP_ME0_PIPE2_PRIORITY … #define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX … #define mmCP_RING2_PRIORITY … #define mmCP_RING2_PRIORITY_BASE_IDX … #define mmCP_FATAL_ERROR … #define mmCP_FATAL_ERROR_BASE_IDX … #define mmCP_RB_VMID … #define mmCP_RB_VMID_BASE_IDX … #define mmCP_ME0_PIPE0_VMID … #define mmCP_ME0_PIPE0_VMID_BASE_IDX … #define mmCP_ME0_PIPE1_VMID … #define mmCP_ME0_PIPE1_VMID_BASE_IDX … #define mmCP_RB0_WPTR … #define mmCP_RB0_WPTR_BASE_IDX … #define mmCP_RB_WPTR … #define mmCP_RB_WPTR_BASE_IDX … #define mmCP_RB0_WPTR_HI … #define mmCP_RB0_WPTR_HI_BASE_IDX … #define mmCP_RB_WPTR_HI … #define mmCP_RB_WPTR_HI_BASE_IDX … #define mmCP_RB1_WPTR … #define mmCP_RB1_WPTR_BASE_IDX … #define mmCP_RB1_WPTR_HI … #define mmCP_RB1_WPTR_HI_BASE_IDX … #define mmCP_RB2_WPTR … #define mmCP_RB2_WPTR_BASE_IDX … #define mmCP_PROCESS_QUANTUM … #define mmCP_PROCESS_QUANTUM_BASE_IDX … #define mmCP_RB_DOORBELL_RANGE_LOWER … #define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX … #define mmCP_RB_DOORBELL_RANGE_UPPER … #define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX … #define mmCP_MEC_DOORBELL_RANGE_LOWER … #define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX … #define mmCP_MEC_DOORBELL_RANGE_UPPER … #define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX … #define mmCPG_UTCL1_ERROR … #define mmCPG_UTCL1_ERROR_BASE_IDX … #define mmCPC_UTCL1_ERROR … #define mmCPC_UTCL1_ERROR_BASE_IDX … #define mmCP_RB1_BASE … #define mmCP_RB1_BASE_BASE_IDX … #define mmCP_RB1_CNTL … #define mmCP_RB1_CNTL_BASE_IDX … #define mmCP_RB1_RPTR_ADDR … #define mmCP_RB1_RPTR_ADDR_BASE_IDX … #define mmCP_RB1_RPTR_ADDR_HI … #define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX … #define mmCP_RB1_BUFSZ_MASK … #define mmCP_RB1_BUFSZ_MASK_BASE_IDX … #define mmCP_RB2_BASE … #define mmCP_RB2_BASE_BASE_IDX … #define mmCP_RB2_CNTL … #define mmCP_RB2_CNTL_BASE_IDX … #define mmCP_RB2_RPTR_ADDR … #define mmCP_RB2_RPTR_ADDR_BASE_IDX … #define mmCP_RB2_RPTR_ADDR_HI … #define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX … #define mmCP_INT_CNTL_RING0 … #define mmCP_INT_CNTL_RING0_BASE_IDX … #define mmCP_INT_CNTL_RING1 … #define mmCP_INT_CNTL_RING1_BASE_IDX … #define mmCP_INT_CNTL_RING2 … #define mmCP_INT_CNTL_RING2_BASE_IDX … #define mmCP_INT_STATUS_RING0 … #define mmCP_INT_STATUS_RING0_BASE_IDX … #define mmCP_INT_STATUS_RING1 … #define mmCP_INT_STATUS_RING1_BASE_IDX … #define mmCP_INT_STATUS_RING2 … #define mmCP_INT_STATUS_RING2_BASE_IDX … #define mmCP_PWR_CNTL … #define mmCP_PWR_CNTL_BASE_IDX … #define mmCP_MEM_SLP_CNTL … #define mmCP_MEM_SLP_CNTL_BASE_IDX … #define mmCP_ECC_FIRSTOCCURRENCE … #define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX … #define mmCP_ECC_FIRSTOCCURRENCE_RING0 … #define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX … #define mmCP_ECC_FIRSTOCCURRENCE_RING1 … #define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX … #define mmCP_ECC_FIRSTOCCURRENCE_RING2 … #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX … #define mmGB_EDC_MODE … #define mmGB_EDC_MODE_BASE_IDX … #define mmCP_DEBUG … #define mmCP_DEBUG_BASE_IDX … #define mmCP_FETCHER_SOURCE … #define mmCP_FETCHER_SOURCE_BASE_IDX … #define mmCP_PQ_WPTR_POLL_CNTL … #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX … #define mmCP_PQ_WPTR_POLL_CNTL1 … #define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX … #define mmCP_ME1_PIPE0_INT_CNTL … #define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX … #define mmCP_ME1_PIPE1_INT_CNTL … #define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX … #define mmCP_ME1_PIPE2_INT_CNTL … #define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX … #define mmCP_ME1_PIPE3_INT_CNTL … #define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX … #define mmCP_ME2_PIPE0_INT_CNTL … #define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX … #define mmCP_ME2_PIPE1_INT_CNTL … #define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX … #define mmCP_ME2_PIPE2_INT_CNTL … #define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX … #define mmCP_ME2_PIPE3_INT_CNTL … #define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX … #define mmCP_ME1_PIPE0_INT_STATUS … #define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX … #define mmCP_ME1_PIPE1_INT_STATUS … #define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX … #define mmCP_ME1_PIPE2_INT_STATUS … #define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX … #define mmCP_ME1_PIPE3_INT_STATUS … #define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX … #define mmCP_ME2_PIPE0_INT_STATUS … #define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX … #define mmCP_ME2_PIPE1_INT_STATUS … #define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX … #define mmCP_ME2_PIPE2_INT_STATUS … #define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX … #define mmCP_ME2_PIPE3_INT_STATUS … #define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX … #define mmCP_ME1_INT_STAT_DEBUG … #define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX … #define mmCP_ME2_INT_STAT_DEBUG … #define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX … #define mmCP_GFX_QUEUE_INDEX … #define mmCP_GFX_QUEUE_INDEX_BASE_IDX … #define mmCC_GC_EDC_CONFIG … #define mmCC_GC_EDC_CONFIG_BASE_IDX … #define mmCP_ME1_PIPE_PRIORITY_CNTS … #define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX … #define mmCP_ME1_PIPE0_PRIORITY … #define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX … #define mmCP_ME1_PIPE1_PRIORITY … #define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX … #define mmCP_ME1_PIPE2_PRIORITY … #define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX … #define mmCP_ME1_PIPE3_PRIORITY … #define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX … #define mmCP_ME2_PIPE_PRIORITY_CNTS … #define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX … #define mmCP_ME2_PIPE0_PRIORITY … #define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX … #define mmCP_ME2_PIPE1_PRIORITY … #define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX … #define mmCP_ME2_PIPE2_PRIORITY … #define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX … #define mmCP_ME2_PIPE3_PRIORITY … #define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX … #define mmCP_CE_PRGRM_CNTR_START … #define mmCP_CE_PRGRM_CNTR_START_BASE_IDX … #define mmCP_PFP_PRGRM_CNTR_START … #define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX … #define mmCP_ME_PRGRM_CNTR_START … #define mmCP_ME_PRGRM_CNTR_START_BASE_IDX … #define mmCP_MEC1_PRGRM_CNTR_START … #define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX … #define mmCP_MEC2_PRGRM_CNTR_START … #define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX … #define mmCP_CE_INTR_ROUTINE_START … #define mmCP_CE_INTR_ROUTINE_START_BASE_IDX … #define mmCP_PFP_INTR_ROUTINE_START … #define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX … #define mmCP_ME_INTR_ROUTINE_START … #define mmCP_ME_INTR_ROUTINE_START_BASE_IDX … #define mmCP_MEC1_INTR_ROUTINE_START … #define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX … #define mmCP_MEC2_INTR_ROUTINE_START … #define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX … #define mmCP_CONTEXT_CNTL … #define mmCP_CONTEXT_CNTL_BASE_IDX … #define mmCP_MAX_CONTEXT … #define mmCP_MAX_CONTEXT_BASE_IDX … #define mmCP_IQ_WAIT_TIME1 … #define mmCP_IQ_WAIT_TIME1_BASE_IDX … #define mmCP_IQ_WAIT_TIME2 … #define mmCP_IQ_WAIT_TIME2_BASE_IDX … #define mmCP_RB0_BASE_HI … #define mmCP_RB0_BASE_HI_BASE_IDX … #define mmCP_RB1_BASE_HI … #define mmCP_RB1_BASE_HI_BASE_IDX … #define mmCP_VMID_RESET … #define mmCP_VMID_RESET_BASE_IDX … #define mmCPC_INT_CNTL … #define mmCPC_INT_CNTL_BASE_IDX … #define mmCPC_INT_STATUS … #define mmCPC_INT_STATUS_BASE_IDX … #define mmCP_VMID_PREEMPT … #define mmCP_VMID_PREEMPT_BASE_IDX … #define mmCPC_INT_CNTX_ID … #define mmCPC_INT_CNTX_ID_BASE_IDX … #define mmCP_PQ_STATUS … #define mmCP_PQ_STATUS_BASE_IDX … #define mmCP_CE_CS_PARTITION_INDEX … #define mmCP_CE_CS_PARTITION_INDEX_BASE_IDX … #define mmCP_MEC1_F32_INT_DIS … #define mmCP_MEC1_F32_INT_DIS_BASE_IDX … #define mmCP_MEC2_F32_INT_DIS … #define mmCP_MEC2_F32_INT_DIS_BASE_IDX … #define mmCP_VMID_STATUS … #define mmCP_VMID_STATUS_BASE_IDX … #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO … #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX … #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI … #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX … #define mmCPC_SUSPEND_CTX_SAVE_CONTROL … #define mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX … #define mmCPC_SUSPEND_CNTL_STACK_OFFSET … #define mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX … #define mmCPC_SUSPEND_CNTL_STACK_SIZE … #define mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX … #define mmCPC_SUSPEND_WG_STATE_OFFSET … #define mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX … #define mmCPC_SUSPEND_CTX_SAVE_SIZE … #define mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX … #define mmCPC_OS_PIPES … #define mmCPC_OS_PIPES_BASE_IDX … #define mmCP_SUSPEND_RESUME_REQ … #define mmCP_SUSPEND_RESUME_REQ_BASE_IDX … #define mmCP_SUSPEND_CNTL … #define mmCP_SUSPEND_CNTL_BASE_IDX … #define mmCP_IQ_WAIT_TIME3 … #define mmCP_IQ_WAIT_TIME3_BASE_IDX … #define mmCPC_DDID_BASE_ADDR_LO … #define mmCPC_DDID_BASE_ADDR_LO_BASE_IDX … #define mmCP_DDID_BASE_ADDR_LO … #define mmCP_DDID_BASE_ADDR_LO_BASE_IDX … #define mmCPC_DDID_BASE_ADDR_HI … #define mmCPC_DDID_BASE_ADDR_HI_BASE_IDX … #define mmCP_DDID_BASE_ADDR_HI … #define mmCP_DDID_BASE_ADDR_HI_BASE_IDX … #define mmCPC_DDID_CNTL … #define mmCPC_DDID_CNTL_BASE_IDX … #define mmCP_DDID_CNTL … #define mmCP_DDID_CNTL_BASE_IDX … #define mmCP_GFX_DDID_INFLIGHT_COUNT … #define mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX … #define mmCP_GFX_DDID_WPTR … #define mmCP_GFX_DDID_WPTR_BASE_IDX … #define mmCP_GFX_DDID_RPTR … #define mmCP_GFX_DDID_RPTR_BASE_IDX … #define mmCP_GFX_DDID_DELTA_RPT_COUNT … #define mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX … #define mmCP_GFX_HPD_STATUS0 … #define mmCP_GFX_HPD_STATUS0_BASE_IDX … #define mmCP_GFX_HPD_CONTROL0 … #define mmCP_GFX_HPD_CONTROL0_BASE_IDX … #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO … #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX … #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI … #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX … #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO … #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX … #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI … #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX … #define mmCP_GFX_INDEX_MUTEX … #define mmCP_GFX_INDEX_MUTEX_BASE_IDX … #define mmCP_GFX_MQD_BASE_ADDR … #define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX … #define mmCP_GFX_MQD_BASE_ADDR_HI … #define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX … #define mmCP_GFX_HQD_ACTIVE … #define mmCP_GFX_HQD_ACTIVE_BASE_IDX … #define mmCP_GFX_HQD_VMID … #define mmCP_GFX_HQD_VMID_BASE_IDX … #define mmCP_GFX_HQD_QUEUE_PRIORITY … #define mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX … #define mmCP_GFX_HQD_QUANTUM … #define mmCP_GFX_HQD_QUANTUM_BASE_IDX … #define mmCP_GFX_HQD_BASE … #define mmCP_GFX_HQD_BASE_BASE_IDX … #define mmCP_GFX_HQD_BASE_HI … #define mmCP_GFX_HQD_BASE_HI_BASE_IDX … #define mmCP_GFX_HQD_RPTR … #define mmCP_GFX_HQD_RPTR_BASE_IDX … #define mmCP_GFX_HQD_RPTR_ADDR … #define mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX … #define mmCP_GFX_HQD_RPTR_ADDR_HI … #define mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX … #define mmCP_RB_WPTR_POLL_ADDR_LO … #define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmCP_RB_WPTR_POLL_ADDR_HI … #define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmCP_RB_DOORBELL_CONTROL … #define mmCP_RB_DOORBELL_CONTROL_BASE_IDX … #define mmCP_GFX_HQD_OFFSET … #define mmCP_GFX_HQD_OFFSET_BASE_IDX … #define mmCP_GFX_HQD_CNTL … #define mmCP_GFX_HQD_CNTL_BASE_IDX … #define mmCP_GFX_HQD_CSMD_RPTR … #define mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX … #define mmCP_GFX_HQD_WPTR … #define mmCP_GFX_HQD_WPTR_BASE_IDX … #define mmCP_GFX_HQD_WPTR_HI … #define mmCP_GFX_HQD_WPTR_HI_BASE_IDX … #define mmCP_GFX_HQD_DEQUEUE_REQUEST … #define mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX … #define mmCP_GFX_HQD_MAPPED … #define mmCP_GFX_HQD_MAPPED_BASE_IDX … #define mmCP_GFX_HQD_QUE_MGR_CONTROL … #define mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX … #define mmCP_GFX_HQD_HQ_STATUS0 … #define mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX … #define mmCP_GFX_HQD_HQ_CONTROL0 … #define mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX … #define mmCP_GFX_MQD_CONTROL … #define mmCP_GFX_MQD_CONTROL_BASE_IDX … #define mmCP_HQD_GFX_CONTROL … #define mmCP_HQD_GFX_CONTROL_BASE_IDX … #define mmCP_HQD_GFX_STATUS … #define mmCP_HQD_GFX_STATUS_BASE_IDX … #define mmCP_GFX_HQD_CE_RPTR_WR … #define mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX … #define mmCP_GFX_HQD_CE_BASE … #define mmCP_GFX_HQD_CE_BASE_BASE_IDX … #define mmCP_GFX_HQD_CE_BASE_HI … #define mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX … #define mmCP_GFX_HQD_CE_RPTR … #define mmCP_GFX_HQD_CE_RPTR_BASE_IDX … #define mmCP_GFX_HQD_CE_RPTR_ADDR … #define mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX … #define mmCP_GFX_HQD_CE_RPTR_ADDR_HI … #define mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX … #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO … #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX … #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI … #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmCP_GFX_HQD_CE_OFFSET … #define mmCP_GFX_HQD_CE_OFFSET_BASE_IDX … #define mmCP_GFX_HQD_CE_CNTL … #define mmCP_GFX_HQD_CE_CNTL_BASE_IDX … #define mmCP_GFX_HQD_CE_CSMD_RPTR … #define mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX … #define mmCP_GFX_HQD_CE_WPTR … #define mmCP_GFX_HQD_CE_WPTR_BASE_IDX … #define mmCP_GFX_HQD_CE_WPTR_HI … #define mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX … #define mmCP_CE_DOORBELL_CONTROL … #define mmCP_CE_DOORBELL_CONTROL_BASE_IDX … #define mmCP_DMA_WATCH0_ADDR_LO … #define mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX … #define mmCP_DMA_WATCH0_ADDR_HI … #define mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX … #define mmCP_DMA_WATCH0_MASK … #define mmCP_DMA_WATCH0_MASK_BASE_IDX … #define mmCP_DMA_WATCH0_CNTL … #define mmCP_DMA_WATCH0_CNTL_BASE_IDX … #define mmCP_DMA_WATCH1_ADDR_LO … #define mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX … #define mmCP_DMA_WATCH1_ADDR_HI … #define mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX … #define mmCP_DMA_WATCH1_MASK … #define mmCP_DMA_WATCH1_MASK_BASE_IDX … #define mmCP_DMA_WATCH1_CNTL … #define mmCP_DMA_WATCH1_CNTL_BASE_IDX … #define mmCP_DMA_WATCH2_ADDR_LO … #define mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX … #define mmCP_DMA_WATCH2_ADDR_HI … #define mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX … #define mmCP_DMA_WATCH2_MASK … #define mmCP_DMA_WATCH2_MASK_BASE_IDX … #define mmCP_DMA_WATCH2_CNTL … #define mmCP_DMA_WATCH2_CNTL_BASE_IDX … #define mmCP_DMA_WATCH3_ADDR_LO … #define mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX … #define mmCP_DMA_WATCH3_ADDR_HI … #define mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX … #define mmCP_DMA_WATCH3_MASK … #define mmCP_DMA_WATCH3_MASK_BASE_IDX … #define mmCP_DMA_WATCH3_CNTL … #define mmCP_DMA_WATCH3_CNTL_BASE_IDX … #define mmCP_DMA_WATCH_STAT_ADDR_LO … #define mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX … #define mmCP_DMA_WATCH_STAT_ADDR_HI … #define mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX … #define mmCP_DMA_WATCH_STAT … #define mmCP_DMA_WATCH_STAT_BASE_IDX … #define mmCP_PFP_JT_STAT … #define mmCP_PFP_JT_STAT_BASE_IDX … #define mmCP_CE_JT_STAT … #define mmCP_CE_JT_STAT_BASE_IDX … #define mmCP_MEC_JT_STAT … #define mmCP_MEC_JT_STAT_BASE_IDX … #define mmCP_RB_DOORBELL_CLEAR … #define mmCP_RB_DOORBELL_CLEAR_BASE_IDX … #define mmCP_RB0_ACTIVE … #define mmCP_RB0_ACTIVE_BASE_IDX … #define mmCP_RB_ACTIVE … #define mmCP_RB_ACTIVE_BASE_IDX … #define mmCP_RB1_ACTIVE … #define mmCP_RB1_ACTIVE_BASE_IDX … #define mmCP_RB_STATUS … #define mmCP_RB_STATUS_BASE_IDX … #define mmCPG_RCIU_CAM_INDEX … #define mmCPG_RCIU_CAM_INDEX_BASE_IDX … #define mmCPG_RCIU_CAM_DATA … #define mmCPG_RCIU_CAM_DATA_BASE_IDX … #define mmCPG_RCIU_CAM_DATA_PHASE0 … #define mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX … #define mmCPG_RCIU_CAM_DATA_PHASE1 … #define mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX … #define mmCPG_RCIU_CAM_DATA_PHASE2 … #define mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX … #define mmCPF_GCR_CNTL … #define mmCPF_GCR_CNTL_BASE_IDX … #define mmCPG_UTCL1_STATUS … #define mmCPG_UTCL1_STATUS_BASE_IDX … #define mmCPC_UTCL1_STATUS … #define mmCPC_UTCL1_STATUS_BASE_IDX … #define mmCPF_UTCL1_STATUS … #define mmCPF_UTCL1_STATUS_BASE_IDX … #define mmCP_SD_CNTL … #define mmCP_SD_CNTL_BASE_IDX … #define mmCP_SOFT_RESET_CNTL … #define mmCP_SOFT_RESET_CNTL_BASE_IDX … #define mmCP_CPC_GFX_CNTL … #define mmCP_CPC_GFX_CNTL_BASE_IDX … // addressBlock: gc_spipdec // base address: 0xc700 #define mmSPI_ARB_PRIORITY … #define mmSPI_ARB_PRIORITY_BASE_IDX … #define mmSPI_ARB_CYCLES_0 … #define mmSPI_ARB_CYCLES_0_BASE_IDX … #define mmSPI_ARB_CYCLES_1 … #define mmSPI_ARB_CYCLES_1_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_GFX … #define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_HP3D … #define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_CS0 … #define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_CS1 … #define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_CS2 … #define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_CS3 … #define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_CS4 … #define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_CS5 … #define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_CS6 … #define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX … #define mmSPI_WCL_PIPE_PERCENT_CS7 … #define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX … #define mmSPI_GDBG_WAVE_CNTL … #define mmSPI_GDBG_WAVE_CNTL_BASE_IDX … #define mmSPI_GDBG_TRAP_CONFIG … #define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX … #define mmSPI_GDBG_TRAP_MASK … #define mmSPI_GDBG_TRAP_MASK_BASE_IDX … #define mmSPI_GDBG_WAVE_CNTL2 … #define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX … #define mmSPI_GDBG_WAVE_CNTL3 … #define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX … #define mmSPI_GDBG_TRAP_DATA0 … #define mmSPI_GDBG_TRAP_DATA0_BASE_IDX … #define mmSPI_GDBG_TRAP_DATA1 … #define mmSPI_GDBG_TRAP_DATA1_BASE_IDX … #define mmSPI_COMPUTE_QUEUE_RESET … #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_0 … #define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_1 … #define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_2 … #define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_3 … #define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_4 … #define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_5 … #define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_6 … #define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_7 … #define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_8 … #define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_9 … #define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_0 … #define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_1 … #define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_2 … #define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_3 … #define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_4 … #define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_5 … #define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_6 … #define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_7 … #define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_8 … #define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_9 … #define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_10 … #define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_11 … #define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_10 … #define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_11 … #define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_12 … #define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_13 … #define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_14 … #define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_CU_15 … #define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_12 … #define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_13 … #define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_14 … #define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX … #define mmSPI_RESOURCE_RESERVE_EN_CU_15 … #define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX … #define mmSPI_COMPUTE_WF_CTX_SAVE … #define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX … #define mmSPI_ARB_CNTL_0 … #define mmSPI_ARB_CNTL_0_BASE_IDX … #define mmSPI_FEATURE_CTRL … #define mmSPI_FEATURE_CTRL_BASE_IDX … #define mmSPI_SHADER_RSRC_LIMIT_CTRL … #define mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX … // addressBlock: gc_cpphqddec // base address: 0xc800 #define mmCP_HPD_MES_ROQ_OFFSETS … #define mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX … #define mmCP_HPD_ROQ_OFFSETS … #define mmCP_HPD_ROQ_OFFSETS_BASE_IDX … #define mmCP_HPD_STATUS0 … #define mmCP_HPD_STATUS0_BASE_IDX … #define mmCP_HPD_UTCL1_CNTL … #define mmCP_HPD_UTCL1_CNTL_BASE_IDX … #define mmCP_HPD_UTCL1_ERROR … #define mmCP_HPD_UTCL1_ERROR_BASE_IDX … #define mmCP_HPD_UTCL1_ERROR_ADDR … #define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX … #define mmCP_MQD_BASE_ADDR … #define mmCP_MQD_BASE_ADDR_BASE_IDX … #define mmCP_MQD_BASE_ADDR_HI … #define mmCP_MQD_BASE_ADDR_HI_BASE_IDX … #define mmCP_HQD_ACTIVE … #define mmCP_HQD_ACTIVE_BASE_IDX … #define mmCP_HQD_VMID … #define mmCP_HQD_VMID_BASE_IDX … #define mmCP_HQD_PERSISTENT_STATE … #define mmCP_HQD_PERSISTENT_STATE_BASE_IDX … #define mmCP_HQD_PIPE_PRIORITY … #define mmCP_HQD_PIPE_PRIORITY_BASE_IDX … #define mmCP_HQD_QUEUE_PRIORITY … #define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX … #define mmCP_HQD_QUANTUM … #define mmCP_HQD_QUANTUM_BASE_IDX … #define mmCP_HQD_PQ_BASE … #define mmCP_HQD_PQ_BASE_BASE_IDX … #define mmCP_HQD_PQ_BASE_HI … #define mmCP_HQD_PQ_BASE_HI_BASE_IDX … #define mmCP_HQD_PQ_RPTR … #define mmCP_HQD_PQ_RPTR_BASE_IDX … #define mmCP_HQD_PQ_RPTR_REPORT_ADDR … #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX … #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI … #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX … #define mmCP_HQD_PQ_WPTR_POLL_ADDR … #define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX … #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI … #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX … #define mmCP_HQD_PQ_DOORBELL_CONTROL … #define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX … #define mmCP_HQD_PQ_CONTROL … #define mmCP_HQD_PQ_CONTROL_BASE_IDX … #define mmCP_HQD_IB_BASE_ADDR … #define mmCP_HQD_IB_BASE_ADDR_BASE_IDX … #define mmCP_HQD_IB_BASE_ADDR_HI … #define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX … #define mmCP_HQD_IB_RPTR … #define mmCP_HQD_IB_RPTR_BASE_IDX … #define mmCP_HQD_IB_CONTROL … #define mmCP_HQD_IB_CONTROL_BASE_IDX … #define mmCP_HQD_IQ_TIMER … #define mmCP_HQD_IQ_TIMER_BASE_IDX … #define mmCP_HQD_IQ_RPTR … #define mmCP_HQD_IQ_RPTR_BASE_IDX … #define mmCP_HQD_DEQUEUE_REQUEST … #define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX … #define mmCP_HQD_DMA_OFFLOAD … #define mmCP_HQD_DMA_OFFLOAD_BASE_IDX … #define mmCP_HQD_OFFLOAD … #define mmCP_HQD_OFFLOAD_BASE_IDX … #define mmCP_HQD_SEMA_CMD … #define mmCP_HQD_SEMA_CMD_BASE_IDX … #define mmCP_HQD_MSG_TYPE … #define mmCP_HQD_MSG_TYPE_BASE_IDX … #define mmCP_HQD_ATOMIC0_PREOP_LO … #define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX … #define mmCP_HQD_ATOMIC0_PREOP_HI … #define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX … #define mmCP_HQD_ATOMIC1_PREOP_LO … #define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX … #define mmCP_HQD_ATOMIC1_PREOP_HI … #define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX … #define mmCP_HQD_HQ_SCHEDULER0 … #define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX … #define mmCP_HQD_HQ_STATUS0 … #define mmCP_HQD_HQ_STATUS0_BASE_IDX … #define mmCP_HQD_HQ_CONTROL0 … #define mmCP_HQD_HQ_CONTROL0_BASE_IDX … #define mmCP_HQD_HQ_SCHEDULER1 … #define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX … #define mmCP_MQD_CONTROL … #define mmCP_MQD_CONTROL_BASE_IDX … #define mmCP_HQD_HQ_STATUS1 … #define mmCP_HQD_HQ_STATUS1_BASE_IDX … #define mmCP_HQD_HQ_CONTROL1 … #define mmCP_HQD_HQ_CONTROL1_BASE_IDX … #define mmCP_HQD_EOP_BASE_ADDR … #define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX … #define mmCP_HQD_EOP_BASE_ADDR_HI … #define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX … #define mmCP_HQD_EOP_CONTROL … #define mmCP_HQD_EOP_CONTROL_BASE_IDX … #define mmCP_HQD_EOP_RPTR … #define mmCP_HQD_EOP_RPTR_BASE_IDX … #define mmCP_HQD_EOP_WPTR … #define mmCP_HQD_EOP_WPTR_BASE_IDX … #define mmCP_HQD_EOP_EVENTS … #define mmCP_HQD_EOP_EVENTS_BASE_IDX … #define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO … #define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX … #define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI … #define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX … #define mmCP_HQD_CTX_SAVE_CONTROL … #define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX … #define mmCP_HQD_CNTL_STACK_OFFSET … #define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX … #define mmCP_HQD_CNTL_STACK_SIZE … #define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX … #define mmCP_HQD_WG_STATE_OFFSET … #define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX … #define mmCP_HQD_CTX_SAVE_SIZE … #define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX … #define mmCP_HQD_GDS_RESOURCE_STATE … #define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX … #define mmCP_HQD_ERROR … #define mmCP_HQD_ERROR_BASE_IDX … #define mmCP_HQD_EOP_WPTR_MEM … #define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX … #define mmCP_HQD_AQL_CONTROL … #define mmCP_HQD_AQL_CONTROL_BASE_IDX … #define mmCP_HQD_PQ_WPTR_LO … #define mmCP_HQD_PQ_WPTR_LO_BASE_IDX … #define mmCP_HQD_PQ_WPTR_HI … #define mmCP_HQD_PQ_WPTR_HI_BASE_IDX … #define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET … #define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX … #define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT … #define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX … #define mmCP_HQD_SUSPEND_WG_STATE_OFFSET … #define mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX … #define mmCP_HQD_DDID_RPTR … #define mmCP_HQD_DDID_RPTR_BASE_IDX … #define mmCP_HQD_DDID_WPTR … #define mmCP_HQD_DDID_WPTR_BASE_IDX … #define mmCP_HQD_DDID_INFLIGHT_COUNT … #define mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX … #define mmCP_HQD_DDID_DELTA_RPT_COUNT … #define mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX … #define mmCP_HQD_DEQUEUE_STATUS … #define mmCP_HQD_DEQUEUE_STATUS_BASE_IDX … // addressBlock: gc_didtdec // base address: 0xca00 #define mmDIDT_IND_INDEX … #define mmDIDT_IND_INDEX_BASE_IDX … #define mmDIDT_IND_DATA … #define mmDIDT_IND_DATA_BASE_IDX … #define mmDIDT_INDEX_AUTO_INCR_EN … #define mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX … // addressBlock: gc_gccacdec // base address: 0xca10 #define mmGC_CAC_CTRL_1 … #define mmGC_CAC_CTRL_1_BASE_IDX … #define mmGC_CAC_CTRL_2 … #define mmGC_CAC_CTRL_2_BASE_IDX … #define mmGC_CAC_AGGR_LOWER … #define mmGC_CAC_AGGR_LOWER_BASE_IDX … #define mmGC_CAC_AGGR_UPPER … #define mmGC_CAC_AGGR_UPPER_BASE_IDX … #define mmGC_CAC_SOFT_CTRL … #define mmGC_CAC_SOFT_CTRL_BASE_IDX … #define mmGC_DIDT_CTRL0 … #define mmGC_DIDT_CTRL0_BASE_IDX … #define mmGC_DIDT_CTRL1 … #define mmGC_DIDT_CTRL1_BASE_IDX … #define mmGC_DIDT_CTRL2 … #define mmGC_DIDT_CTRL2_BASE_IDX … #define mmGC_DIDT_WEIGHT … #define mmGC_DIDT_WEIGHT_BASE_IDX … #define mmGC_THROTTLE_CTRL … #define mmGC_THROTTLE_CTRL_BASE_IDX … #define mmGC_EDC_CTRL … #define mmGC_EDC_CTRL_BASE_IDX … #define mmGC_EDC_THRESHOLD … #define mmGC_EDC_THRESHOLD_BASE_IDX … #define mmGC_EDC_STATUS … #define mmGC_EDC_STATUS_BASE_IDX … #define mmGC_EDC_OVERFLOW … #define mmGC_EDC_OVERFLOW_BASE_IDX … #define mmGC_EDC_ROLLING_POWER_DELTA … #define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX … #define mmGC_THROTTLE_CTRL1 … #define mmGC_THROTTLE_CTRL1_BASE_IDX … #define mmGC_THROTTLE_STATUS … #define mmGC_THROTTLE_STATUS_BASE_IDX … #define mmEDC_PERF_COUNTER … #define mmEDC_PERF_COUNTER_BASE_IDX … #define mmPCC_PERF_COUNTER … #define mmPCC_PERF_COUNTER_BASE_IDX … #define mmPWRBRK_PERF_COUNTER … #define mmPWRBRK_PERF_COUNTER_BASE_IDX … #define mmGC_CAC_IND_INDEX … #define mmGC_CAC_IND_INDEX_BASE_IDX … #define mmGC_CAC_IND_DATA … #define mmGC_CAC_IND_DATA_BASE_IDX … #define mmSE_CAC_IND_INDEX … #define mmSE_CAC_IND_INDEX_BASE_IDX … #define mmSE_CAC_IND_DATA … #define mmSE_CAC_IND_DATA_BASE_IDX … // addressBlock: gc_tcpdec // base address: 0xca80 #define mmTCP_WATCH0_ADDR_H … #define mmTCP_WATCH0_ADDR_H_BASE_IDX … #define mmTCP_WATCH0_ADDR_L … #define mmTCP_WATCH0_ADDR_L_BASE_IDX … #define mmTCP_WATCH0_CNTL … #define mmTCP_WATCH0_CNTL_BASE_IDX … #define mmTCP_WATCH1_ADDR_H … #define mmTCP_WATCH1_ADDR_H_BASE_IDX … #define mmTCP_WATCH1_ADDR_L … #define mmTCP_WATCH1_ADDR_L_BASE_IDX … #define mmTCP_WATCH1_CNTL … #define mmTCP_WATCH1_CNTL_BASE_IDX … #define mmTCP_WATCH2_ADDR_H … #define mmTCP_WATCH2_ADDR_H_BASE_IDX … #define mmTCP_WATCH2_ADDR_L … #define mmTCP_WATCH2_ADDR_L_BASE_IDX … #define mmTCP_WATCH2_CNTL … #define mmTCP_WATCH2_CNTL_BASE_IDX … #define mmTCP_WATCH3_ADDR_H … #define mmTCP_WATCH3_ADDR_H_BASE_IDX … #define mmTCP_WATCH3_ADDR_L … #define mmTCP_WATCH3_ADDR_L_BASE_IDX … #define mmTCP_WATCH3_CNTL … #define mmTCP_WATCH3_CNTL_BASE_IDX … #define mmTCP_CNTL2 … #define mmTCP_CNTL2_BASE_IDX … #define mmTCP_UTCL0_CNTL1 … #define mmTCP_UTCL0_CNTL1_BASE_IDX … #define mmTCP_UTCL0_CNTL2 … #define mmTCP_UTCL0_CNTL2_BASE_IDX … #define mmTCP_UTCL0_STATUS … #define mmTCP_UTCL0_STATUS_BASE_IDX … #define mmTCP_PERFCOUNTER_FILTER … #define mmTCP_PERFCOUNTER_FILTER_BASE_IDX … #define mmTCP_PERFCOUNTER_FILTER_EN … #define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX … #define mmTCP_PERFCOUNTER_FILTER2 … #define mmTCP_PERFCOUNTER_FILTER2_BASE_IDX … // addressBlock: gc_gdspdec // base address: 0xcc00 #define mmGDS_VMID0_BASE … #define mmGDS_VMID0_BASE_BASE_IDX … #define mmGDS_VMID0_SIZE … #define mmGDS_VMID0_SIZE_BASE_IDX … #define mmGDS_VMID1_BASE … #define mmGDS_VMID1_BASE_BASE_IDX … #define mmGDS_VMID1_SIZE … #define mmGDS_VMID1_SIZE_BASE_IDX … #define mmGDS_VMID2_BASE … #define mmGDS_VMID2_BASE_BASE_IDX … #define mmGDS_VMID2_SIZE … #define mmGDS_VMID2_SIZE_BASE_IDX … #define mmGDS_VMID3_BASE … #define mmGDS_VMID3_BASE_BASE_IDX … #define mmGDS_VMID3_SIZE … #define mmGDS_VMID3_SIZE_BASE_IDX … #define mmGDS_VMID4_BASE … #define mmGDS_VMID4_BASE_BASE_IDX … #define mmGDS_VMID4_SIZE … #define mmGDS_VMID4_SIZE_BASE_IDX … #define mmGDS_VMID5_BASE … #define mmGDS_VMID5_BASE_BASE_IDX … #define mmGDS_VMID5_SIZE … #define mmGDS_VMID5_SIZE_BASE_IDX … #define mmGDS_VMID6_BASE … #define mmGDS_VMID6_BASE_BASE_IDX … #define mmGDS_VMID6_SIZE … #define mmGDS_VMID6_SIZE_BASE_IDX … #define mmGDS_VMID7_BASE … #define mmGDS_VMID7_BASE_BASE_IDX … #define mmGDS_VMID7_SIZE … #define mmGDS_VMID7_SIZE_BASE_IDX … #define mmGDS_VMID8_BASE … #define mmGDS_VMID8_BASE_BASE_IDX … #define mmGDS_VMID8_SIZE … #define mmGDS_VMID8_SIZE_BASE_IDX … #define mmGDS_VMID9_BASE … #define mmGDS_VMID9_BASE_BASE_IDX … #define mmGDS_VMID9_SIZE … #define mmGDS_VMID9_SIZE_BASE_IDX … #define mmGDS_VMID10_BASE … #define mmGDS_VMID10_BASE_BASE_IDX … #define mmGDS_VMID10_SIZE … #define mmGDS_VMID10_SIZE_BASE_IDX … #define mmGDS_VMID11_BASE … #define mmGDS_VMID11_BASE_BASE_IDX … #define mmGDS_VMID11_SIZE … #define mmGDS_VMID11_SIZE_BASE_IDX … #define mmGDS_VMID12_BASE … #define mmGDS_VMID12_BASE_BASE_IDX … #define mmGDS_VMID12_SIZE … #define mmGDS_VMID12_SIZE_BASE_IDX … #define mmGDS_VMID13_BASE … #define mmGDS_VMID13_BASE_BASE_IDX … #define mmGDS_VMID13_SIZE … #define mmGDS_VMID13_SIZE_BASE_IDX … #define mmGDS_VMID14_BASE … #define mmGDS_VMID14_BASE_BASE_IDX … #define mmGDS_VMID14_SIZE … #define mmGDS_VMID14_SIZE_BASE_IDX … #define mmGDS_VMID15_BASE … #define mmGDS_VMID15_BASE_BASE_IDX … #define mmGDS_VMID15_SIZE … #define mmGDS_VMID15_SIZE_BASE_IDX … #define mmGDS_GWS_VMID0 … #define mmGDS_GWS_VMID0_BASE_IDX … #define mmGDS_GWS_VMID1 … #define mmGDS_GWS_VMID1_BASE_IDX … #define mmGDS_GWS_VMID2 … #define mmGDS_GWS_VMID2_BASE_IDX … #define mmGDS_GWS_VMID3 … #define mmGDS_GWS_VMID3_BASE_IDX … #define mmGDS_GWS_VMID4 … #define mmGDS_GWS_VMID4_BASE_IDX … #define mmGDS_GWS_VMID5 … #define mmGDS_GWS_VMID5_BASE_IDX … #define mmGDS_GWS_VMID6 … #define mmGDS_GWS_VMID6_BASE_IDX … #define mmGDS_GWS_VMID7 … #define mmGDS_GWS_VMID7_BASE_IDX … #define mmGDS_GWS_VMID8 … #define mmGDS_GWS_VMID8_BASE_IDX … #define mmGDS_GWS_VMID9 … #define mmGDS_GWS_VMID9_BASE_IDX … #define mmGDS_GWS_VMID10 … #define mmGDS_GWS_VMID10_BASE_IDX … #define mmGDS_GWS_VMID11 … #define mmGDS_GWS_VMID11_BASE_IDX … #define mmGDS_GWS_VMID12 … #define mmGDS_GWS_VMID12_BASE_IDX … #define mmGDS_GWS_VMID13 … #define mmGDS_GWS_VMID13_BASE_IDX … #define mmGDS_GWS_VMID14 … #define mmGDS_GWS_VMID14_BASE_IDX … #define mmGDS_GWS_VMID15 … #define mmGDS_GWS_VMID15_BASE_IDX … #define mmGDS_OA_VMID0 … #define mmGDS_OA_VMID0_BASE_IDX … #define mmGDS_OA_VMID1 … #define mmGDS_OA_VMID1_BASE_IDX … #define mmGDS_OA_VMID2 … #define mmGDS_OA_VMID2_BASE_IDX … #define mmGDS_OA_VMID3 … #define mmGDS_OA_VMID3_BASE_IDX … #define mmGDS_OA_VMID4 … #define mmGDS_OA_VMID4_BASE_IDX … #define mmGDS_OA_VMID5 … #define mmGDS_OA_VMID5_BASE_IDX … #define mmGDS_OA_VMID6 … #define mmGDS_OA_VMID6_BASE_IDX … #define mmGDS_OA_VMID7 … #define mmGDS_OA_VMID7_BASE_IDX … #define mmGDS_OA_VMID8 … #define mmGDS_OA_VMID8_BASE_IDX … #define mmGDS_OA_VMID9 … #define mmGDS_OA_VMID9_BASE_IDX … #define mmGDS_OA_VMID10 … #define mmGDS_OA_VMID10_BASE_IDX … #define mmGDS_OA_VMID11 … #define mmGDS_OA_VMID11_BASE_IDX … #define mmGDS_OA_VMID12 … #define mmGDS_OA_VMID12_BASE_IDX … #define mmGDS_OA_VMID13 … #define mmGDS_OA_VMID13_BASE_IDX … #define mmGDS_OA_VMID14 … #define mmGDS_OA_VMID14_BASE_IDX … #define mmGDS_OA_VMID15 … #define mmGDS_OA_VMID15_BASE_IDX … #define mmGDS_GWS_RESET0 … #define mmGDS_GWS_RESET0_BASE_IDX … #define mmGDS_GWS_RESET1 … #define mmGDS_GWS_RESET1_BASE_IDX … #define mmGDS_GWS_RESOURCE_RESET … #define mmGDS_GWS_RESOURCE_RESET_BASE_IDX … #define mmGDS_COMPUTE_MAX_WAVE_ID … #define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX … #define mmGDS_OA_RESET_MASK … #define mmGDS_OA_RESET_MASK_BASE_IDX … #define mmGDS_OA_RESET … #define mmGDS_OA_RESET_BASE_IDX … #define mmGDS_ENHANCE2 … #define mmGDS_ENHANCE2_BASE_IDX … #define mmGDS_OA_CGPG_RESTORE … #define mmGDS_OA_CGPG_RESTORE_BASE_IDX … #define mmGDS_CS_CTXSW_STATUS … #define mmGDS_CS_CTXSW_STATUS_BASE_IDX … #define mmGDS_CS_CTXSW_CNT0 … #define mmGDS_CS_CTXSW_CNT0_BASE_IDX … #define mmGDS_CS_CTXSW_CNT1 … #define mmGDS_CS_CTXSW_CNT1_BASE_IDX … #define mmGDS_CS_CTXSW_CNT2 … #define mmGDS_CS_CTXSW_CNT2_BASE_IDX … #define mmGDS_CS_CTXSW_CNT3 … #define mmGDS_CS_CTXSW_CNT3_BASE_IDX … #define mmGDS_GFX_CTXSW_STATUS … #define mmGDS_GFX_CTXSW_STATUS_BASE_IDX … #define mmGDS_VS_CTXSW_CNT0 … #define mmGDS_VS_CTXSW_CNT0_BASE_IDX … #define mmGDS_VS_CTXSW_CNT1 … #define mmGDS_VS_CTXSW_CNT1_BASE_IDX … #define mmGDS_VS_CTXSW_CNT2 … #define mmGDS_VS_CTXSW_CNT2_BASE_IDX … #define mmGDS_VS_CTXSW_CNT3 … #define mmGDS_VS_CTXSW_CNT3_BASE_IDX … #define mmGDS_PS_CTXSW_CNT0 … #define mmGDS_PS_CTXSW_CNT0_BASE_IDX … #define mmGDS_PS_CTXSW_CNT1 … #define mmGDS_PS_CTXSW_CNT1_BASE_IDX … #define mmGDS_PS_CTXSW_CNT2 … #define mmGDS_PS_CTXSW_CNT2_BASE_IDX … #define mmGDS_PS_CTXSW_CNT3 … #define mmGDS_PS_CTXSW_CNT3_BASE_IDX … #define mmGDS_PS_CTXSW_IDX … #define mmGDS_PS_CTXSW_IDX_BASE_IDX … #define mmGDS_GS_CTXSW_CNT0 … #define mmGDS_GS_CTXSW_CNT0_BASE_IDX … #define mmGDS_GS_CTXSW_CNT1 … #define mmGDS_GS_CTXSW_CNT1_BASE_IDX … #define mmGDS_GS_CTXSW_CNT2 … #define mmGDS_GS_CTXSW_CNT2_BASE_IDX … #define mmGDS_GS_CTXSW_CNT3 … #define mmGDS_GS_CTXSW_CNT3_BASE_IDX … // addressBlock: gc_gfxdec0 // base address: 0x28000 #define mmDB_RENDER_CONTROL … #define mmDB_RENDER_CONTROL_BASE_IDX … #define mmDB_COUNT_CONTROL … #define mmDB_COUNT_CONTROL_BASE_IDX … #define mmDB_DEPTH_VIEW … #define mmDB_DEPTH_VIEW_BASE_IDX … #define mmDB_RENDER_OVERRIDE … #define mmDB_RENDER_OVERRIDE_BASE_IDX … #define mmDB_RENDER_OVERRIDE2 … #define mmDB_RENDER_OVERRIDE2_BASE_IDX … #define mmDB_HTILE_DATA_BASE … #define mmDB_HTILE_DATA_BASE_BASE_IDX … #define mmDB_DEPTH_SIZE_XY … #define mmDB_DEPTH_SIZE_XY_BASE_IDX … #define mmDB_DEPTH_BOUNDS_MIN … #define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX … #define mmDB_DEPTH_BOUNDS_MAX … #define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX … #define mmDB_STENCIL_CLEAR … #define mmDB_STENCIL_CLEAR_BASE_IDX … #define mmDB_DEPTH_CLEAR … #define mmDB_DEPTH_CLEAR_BASE_IDX … #define mmPA_SC_SCREEN_SCISSOR_TL … #define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX … #define mmPA_SC_SCREEN_SCISSOR_BR … #define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX … #define mmDB_DFSM_CONTROL … #define mmDB_DFSM_CONTROL_BASE_IDX … #define mmDB_RESERVED_REG_2 … #define mmDB_RESERVED_REG_2_BASE_IDX … #define mmDB_Z_INFO … #define mmDB_Z_INFO_BASE_IDX … #define mmDB_STENCIL_INFO … #define mmDB_STENCIL_INFO_BASE_IDX … #define mmDB_Z_READ_BASE … #define mmDB_Z_READ_BASE_BASE_IDX … #define mmDB_STENCIL_READ_BASE … #define mmDB_STENCIL_READ_BASE_BASE_IDX … #define mmDB_Z_WRITE_BASE … #define mmDB_Z_WRITE_BASE_BASE_IDX … #define mmDB_STENCIL_WRITE_BASE … #define mmDB_STENCIL_WRITE_BASE_BASE_IDX … #define mmDB_RESERVED_REG_1 … #define mmDB_RESERVED_REG_1_BASE_IDX … #define mmDB_RESERVED_REG_3 … #define mmDB_RESERVED_REG_3_BASE_IDX … #define mmDB_Z_READ_BASE_HI … #define mmDB_Z_READ_BASE_HI_BASE_IDX … #define mmDB_STENCIL_READ_BASE_HI … #define mmDB_STENCIL_READ_BASE_HI_BASE_IDX … #define mmDB_Z_WRITE_BASE_HI … #define mmDB_Z_WRITE_BASE_HI_BASE_IDX … #define mmDB_STENCIL_WRITE_BASE_HI … #define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX … #define mmDB_HTILE_DATA_BASE_HI … #define mmDB_HTILE_DATA_BASE_HI_BASE_IDX … #define mmDB_RMI_L2_CACHE_CONTROL … #define mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX … #define mmTA_BC_BASE_ADDR … #define mmTA_BC_BASE_ADDR_BASE_IDX … #define mmTA_BC_BASE_ADDR_HI … #define mmTA_BC_BASE_ADDR_HI_BASE_IDX … #define mmCOHER_DEST_BASE_HI_0 … #define mmCOHER_DEST_BASE_HI_0_BASE_IDX … #define mmCOHER_DEST_BASE_HI_1 … #define mmCOHER_DEST_BASE_HI_1_BASE_IDX … #define mmCOHER_DEST_BASE_HI_2 … #define mmCOHER_DEST_BASE_HI_2_BASE_IDX … #define mmCOHER_DEST_BASE_HI_3 … #define mmCOHER_DEST_BASE_HI_3_BASE_IDX … #define mmCOHER_DEST_BASE_2 … #define mmCOHER_DEST_BASE_2_BASE_IDX … #define mmCOHER_DEST_BASE_3 … #define mmCOHER_DEST_BASE_3_BASE_IDX … #define mmPA_SC_WINDOW_OFFSET … #define mmPA_SC_WINDOW_OFFSET_BASE_IDX … #define mmPA_SC_WINDOW_SCISSOR_TL … #define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX … #define mmPA_SC_WINDOW_SCISSOR_BR … #define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX … #define mmPA_SC_CLIPRECT_RULE … #define mmPA_SC_CLIPRECT_RULE_BASE_IDX … #define mmPA_SC_CLIPRECT_0_TL … #define mmPA_SC_CLIPRECT_0_TL_BASE_IDX … #define mmPA_SC_CLIPRECT_0_BR … #define mmPA_SC_CLIPRECT_0_BR_BASE_IDX … #define mmPA_SC_CLIPRECT_1_TL … #define mmPA_SC_CLIPRECT_1_TL_BASE_IDX … #define mmPA_SC_CLIPRECT_1_BR … #define mmPA_SC_CLIPRECT_1_BR_BASE_IDX … #define mmPA_SC_CLIPRECT_2_TL … #define mmPA_SC_CLIPRECT_2_TL_BASE_IDX … #define mmPA_SC_CLIPRECT_2_BR … #define mmPA_SC_CLIPRECT_2_BR_BASE_IDX … #define mmPA_SC_CLIPRECT_3_TL … #define mmPA_SC_CLIPRECT_3_TL_BASE_IDX … #define mmPA_SC_CLIPRECT_3_BR … #define mmPA_SC_CLIPRECT_3_BR_BASE_IDX … #define mmPA_SC_EDGERULE … #define mmPA_SC_EDGERULE_BASE_IDX … #define mmPA_SU_HARDWARE_SCREEN_OFFSET … #define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX … #define mmCB_TARGET_MASK … #define mmCB_TARGET_MASK_BASE_IDX … #define mmCB_SHADER_MASK … #define mmCB_SHADER_MASK_BASE_IDX … #define mmPA_SC_GENERIC_SCISSOR_TL … #define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX … #define mmPA_SC_GENERIC_SCISSOR_BR … #define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX … #define mmCOHER_DEST_BASE_0 … #define mmCOHER_DEST_BASE_0_BASE_IDX … #define mmCOHER_DEST_BASE_1 … #define mmCOHER_DEST_BASE_1_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_0_TL … #define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_0_BR … #define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_1_TL … #define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_1_BR … #define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_2_TL … #define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_2_BR … #define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_3_TL … #define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_3_BR … #define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_4_TL … #define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_4_BR … #define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_5_TL … #define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_5_BR … #define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_6_TL … #define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_6_BR … #define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_7_TL … #define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_7_BR … #define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_8_TL … #define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_8_BR … #define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_9_TL … #define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_9_BR … #define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_10_TL … #define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_10_BR … #define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_11_TL … #define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_11_BR … #define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_12_TL … #define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_12_BR … #define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_13_TL … #define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_13_BR … #define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_14_TL … #define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_14_BR … #define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_15_TL … #define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX … #define mmPA_SC_VPORT_SCISSOR_15_BR … #define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_0 … #define mmPA_SC_VPORT_ZMIN_0_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_0 … #define mmPA_SC_VPORT_ZMAX_0_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_1 … #define mmPA_SC_VPORT_ZMIN_1_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_1 … #define mmPA_SC_VPORT_ZMAX_1_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_2 … #define mmPA_SC_VPORT_ZMIN_2_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_2 … #define mmPA_SC_VPORT_ZMAX_2_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_3 … #define mmPA_SC_VPORT_ZMIN_3_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_3 … #define mmPA_SC_VPORT_ZMAX_3_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_4 … #define mmPA_SC_VPORT_ZMIN_4_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_4 … #define mmPA_SC_VPORT_ZMAX_4_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_5 … #define mmPA_SC_VPORT_ZMIN_5_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_5 … #define mmPA_SC_VPORT_ZMAX_5_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_6 … #define mmPA_SC_VPORT_ZMIN_6_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_6 … #define mmPA_SC_VPORT_ZMAX_6_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_7 … #define mmPA_SC_VPORT_ZMIN_7_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_7 … #define mmPA_SC_VPORT_ZMAX_7_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_8 … #define mmPA_SC_VPORT_ZMIN_8_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_8 … #define mmPA_SC_VPORT_ZMAX_8_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_9 … #define mmPA_SC_VPORT_ZMIN_9_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_9 … #define mmPA_SC_VPORT_ZMAX_9_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_10 … #define mmPA_SC_VPORT_ZMIN_10_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_10 … #define mmPA_SC_VPORT_ZMAX_10_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_11 … #define mmPA_SC_VPORT_ZMIN_11_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_11 … #define mmPA_SC_VPORT_ZMAX_11_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_12 … #define mmPA_SC_VPORT_ZMIN_12_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_12 … #define mmPA_SC_VPORT_ZMAX_12_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_13 … #define mmPA_SC_VPORT_ZMIN_13_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_13 … #define mmPA_SC_VPORT_ZMAX_13_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_14 … #define mmPA_SC_VPORT_ZMIN_14_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_14 … #define mmPA_SC_VPORT_ZMAX_14_BASE_IDX … #define mmPA_SC_VPORT_ZMIN_15 … #define mmPA_SC_VPORT_ZMIN_15_BASE_IDX … #define mmPA_SC_VPORT_ZMAX_15 … #define mmPA_SC_VPORT_ZMAX_15_BASE_IDX … #define mmPA_SC_RASTER_CONFIG … #define mmPA_SC_RASTER_CONFIG_BASE_IDX … #define mmPA_SC_RASTER_CONFIG_1 … #define mmPA_SC_RASTER_CONFIG_1_BASE_IDX … #define mmPA_SC_SCREEN_EXTENT_CONTROL … #define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX … #define mmPA_SC_TILE_STEERING_OVERRIDE … #define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX … #define mmCP_PERFMON_CNTX_CNTL … #define mmCP_PERFMON_CNTX_CNTL_BASE_IDX … #define mmCP_PIPEID … #define mmCP_PIPEID_BASE_IDX … #define mmCP_RINGID … #define mmCP_RINGID_BASE_IDX … #define mmCP_VMID … #define mmCP_VMID_BASE_IDX … #define mmPA_SC_RIGHT_VERT_GRID … #define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX … #define mmPA_SC_LEFT_VERT_GRID … #define mmPA_SC_LEFT_VERT_GRID_BASE_IDX … #define mmPA_SC_HORIZ_GRID … #define mmPA_SC_HORIZ_GRID_BASE_IDX … #define mmVGT_MAX_VTX_INDX … #define mmVGT_MAX_VTX_INDX_BASE_IDX … #define mmVGT_MIN_VTX_INDX … #define mmVGT_MIN_VTX_INDX_BASE_IDX … #define mmVGT_INDX_OFFSET … #define mmVGT_INDX_OFFSET_BASE_IDX … #define mmVGT_MULTI_PRIM_IB_RESET_INDX … #define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX … #define mmCB_RMI_GL2_CACHE_CONTROL … #define mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX … #define mmCB_BLEND_RED … #define mmCB_BLEND_RED_BASE_IDX … #define mmCB_BLEND_GREEN … #define mmCB_BLEND_GREEN_BASE_IDX … #define mmCB_BLEND_BLUE … #define mmCB_BLEND_BLUE_BASE_IDX … #define mmCB_BLEND_ALPHA … #define mmCB_BLEND_ALPHA_BASE_IDX … #define mmCB_DCC_CONTROL … #define mmCB_DCC_CONTROL_BASE_IDX … #define mmCB_COVERAGE_OUT_CONTROL … #define mmCB_COVERAGE_OUT_CONTROL_BASE_IDX … #define mmDB_STENCIL_CONTROL … #define mmDB_STENCIL_CONTROL_BASE_IDX … #define mmDB_STENCILREFMASK … #define mmDB_STENCILREFMASK_BASE_IDX … #define mmDB_STENCILREFMASK_BF … #define mmDB_STENCILREFMASK_BF_BASE_IDX … #define mmPA_CL_VPORT_XSCALE … #define mmPA_CL_VPORT_XSCALE_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET … #define mmPA_CL_VPORT_XOFFSET_BASE_IDX … #define mmPA_CL_VPORT_YSCALE … #define mmPA_CL_VPORT_YSCALE_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET … #define mmPA_CL_VPORT_YOFFSET_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE … #define mmPA_CL_VPORT_ZSCALE_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET … #define mmPA_CL_VPORT_ZOFFSET_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_1 … #define mmPA_CL_VPORT_XSCALE_1_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_1 … #define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_1 … #define mmPA_CL_VPORT_YSCALE_1_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_1 … #define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_1 … #define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_1 … #define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_2 … #define mmPA_CL_VPORT_XSCALE_2_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_2 … #define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_2 … #define mmPA_CL_VPORT_YSCALE_2_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_2 … #define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_2 … #define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_2 … #define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_3 … #define mmPA_CL_VPORT_XSCALE_3_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_3 … #define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_3 … #define mmPA_CL_VPORT_YSCALE_3_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_3 … #define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_3 … #define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_3 … #define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_4 … #define mmPA_CL_VPORT_XSCALE_4_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_4 … #define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_4 … #define mmPA_CL_VPORT_YSCALE_4_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_4 … #define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_4 … #define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_4 … #define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_5 … #define mmPA_CL_VPORT_XSCALE_5_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_5 … #define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_5 … #define mmPA_CL_VPORT_YSCALE_5_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_5 … #define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_5 … #define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_5 … #define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_6 … #define mmPA_CL_VPORT_XSCALE_6_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_6 … #define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_6 … #define mmPA_CL_VPORT_YSCALE_6_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_6 … #define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_6 … #define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_6 … #define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_7 … #define mmPA_CL_VPORT_XSCALE_7_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_7 … #define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_7 … #define mmPA_CL_VPORT_YSCALE_7_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_7 … #define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_7 … #define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_7 … #define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_8 … #define mmPA_CL_VPORT_XSCALE_8_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_8 … #define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_8 … #define mmPA_CL_VPORT_YSCALE_8_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_8 … #define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_8 … #define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_8 … #define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_9 … #define mmPA_CL_VPORT_XSCALE_9_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_9 … #define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_9 … #define mmPA_CL_VPORT_YSCALE_9_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_9 … #define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_9 … #define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_9 … #define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_10 … #define mmPA_CL_VPORT_XSCALE_10_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_10 … #define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_10 … #define mmPA_CL_VPORT_YSCALE_10_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_10 … #define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_10 … #define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_10 … #define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_11 … #define mmPA_CL_VPORT_XSCALE_11_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_11 … #define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_11 … #define mmPA_CL_VPORT_YSCALE_11_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_11 … #define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_11 … #define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_11 … #define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_12 … #define mmPA_CL_VPORT_XSCALE_12_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_12 … #define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_12 … #define mmPA_CL_VPORT_YSCALE_12_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_12 … #define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_12 … #define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_12 … #define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_13 … #define mmPA_CL_VPORT_XSCALE_13_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_13 … #define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_13 … #define mmPA_CL_VPORT_YSCALE_13_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_13 … #define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_13 … #define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_13 … #define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_14 … #define mmPA_CL_VPORT_XSCALE_14_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_14 … #define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_14 … #define mmPA_CL_VPORT_YSCALE_14_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_14 … #define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_14 … #define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_14 … #define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX … #define mmPA_CL_VPORT_XSCALE_15 … #define mmPA_CL_VPORT_XSCALE_15_BASE_IDX … #define mmPA_CL_VPORT_XOFFSET_15 … #define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX … #define mmPA_CL_VPORT_YSCALE_15 … #define mmPA_CL_VPORT_YSCALE_15_BASE_IDX … #define mmPA_CL_VPORT_YOFFSET_15 … #define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX … #define mmPA_CL_VPORT_ZSCALE_15 … #define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX … #define mmPA_CL_VPORT_ZOFFSET_15 … #define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX … #define mmPA_CL_UCP_0_X … #define mmPA_CL_UCP_0_X_BASE_IDX … #define mmPA_CL_UCP_0_Y … #define mmPA_CL_UCP_0_Y_BASE_IDX … #define mmPA_CL_UCP_0_Z … #define mmPA_CL_UCP_0_Z_BASE_IDX … #define mmPA_CL_UCP_0_W … #define mmPA_CL_UCP_0_W_BASE_IDX … #define mmPA_CL_UCP_1_X … #define mmPA_CL_UCP_1_X_BASE_IDX … #define mmPA_CL_UCP_1_Y … #define mmPA_CL_UCP_1_Y_BASE_IDX … #define mmPA_CL_UCP_1_Z … #define mmPA_CL_UCP_1_Z_BASE_IDX … #define mmPA_CL_UCP_1_W … #define mmPA_CL_UCP_1_W_BASE_IDX … #define mmPA_CL_UCP_2_X … #define mmPA_CL_UCP_2_X_BASE_IDX … #define mmPA_CL_UCP_2_Y … #define mmPA_CL_UCP_2_Y_BASE_IDX … #define mmPA_CL_UCP_2_Z … #define mmPA_CL_UCP_2_Z_BASE_IDX … #define mmPA_CL_UCP_2_W … #define mmPA_CL_UCP_2_W_BASE_IDX … #define mmPA_CL_UCP_3_X … #define mmPA_CL_UCP_3_X_BASE_IDX … #define mmPA_CL_UCP_3_Y … #define mmPA_CL_UCP_3_Y_BASE_IDX … #define mmPA_CL_UCP_3_Z … #define mmPA_CL_UCP_3_Z_BASE_IDX … #define mmPA_CL_UCP_3_W … #define mmPA_CL_UCP_3_W_BASE_IDX … #define mmPA_CL_UCP_4_X … #define mmPA_CL_UCP_4_X_BASE_IDX … #define mmPA_CL_UCP_4_Y … #define mmPA_CL_UCP_4_Y_BASE_IDX … #define mmPA_CL_UCP_4_Z … #define mmPA_CL_UCP_4_Z_BASE_IDX … #define mmPA_CL_UCP_4_W … #define mmPA_CL_UCP_4_W_BASE_IDX … #define mmPA_CL_UCP_5_X … #define mmPA_CL_UCP_5_X_BASE_IDX … #define mmPA_CL_UCP_5_Y … #define mmPA_CL_UCP_5_Y_BASE_IDX … #define mmPA_CL_UCP_5_Z … #define mmPA_CL_UCP_5_Z_BASE_IDX … #define mmPA_CL_UCP_5_W … #define mmPA_CL_UCP_5_W_BASE_IDX … #define mmPA_CL_PROG_NEAR_CLIP_Z … #define mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_0 … #define mmSPI_PS_INPUT_CNTL_0_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_1 … #define mmSPI_PS_INPUT_CNTL_1_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_2 … #define mmSPI_PS_INPUT_CNTL_2_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_3 … #define mmSPI_PS_INPUT_CNTL_3_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_4 … #define mmSPI_PS_INPUT_CNTL_4_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_5 … #define mmSPI_PS_INPUT_CNTL_5_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_6 … #define mmSPI_PS_INPUT_CNTL_6_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_7 … #define mmSPI_PS_INPUT_CNTL_7_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_8 … #define mmSPI_PS_INPUT_CNTL_8_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_9 … #define mmSPI_PS_INPUT_CNTL_9_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_10 … #define mmSPI_PS_INPUT_CNTL_10_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_11 … #define mmSPI_PS_INPUT_CNTL_11_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_12 … #define mmSPI_PS_INPUT_CNTL_12_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_13 … #define mmSPI_PS_INPUT_CNTL_13_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_14 … #define mmSPI_PS_INPUT_CNTL_14_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_15 … #define mmSPI_PS_INPUT_CNTL_15_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_16 … #define mmSPI_PS_INPUT_CNTL_16_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_17 … #define mmSPI_PS_INPUT_CNTL_17_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_18 … #define mmSPI_PS_INPUT_CNTL_18_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_19 … #define mmSPI_PS_INPUT_CNTL_19_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_20 … #define mmSPI_PS_INPUT_CNTL_20_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_21 … #define mmSPI_PS_INPUT_CNTL_21_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_22 … #define mmSPI_PS_INPUT_CNTL_22_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_23 … #define mmSPI_PS_INPUT_CNTL_23_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_24 … #define mmSPI_PS_INPUT_CNTL_24_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_25 … #define mmSPI_PS_INPUT_CNTL_25_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_26 … #define mmSPI_PS_INPUT_CNTL_26_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_27 … #define mmSPI_PS_INPUT_CNTL_27_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_28 … #define mmSPI_PS_INPUT_CNTL_28_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_29 … #define mmSPI_PS_INPUT_CNTL_29_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_30 … #define mmSPI_PS_INPUT_CNTL_30_BASE_IDX … #define mmSPI_PS_INPUT_CNTL_31 … #define mmSPI_PS_INPUT_CNTL_31_BASE_IDX … #define mmSPI_VS_OUT_CONFIG … #define mmSPI_VS_OUT_CONFIG_BASE_IDX … #define mmSPI_PS_INPUT_ENA … #define mmSPI_PS_INPUT_ENA_BASE_IDX … #define mmSPI_PS_INPUT_ADDR … #define mmSPI_PS_INPUT_ADDR_BASE_IDX … #define mmSPI_INTERP_CONTROL_0 … #define mmSPI_INTERP_CONTROL_0_BASE_IDX … #define mmSPI_PS_IN_CONTROL … #define mmSPI_PS_IN_CONTROL_BASE_IDX … #define mmSPI_BARYC_CNTL … #define mmSPI_BARYC_CNTL_BASE_IDX … #define mmSPI_TMPRING_SIZE … #define mmSPI_TMPRING_SIZE_BASE_IDX … #define mmSPI_SHADER_IDX_FORMAT … #define mmSPI_SHADER_IDX_FORMAT_BASE_IDX … #define mmSPI_SHADER_POS_FORMAT … #define mmSPI_SHADER_POS_FORMAT_BASE_IDX … #define mmSPI_SHADER_Z_FORMAT … #define mmSPI_SHADER_Z_FORMAT_BASE_IDX … #define mmSPI_SHADER_COL_FORMAT … #define mmSPI_SHADER_COL_FORMAT_BASE_IDX … #define mmSX_PS_DOWNCONVERT … #define mmSX_PS_DOWNCONVERT_BASE_IDX … #define mmSX_BLEND_OPT_EPSILON … #define mmSX_BLEND_OPT_EPSILON_BASE_IDX … #define mmSX_BLEND_OPT_CONTROL … #define mmSX_BLEND_OPT_CONTROL_BASE_IDX … #define mmSX_MRT0_BLEND_OPT … #define mmSX_MRT0_BLEND_OPT_BASE_IDX … #define mmSX_MRT1_BLEND_OPT … #define mmSX_MRT1_BLEND_OPT_BASE_IDX … #define mmSX_MRT2_BLEND_OPT … #define mmSX_MRT2_BLEND_OPT_BASE_IDX … #define mmSX_MRT3_BLEND_OPT … #define mmSX_MRT3_BLEND_OPT_BASE_IDX … #define mmSX_MRT4_BLEND_OPT … #define mmSX_MRT4_BLEND_OPT_BASE_IDX … #define mmSX_MRT5_BLEND_OPT … #define mmSX_MRT5_BLEND_OPT_BASE_IDX … #define mmSX_MRT6_BLEND_OPT … #define mmSX_MRT6_BLEND_OPT_BASE_IDX … #define mmSX_MRT7_BLEND_OPT … #define mmSX_MRT7_BLEND_OPT_BASE_IDX … #define mmCB_BLEND0_CONTROL … #define mmCB_BLEND0_CONTROL_BASE_IDX … #define mmCB_BLEND1_CONTROL … #define mmCB_BLEND1_CONTROL_BASE_IDX … #define mmCB_BLEND2_CONTROL … #define mmCB_BLEND2_CONTROL_BASE_IDX … #define mmCB_BLEND3_CONTROL … #define mmCB_BLEND3_CONTROL_BASE_IDX … #define mmCB_BLEND4_CONTROL … #define mmCB_BLEND4_CONTROL_BASE_IDX … #define mmCB_BLEND5_CONTROL … #define mmCB_BLEND5_CONTROL_BASE_IDX … #define mmCB_BLEND6_CONTROL … #define mmCB_BLEND6_CONTROL_BASE_IDX … #define mmCB_BLEND7_CONTROL … #define mmCB_BLEND7_CONTROL_BASE_IDX … #define mmCS_COPY_STATE … #define mmCS_COPY_STATE_BASE_IDX … #define mmGFX_COPY_STATE … #define mmGFX_COPY_STATE_BASE_IDX … #define mmPA_CL_POINT_X_RAD … #define mmPA_CL_POINT_X_RAD_BASE_IDX … #define mmPA_CL_POINT_Y_RAD … #define mmPA_CL_POINT_Y_RAD_BASE_IDX … #define mmPA_CL_POINT_SIZE … #define mmPA_CL_POINT_SIZE_BASE_IDX … #define mmPA_CL_POINT_CULL_RAD … #define mmPA_CL_POINT_CULL_RAD_BASE_IDX … #define mmVGT_DMA_BASE_HI … #define mmVGT_DMA_BASE_HI_BASE_IDX … #define mmVGT_DMA_BASE … #define mmVGT_DMA_BASE_BASE_IDX … #define mmVGT_DRAW_INITIATOR … #define mmVGT_DRAW_INITIATOR_BASE_IDX … #define mmVGT_IMMED_DATA … #define mmVGT_IMMED_DATA_BASE_IDX … #define mmVGT_EVENT_ADDRESS_REG … #define mmVGT_EVENT_ADDRESS_REG_BASE_IDX … #define mmGE_MAX_OUTPUT_PER_SUBGROUP … #define mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX … #define mmDB_DEPTH_CONTROL … #define mmDB_DEPTH_CONTROL_BASE_IDX … #define mmDB_EQAA … #define mmDB_EQAA_BASE_IDX … #define mmCB_COLOR_CONTROL … #define mmCB_COLOR_CONTROL_BASE_IDX … #define mmDB_SHADER_CONTROL … #define mmDB_SHADER_CONTROL_BASE_IDX … #define mmPA_CL_CLIP_CNTL … #define mmPA_CL_CLIP_CNTL_BASE_IDX … #define mmPA_SU_SC_MODE_CNTL … #define mmPA_SU_SC_MODE_CNTL_BASE_IDX … #define mmPA_CL_VTE_CNTL … #define mmPA_CL_VTE_CNTL_BASE_IDX … #define mmPA_CL_VS_OUT_CNTL … #define mmPA_CL_VS_OUT_CNTL_BASE_IDX … #define mmPA_CL_NANINF_CNTL … #define mmPA_CL_NANINF_CNTL_BASE_IDX … #define mmPA_SU_LINE_STIPPLE_CNTL … #define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX … #define mmPA_SU_LINE_STIPPLE_SCALE … #define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX … #define mmPA_SU_PRIM_FILTER_CNTL … #define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX … #define mmPA_SU_SMALL_PRIM_FILTER_CNTL … #define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX … #define mmPA_CL_OBJPRIM_ID_CNTL … #define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX … #define mmPA_CL_NGG_CNTL … #define mmPA_CL_NGG_CNTL_BASE_IDX … #define mmPA_SU_OVER_RASTERIZATION_CNTL … #define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX … #define mmPA_STEREO_CNTL … #define mmPA_STEREO_CNTL_BASE_IDX … #define mmPA_STATE_STEREO_X … #define mmPA_STATE_STEREO_X_BASE_IDX … #define mmPA_SU_POINT_SIZE … #define mmPA_SU_POINT_SIZE_BASE_IDX … #define mmPA_SU_POINT_MINMAX … #define mmPA_SU_POINT_MINMAX_BASE_IDX … #define mmPA_SU_LINE_CNTL … #define mmPA_SU_LINE_CNTL_BASE_IDX … #define mmPA_SC_LINE_STIPPLE … #define mmPA_SC_LINE_STIPPLE_BASE_IDX … #define mmVGT_OUTPUT_PATH_CNTL … #define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX … #define mmVGT_HOS_CNTL … #define mmVGT_HOS_CNTL_BASE_IDX … #define mmVGT_HOS_MAX_TESS_LEVEL … #define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX … #define mmVGT_HOS_MIN_TESS_LEVEL … #define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX … #define mmVGT_HOS_REUSE_DEPTH … #define mmVGT_HOS_REUSE_DEPTH_BASE_IDX … #define mmVGT_GROUP_PRIM_TYPE … #define mmVGT_GROUP_PRIM_TYPE_BASE_IDX … #define mmVGT_GROUP_FIRST_DECR … #define mmVGT_GROUP_FIRST_DECR_BASE_IDX … #define mmVGT_GROUP_DECR … #define mmVGT_GROUP_DECR_BASE_IDX … #define mmVGT_GROUP_VECT_0_CNTL … #define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX … #define mmVGT_GROUP_VECT_1_CNTL … #define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX … #define mmVGT_GROUP_VECT_0_FMT_CNTL … #define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX … #define mmVGT_GROUP_VECT_1_FMT_CNTL … #define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX … #define mmVGT_GS_MODE … #define mmVGT_GS_MODE_BASE_IDX … #define mmVGT_GS_ONCHIP_CNTL … #define mmVGT_GS_ONCHIP_CNTL_BASE_IDX … #define mmPA_SC_MODE_CNTL_0 … #define mmPA_SC_MODE_CNTL_0_BASE_IDX … #define mmPA_SC_MODE_CNTL_1 … #define mmPA_SC_MODE_CNTL_1_BASE_IDX … #define mmVGT_ENHANCE … #define mmVGT_ENHANCE_BASE_IDX … #define mmVGT_GS_PER_ES … #define mmVGT_GS_PER_ES_BASE_IDX … #define mmVGT_ES_PER_GS … #define mmVGT_ES_PER_GS_BASE_IDX … #define mmVGT_GS_PER_VS … #define mmVGT_GS_PER_VS_BASE_IDX … #define mmVGT_GSVS_RING_OFFSET_1 … #define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX … #define mmVGT_GSVS_RING_OFFSET_2 … #define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX … #define mmVGT_GSVS_RING_OFFSET_3 … #define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX … #define mmVGT_GS_OUT_PRIM_TYPE … #define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX … #define mmIA_ENHANCE … #define mmIA_ENHANCE_BASE_IDX … #define mmVGT_DMA_SIZE … #define mmVGT_DMA_SIZE_BASE_IDX … #define mmVGT_DMA_MAX_SIZE … #define mmVGT_DMA_MAX_SIZE_BASE_IDX … #define mmVGT_DMA_INDEX_TYPE … #define mmVGT_DMA_INDEX_TYPE_BASE_IDX … #define mmWD_ENHANCE … #define mmWD_ENHANCE_BASE_IDX … #define mmVGT_PRIMITIVEID_EN … #define mmVGT_PRIMITIVEID_EN_BASE_IDX … #define mmVGT_DMA_NUM_INSTANCES … #define mmVGT_DMA_NUM_INSTANCES_BASE_IDX … #define mmVGT_PRIMITIVEID_RESET … #define mmVGT_PRIMITIVEID_RESET_BASE_IDX … #define mmVGT_EVENT_INITIATOR … #define mmVGT_EVENT_INITIATOR_BASE_IDX … #define mmVGT_MULTI_PRIM_IB_RESET_EN … #define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX … #define mmVGT_DRAW_PAYLOAD_CNTL … #define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX … #define mmVGT_INSTANCE_STEP_RATE_0 … #define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX … #define mmVGT_INSTANCE_STEP_RATE_1 … #define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX … #define mmIA_MULTI_VGT_PARAM … #define mmIA_MULTI_VGT_PARAM_BASE_IDX … #define mmVGT_ESGS_RING_ITEMSIZE … #define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX … #define mmVGT_GSVS_RING_ITEMSIZE … #define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX … #define mmVGT_REUSE_OFF … #define mmVGT_REUSE_OFF_BASE_IDX … #define mmVGT_VTX_CNT_EN … #define mmVGT_VTX_CNT_EN_BASE_IDX … #define mmDB_HTILE_SURFACE … #define mmDB_HTILE_SURFACE_BASE_IDX … #define mmDB_SRESULTS_COMPARE_STATE0 … #define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX … #define mmDB_SRESULTS_COMPARE_STATE1 … #define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX … #define mmDB_PRELOAD_CONTROL … #define mmDB_PRELOAD_CONTROL_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_SIZE_0 … #define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX … #define mmVGT_STRMOUT_VTX_STRIDE_0 … #define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_OFFSET_0 … #define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_SIZE_1 … #define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX … #define mmVGT_STRMOUT_VTX_STRIDE_1 … #define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_OFFSET_1 … #define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_SIZE_2 … #define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX … #define mmVGT_STRMOUT_VTX_STRIDE_2 … #define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_OFFSET_2 … #define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_SIZE_3 … #define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX … #define mmVGT_STRMOUT_VTX_STRIDE_3 … #define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_OFFSET_3 … #define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX … #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET … #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX … #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE … #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX … #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE … #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX … #define mmVGT_GS_MAX_VERT_OUT … #define mmVGT_GS_MAX_VERT_OUT_BASE_IDX … #define mmGE_NGG_SUBGRP_CNTL … #define mmGE_NGG_SUBGRP_CNTL_BASE_IDX … #define mmVGT_TESS_DISTRIBUTION … #define mmVGT_TESS_DISTRIBUTION_BASE_IDX … #define mmVGT_SHADER_STAGES_EN … #define mmVGT_SHADER_STAGES_EN_BASE_IDX … #define mmVGT_LS_HS_CONFIG … #define mmVGT_LS_HS_CONFIG_BASE_IDX … #define mmVGT_GS_VERT_ITEMSIZE … #define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX … #define mmVGT_GS_VERT_ITEMSIZE_1 … #define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX … #define mmVGT_GS_VERT_ITEMSIZE_2 … #define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX … #define mmVGT_GS_VERT_ITEMSIZE_3 … #define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX … #define mmVGT_TF_PARAM … #define mmVGT_TF_PARAM_BASE_IDX … #define mmDB_ALPHA_TO_MASK … #define mmDB_ALPHA_TO_MASK_BASE_IDX … #define mmVGT_DISPATCH_DRAW_INDEX … #define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX … #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL … #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX … #define mmPA_SU_POLY_OFFSET_CLAMP … #define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX … #define mmPA_SU_POLY_OFFSET_FRONT_SCALE … #define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX … #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET … #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX … #define mmPA_SU_POLY_OFFSET_BACK_SCALE … #define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX … #define mmPA_SU_POLY_OFFSET_BACK_OFFSET … #define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX … #define mmVGT_GS_INSTANCE_CNT … #define mmVGT_GS_INSTANCE_CNT_BASE_IDX … #define mmVGT_STRMOUT_CONFIG … #define mmVGT_STRMOUT_CONFIG_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_CONFIG … #define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX … #define mmVGT_DMA_EVENT_INITIATOR … #define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX … #define mmPA_SC_CENTROID_PRIORITY_0 … #define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX … #define mmPA_SC_CENTROID_PRIORITY_1 … #define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX … #define mmPA_SC_LINE_CNTL … #define mmPA_SC_LINE_CNTL_BASE_IDX … #define mmPA_SC_AA_CONFIG … #define mmPA_SC_AA_CONFIG_BASE_IDX … #define mmPA_SU_VTX_CNTL … #define mmPA_SU_VTX_CNTL_BASE_IDX … #define mmPA_CL_GB_VERT_CLIP_ADJ … #define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX … #define mmPA_CL_GB_VERT_DISC_ADJ … #define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX … #define mmPA_CL_GB_HORZ_CLIP_ADJ … #define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX … #define mmPA_CL_GB_HORZ_DISC_ADJ … #define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 … #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX … #define mmPA_SC_AA_MASK_X0Y0_X1Y0 … #define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX … #define mmPA_SC_AA_MASK_X0Y1_X1Y1 … #define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX … #define mmPA_SC_SHADER_CONTROL … #define mmPA_SC_SHADER_CONTROL_BASE_IDX … #define mmPA_SC_BINNER_CNTL_0 … #define mmPA_SC_BINNER_CNTL_0_BASE_IDX … #define mmPA_SC_BINNER_CNTL_1 … #define mmPA_SC_BINNER_CNTL_1_BASE_IDX … #define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL … #define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX … #define mmPA_SC_NGG_MODE_CNTL … #define mmPA_SC_NGG_MODE_CNTL_BASE_IDX … #define mmVGT_VERTEX_REUSE_BLOCK_CNTL … #define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX … #define mmVGT_OUT_DEALLOC_CNTL … #define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX … #define mmCB_COLOR0_BASE … #define mmCB_COLOR0_BASE_BASE_IDX … #define mmCB_COLOR0_PITCH … #define mmCB_COLOR0_PITCH_BASE_IDX … #define mmCB_COLOR0_SLICE … #define mmCB_COLOR0_SLICE_BASE_IDX … #define mmCB_COLOR0_VIEW … #define mmCB_COLOR0_VIEW_BASE_IDX … #define mmCB_COLOR0_INFO … #define mmCB_COLOR0_INFO_BASE_IDX … #define mmCB_COLOR0_ATTRIB … #define mmCB_COLOR0_ATTRIB_BASE_IDX … #define mmCB_COLOR0_DCC_CONTROL … #define mmCB_COLOR0_DCC_CONTROL_BASE_IDX … #define mmCB_COLOR0_CMASK … #define mmCB_COLOR0_CMASK_BASE_IDX … #define mmCB_COLOR0_CMASK_SLICE … #define mmCB_COLOR0_CMASK_SLICE_BASE_IDX … #define mmCB_COLOR0_FMASK … #define mmCB_COLOR0_FMASK_BASE_IDX … #define mmCB_COLOR0_FMASK_SLICE … #define mmCB_COLOR0_FMASK_SLICE_BASE_IDX … #define mmCB_COLOR0_CLEAR_WORD0 … #define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX … #define mmCB_COLOR0_CLEAR_WORD1 … #define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX … #define mmCB_COLOR0_DCC_BASE … #define mmCB_COLOR0_DCC_BASE_BASE_IDX … #define mmCB_COLOR1_BASE … #define mmCB_COLOR1_BASE_BASE_IDX … #define mmCB_COLOR1_PITCH … #define mmCB_COLOR1_PITCH_BASE_IDX … #define mmCB_COLOR1_SLICE … #define mmCB_COLOR1_SLICE_BASE_IDX … #define mmCB_COLOR1_VIEW … #define mmCB_COLOR1_VIEW_BASE_IDX … #define mmCB_COLOR1_INFO … #define mmCB_COLOR1_INFO_BASE_IDX … #define mmCB_COLOR1_ATTRIB … #define mmCB_COLOR1_ATTRIB_BASE_IDX … #define mmCB_COLOR1_DCC_CONTROL … #define mmCB_COLOR1_DCC_CONTROL_BASE_IDX … #define mmCB_COLOR1_CMASK … #define mmCB_COLOR1_CMASK_BASE_IDX … #define mmCB_COLOR1_CMASK_SLICE … #define mmCB_COLOR1_CMASK_SLICE_BASE_IDX … #define mmCB_COLOR1_FMASK … #define mmCB_COLOR1_FMASK_BASE_IDX … #define mmCB_COLOR1_FMASK_SLICE … #define mmCB_COLOR1_FMASK_SLICE_BASE_IDX … #define mmCB_COLOR1_CLEAR_WORD0 … #define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX … #define mmCB_COLOR1_CLEAR_WORD1 … #define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX … #define mmCB_COLOR1_DCC_BASE … #define mmCB_COLOR1_DCC_BASE_BASE_IDX … #define mmCB_COLOR2_BASE … #define mmCB_COLOR2_BASE_BASE_IDX … #define mmCB_COLOR2_PITCH … #define mmCB_COLOR2_PITCH_BASE_IDX … #define mmCB_COLOR2_SLICE … #define mmCB_COLOR2_SLICE_BASE_IDX … #define mmCB_COLOR2_VIEW … #define mmCB_COLOR2_VIEW_BASE_IDX … #define mmCB_COLOR2_INFO … #define mmCB_COLOR2_INFO_BASE_IDX … #define mmCB_COLOR2_ATTRIB … #define mmCB_COLOR2_ATTRIB_BASE_IDX … #define mmCB_COLOR2_DCC_CONTROL … #define mmCB_COLOR2_DCC_CONTROL_BASE_IDX … #define mmCB_COLOR2_CMASK … #define mmCB_COLOR2_CMASK_BASE_IDX … #define mmCB_COLOR2_CMASK_SLICE … #define mmCB_COLOR2_CMASK_SLICE_BASE_IDX … #define mmCB_COLOR2_FMASK … #define mmCB_COLOR2_FMASK_BASE_IDX … #define mmCB_COLOR2_FMASK_SLICE … #define mmCB_COLOR2_FMASK_SLICE_BASE_IDX … #define mmCB_COLOR2_CLEAR_WORD0 … #define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX … #define mmCB_COLOR2_CLEAR_WORD1 … #define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX … #define mmCB_COLOR2_DCC_BASE … #define mmCB_COLOR2_DCC_BASE_BASE_IDX … #define mmCB_COLOR3_BASE … #define mmCB_COLOR3_BASE_BASE_IDX … #define mmCB_COLOR3_PITCH … #define mmCB_COLOR3_PITCH_BASE_IDX … #define mmCB_COLOR3_SLICE … #define mmCB_COLOR3_SLICE_BASE_IDX … #define mmCB_COLOR3_VIEW … #define mmCB_COLOR3_VIEW_BASE_IDX … #define mmCB_COLOR3_INFO … #define mmCB_COLOR3_INFO_BASE_IDX … #define mmCB_COLOR3_ATTRIB … #define mmCB_COLOR3_ATTRIB_BASE_IDX … #define mmCB_COLOR3_DCC_CONTROL … #define mmCB_COLOR3_DCC_CONTROL_BASE_IDX … #define mmCB_COLOR3_CMASK … #define mmCB_COLOR3_CMASK_BASE_IDX … #define mmCB_COLOR3_CMASK_SLICE … #define mmCB_COLOR3_CMASK_SLICE_BASE_IDX … #define mmCB_COLOR3_FMASK … #define mmCB_COLOR3_FMASK_BASE_IDX … #define mmCB_COLOR3_FMASK_SLICE … #define mmCB_COLOR3_FMASK_SLICE_BASE_IDX … #define mmCB_COLOR3_CLEAR_WORD0 … #define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX … #define mmCB_COLOR3_CLEAR_WORD1 … #define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX … #define mmCB_COLOR3_DCC_BASE … #define mmCB_COLOR3_DCC_BASE_BASE_IDX … #define mmCB_COLOR4_BASE … #define mmCB_COLOR4_BASE_BASE_IDX … #define mmCB_COLOR4_PITCH … #define mmCB_COLOR4_PITCH_BASE_IDX … #define mmCB_COLOR4_SLICE … #define mmCB_COLOR4_SLICE_BASE_IDX … #define mmCB_COLOR4_VIEW … #define mmCB_COLOR4_VIEW_BASE_IDX … #define mmCB_COLOR4_INFO … #define mmCB_COLOR4_INFO_BASE_IDX … #define mmCB_COLOR4_ATTRIB … #define mmCB_COLOR4_ATTRIB_BASE_IDX … #define mmCB_COLOR4_DCC_CONTROL … #define mmCB_COLOR4_DCC_CONTROL_BASE_IDX … #define mmCB_COLOR4_CMASK … #define mmCB_COLOR4_CMASK_BASE_IDX … #define mmCB_COLOR4_CMASK_SLICE … #define mmCB_COLOR4_CMASK_SLICE_BASE_IDX … #define mmCB_COLOR4_FMASK … #define mmCB_COLOR4_FMASK_BASE_IDX … #define mmCB_COLOR4_FMASK_SLICE … #define mmCB_COLOR4_FMASK_SLICE_BASE_IDX … #define mmCB_COLOR4_CLEAR_WORD0 … #define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX … #define mmCB_COLOR4_CLEAR_WORD1 … #define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX … #define mmCB_COLOR4_DCC_BASE … #define mmCB_COLOR4_DCC_BASE_BASE_IDX … #define mmCB_COLOR5_BASE … #define mmCB_COLOR5_BASE_BASE_IDX … #define mmCB_COLOR5_PITCH … #define mmCB_COLOR5_PITCH_BASE_IDX … #define mmCB_COLOR5_SLICE … #define mmCB_COLOR5_SLICE_BASE_IDX … #define mmCB_COLOR5_VIEW … #define mmCB_COLOR5_VIEW_BASE_IDX … #define mmCB_COLOR5_INFO … #define mmCB_COLOR5_INFO_BASE_IDX … #define mmCB_COLOR5_ATTRIB … #define mmCB_COLOR5_ATTRIB_BASE_IDX … #define mmCB_COLOR5_DCC_CONTROL … #define mmCB_COLOR5_DCC_CONTROL_BASE_IDX … #define mmCB_COLOR5_CMASK … #define mmCB_COLOR5_CMASK_BASE_IDX … #define mmCB_COLOR5_CMASK_SLICE … #define mmCB_COLOR5_CMASK_SLICE_BASE_IDX … #define mmCB_COLOR5_FMASK … #define mmCB_COLOR5_FMASK_BASE_IDX … #define mmCB_COLOR5_FMASK_SLICE … #define mmCB_COLOR5_FMASK_SLICE_BASE_IDX … #define mmCB_COLOR5_CLEAR_WORD0 … #define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX … #define mmCB_COLOR5_CLEAR_WORD1 … #define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX … #define mmCB_COLOR5_DCC_BASE … #define mmCB_COLOR5_DCC_BASE_BASE_IDX … #define mmCB_COLOR6_BASE … #define mmCB_COLOR6_BASE_BASE_IDX … #define mmCB_COLOR6_PITCH … #define mmCB_COLOR6_PITCH_BASE_IDX … #define mmCB_COLOR6_SLICE … #define mmCB_COLOR6_SLICE_BASE_IDX … #define mmCB_COLOR6_VIEW … #define mmCB_COLOR6_VIEW_BASE_IDX … #define mmCB_COLOR6_INFO … #define mmCB_COLOR6_INFO_BASE_IDX … #define mmCB_COLOR6_ATTRIB … #define mmCB_COLOR6_ATTRIB_BASE_IDX … #define mmCB_COLOR6_DCC_CONTROL … #define mmCB_COLOR6_DCC_CONTROL_BASE_IDX … #define mmCB_COLOR6_CMASK … #define mmCB_COLOR6_CMASK_BASE_IDX … #define mmCB_COLOR6_CMASK_SLICE … #define mmCB_COLOR6_CMASK_SLICE_BASE_IDX … #define mmCB_COLOR6_FMASK … #define mmCB_COLOR6_FMASK_BASE_IDX … #define mmCB_COLOR6_FMASK_SLICE … #define mmCB_COLOR6_FMASK_SLICE_BASE_IDX … #define mmCB_COLOR6_CLEAR_WORD0 … #define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX … #define mmCB_COLOR6_CLEAR_WORD1 … #define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX … #define mmCB_COLOR6_DCC_BASE … #define mmCB_COLOR6_DCC_BASE_BASE_IDX … #define mmCB_COLOR7_BASE … #define mmCB_COLOR7_BASE_BASE_IDX … #define mmCB_COLOR7_PITCH … #define mmCB_COLOR7_PITCH_BASE_IDX … #define mmCB_COLOR7_SLICE … #define mmCB_COLOR7_SLICE_BASE_IDX … #define mmCB_COLOR7_VIEW … #define mmCB_COLOR7_VIEW_BASE_IDX … #define mmCB_COLOR7_INFO … #define mmCB_COLOR7_INFO_BASE_IDX … #define mmCB_COLOR7_ATTRIB … #define mmCB_COLOR7_ATTRIB_BASE_IDX … #define mmCB_COLOR7_DCC_CONTROL … #define mmCB_COLOR7_DCC_CONTROL_BASE_IDX … #define mmCB_COLOR7_CMASK … #define mmCB_COLOR7_CMASK_BASE_IDX … #define mmCB_COLOR7_CMASK_SLICE … #define mmCB_COLOR7_CMASK_SLICE_BASE_IDX … #define mmCB_COLOR7_FMASK … #define mmCB_COLOR7_FMASK_BASE_IDX … #define mmCB_COLOR7_FMASK_SLICE … #define mmCB_COLOR7_FMASK_SLICE_BASE_IDX … #define mmCB_COLOR7_CLEAR_WORD0 … #define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX … #define mmCB_COLOR7_CLEAR_WORD1 … #define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX … #define mmCB_COLOR7_DCC_BASE … #define mmCB_COLOR7_DCC_BASE_BASE_IDX … #define mmCB_COLOR0_BASE_EXT … #define mmCB_COLOR0_BASE_EXT_BASE_IDX … #define mmCB_COLOR1_BASE_EXT … #define mmCB_COLOR1_BASE_EXT_BASE_IDX … #define mmCB_COLOR2_BASE_EXT … #define mmCB_COLOR2_BASE_EXT_BASE_IDX … #define mmCB_COLOR3_BASE_EXT … #define mmCB_COLOR3_BASE_EXT_BASE_IDX … #define mmCB_COLOR4_BASE_EXT … #define mmCB_COLOR4_BASE_EXT_BASE_IDX … #define mmCB_COLOR5_BASE_EXT … #define mmCB_COLOR5_BASE_EXT_BASE_IDX … #define mmCB_COLOR6_BASE_EXT … #define mmCB_COLOR6_BASE_EXT_BASE_IDX … #define mmCB_COLOR7_BASE_EXT … #define mmCB_COLOR7_BASE_EXT_BASE_IDX … #define mmCB_COLOR0_CMASK_BASE_EXT … #define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR1_CMASK_BASE_EXT … #define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR2_CMASK_BASE_EXT … #define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR3_CMASK_BASE_EXT … #define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR4_CMASK_BASE_EXT … #define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR5_CMASK_BASE_EXT … #define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR6_CMASK_BASE_EXT … #define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR7_CMASK_BASE_EXT … #define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR0_FMASK_BASE_EXT … #define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR1_FMASK_BASE_EXT … #define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR2_FMASK_BASE_EXT … #define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR3_FMASK_BASE_EXT … #define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR4_FMASK_BASE_EXT … #define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR5_FMASK_BASE_EXT … #define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR6_FMASK_BASE_EXT … #define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR7_FMASK_BASE_EXT … #define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX … #define mmCB_COLOR0_DCC_BASE_EXT … #define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX … #define mmCB_COLOR1_DCC_BASE_EXT … #define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX … #define mmCB_COLOR2_DCC_BASE_EXT … #define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX … #define mmCB_COLOR3_DCC_BASE_EXT … #define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX … #define mmCB_COLOR4_DCC_BASE_EXT … #define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX … #define mmCB_COLOR5_DCC_BASE_EXT … #define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX … #define mmCB_COLOR6_DCC_BASE_EXT … #define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX … #define mmCB_COLOR7_DCC_BASE_EXT … #define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX … #define mmCB_COLOR0_ATTRIB2 … #define mmCB_COLOR0_ATTRIB2_BASE_IDX … #define mmCB_COLOR1_ATTRIB2 … #define mmCB_COLOR1_ATTRIB2_BASE_IDX … #define mmCB_COLOR2_ATTRIB2 … #define mmCB_COLOR2_ATTRIB2_BASE_IDX … #define mmCB_COLOR3_ATTRIB2 … #define mmCB_COLOR3_ATTRIB2_BASE_IDX … #define mmCB_COLOR4_ATTRIB2 … #define mmCB_COLOR4_ATTRIB2_BASE_IDX … #define mmCB_COLOR5_ATTRIB2 … #define mmCB_COLOR5_ATTRIB2_BASE_IDX … #define mmCB_COLOR6_ATTRIB2 … #define mmCB_COLOR6_ATTRIB2_BASE_IDX … #define mmCB_COLOR7_ATTRIB2 … #define mmCB_COLOR7_ATTRIB2_BASE_IDX … #define mmCB_COLOR0_ATTRIB3 … #define mmCB_COLOR0_ATTRIB3_BASE_IDX … #define mmCB_COLOR1_ATTRIB3 … #define mmCB_COLOR1_ATTRIB3_BASE_IDX … #define mmCB_COLOR2_ATTRIB3 … #define mmCB_COLOR2_ATTRIB3_BASE_IDX … #define mmCB_COLOR3_ATTRIB3 … #define mmCB_COLOR3_ATTRIB3_BASE_IDX … #define mmCB_COLOR4_ATTRIB3 … #define mmCB_COLOR4_ATTRIB3_BASE_IDX … #define mmCB_COLOR5_ATTRIB3 … #define mmCB_COLOR5_ATTRIB3_BASE_IDX … #define mmCB_COLOR6_ATTRIB3 … #define mmCB_COLOR6_ATTRIB3_BASE_IDX … #define mmCB_COLOR7_ATTRIB3 … #define mmCB_COLOR7_ATTRIB3_BASE_IDX … // addressBlock: gc_gfxudec // base address: 0x30000 #define mmCP_EOP_DONE_ADDR_LO … #define mmCP_EOP_DONE_ADDR_LO_BASE_IDX … #define mmCP_EOP_DONE_ADDR_HI … #define mmCP_EOP_DONE_ADDR_HI_BASE_IDX … #define mmCP_EOP_DONE_DATA_LO … #define mmCP_EOP_DONE_DATA_LO_BASE_IDX … #define mmCP_EOP_DONE_DATA_HI … #define mmCP_EOP_DONE_DATA_HI_BASE_IDX … #define mmCP_EOP_LAST_FENCE_LO … #define mmCP_EOP_LAST_FENCE_LO_BASE_IDX … #define mmCP_EOP_LAST_FENCE_HI … #define mmCP_EOP_LAST_FENCE_HI_BASE_IDX … #define mmCP_STREAM_OUT_ADDR_LO … #define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX … #define mmCP_STREAM_OUT_ADDR_HI … #define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX … #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO … #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX … #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI … #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX … #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO … #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX … #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI … #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX … #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO … #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX … #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI … #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX … #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO … #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX … #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI … #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX … #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO … #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX … #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI … #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX … #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO … #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX … #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI … #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX … #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO … #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX … #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI … #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX … #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO … #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX … #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI … #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX … #define mmCP_PIPE_STATS_ADDR_LO … #define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX … #define mmCP_PIPE_STATS_ADDR_HI … #define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX … #define mmCP_VGT_IAVERT_COUNT_LO … #define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX … #define mmCP_VGT_IAVERT_COUNT_HI … #define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX … #define mmCP_VGT_IAPRIM_COUNT_LO … #define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX … #define mmCP_VGT_IAPRIM_COUNT_HI … #define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX … #define mmCP_VGT_GSPRIM_COUNT_LO … #define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX … #define mmCP_VGT_GSPRIM_COUNT_HI … #define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX … #define mmCP_VGT_VSINVOC_COUNT_LO … #define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX … #define mmCP_VGT_VSINVOC_COUNT_HI … #define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX … #define mmCP_VGT_GSINVOC_COUNT_LO … #define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX … #define mmCP_VGT_GSINVOC_COUNT_HI … #define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX … #define mmCP_VGT_HSINVOC_COUNT_LO … #define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX … #define mmCP_VGT_HSINVOC_COUNT_HI … #define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX … #define mmCP_VGT_DSINVOC_COUNT_LO … #define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX … #define mmCP_VGT_DSINVOC_COUNT_HI … #define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX … #define mmCP_PA_CINVOC_COUNT_LO … #define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX … #define mmCP_PA_CINVOC_COUNT_HI … #define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX … #define mmCP_PA_CPRIM_COUNT_LO … #define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX … #define mmCP_PA_CPRIM_COUNT_HI … #define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX … #define mmCP_SC_PSINVOC_COUNT0_LO … #define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX … #define mmCP_SC_PSINVOC_COUNT0_HI … #define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX … #define mmCP_SC_PSINVOC_COUNT1_LO … #define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX … #define mmCP_SC_PSINVOC_COUNT1_HI … #define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX … #define mmCP_VGT_CSINVOC_COUNT_LO … #define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX … #define mmCP_VGT_CSINVOC_COUNT_HI … #define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX … #define mmCP_EOP_DONE_DOORBELL … #define mmCP_EOP_DONE_DOORBELL_BASE_IDX … #define mmCP_STREAM_OUT_DOORBELL … #define mmCP_STREAM_OUT_DOORBELL_BASE_IDX … #define mmCP_SEM_DOORBELL … #define mmCP_SEM_DOORBELL_BASE_IDX … #define mmCP_PIPE_STATS_CONTROL … #define mmCP_PIPE_STATS_CONTROL_BASE_IDX … #define mmCP_STREAM_OUT_CONTROL … #define mmCP_STREAM_OUT_CONTROL_BASE_IDX … #define mmCP_STRMOUT_CNTL … #define mmCP_STRMOUT_CNTL_BASE_IDX … #define mmSCRATCH_REG0 … #define mmSCRATCH_REG0_BASE_IDX … #define mmSCRATCH_REG1 … #define mmSCRATCH_REG1_BASE_IDX … #define mmSCRATCH_REG2 … #define mmSCRATCH_REG2_BASE_IDX … #define mmSCRATCH_REG3 … #define mmSCRATCH_REG3_BASE_IDX … #define mmSCRATCH_REG4 … #define mmSCRATCH_REG4_BASE_IDX … #define mmSCRATCH_REG5 … #define mmSCRATCH_REG5_BASE_IDX … #define mmSCRATCH_REG6 … #define mmSCRATCH_REG6_BASE_IDX … #define mmSCRATCH_REG7 … #define mmSCRATCH_REG7_BASE_IDX … #define mmCP_PIPE_STATS_DOORBELL … #define mmCP_PIPE_STATS_DOORBELL_BASE_IDX … #define mmCP_APPEND_DDID_CNT … #define mmCP_APPEND_DDID_CNT_BASE_IDX … #define mmCP_APPEND_DATA_HI … #define mmCP_APPEND_DATA_HI_BASE_IDX … #define mmCP_APPEND_LAST_CS_FENCE_HI … #define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX … #define mmCP_APPEND_LAST_PS_FENCE_HI … #define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX … #define mmSCRATCH_UMSK … #define mmSCRATCH_UMSK_BASE_IDX … #define mmSCRATCH_ADDR … #define mmSCRATCH_ADDR_BASE_IDX … #define mmCP_PFP_ATOMIC_PREOP_LO … #define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX … #define mmCP_PFP_ATOMIC_PREOP_HI … #define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX … #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO … #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX … #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI … #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX … #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO … #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX … #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI … #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX … #define mmCP_APPEND_ADDR_LO … #define mmCP_APPEND_ADDR_LO_BASE_IDX … #define mmCP_APPEND_ADDR_HI … #define mmCP_APPEND_ADDR_HI_BASE_IDX … #define mmCP_APPEND_DATA … #define mmCP_APPEND_DATA_BASE_IDX … #define mmCP_APPEND_DATA_LO … #define mmCP_APPEND_DATA_LO_BASE_IDX … #define mmCP_APPEND_LAST_CS_FENCE … #define mmCP_APPEND_LAST_CS_FENCE_BASE_IDX … #define mmCP_APPEND_LAST_CS_FENCE_LO … #define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX … #define mmCP_APPEND_LAST_PS_FENCE … #define mmCP_APPEND_LAST_PS_FENCE_BASE_IDX … #define mmCP_APPEND_LAST_PS_FENCE_LO … #define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX … #define mmCP_ATOMIC_PREOP_LO … #define mmCP_ATOMIC_PREOP_LO_BASE_IDX … #define mmCP_ME_ATOMIC_PREOP_LO … #define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX … #define mmCP_ATOMIC_PREOP_HI … #define mmCP_ATOMIC_PREOP_HI_BASE_IDX … #define mmCP_ME_ATOMIC_PREOP_HI … #define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX … #define mmCP_GDS_ATOMIC0_PREOP_LO … #define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX … #define mmCP_ME_GDS_ATOMIC0_PREOP_LO … #define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX … #define mmCP_GDS_ATOMIC0_PREOP_HI … #define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX … #define mmCP_ME_GDS_ATOMIC0_PREOP_HI … #define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX … #define mmCP_GDS_ATOMIC1_PREOP_LO … #define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX … #define mmCP_ME_GDS_ATOMIC1_PREOP_LO … #define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX … #define mmCP_GDS_ATOMIC1_PREOP_HI … #define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX … #define mmCP_ME_GDS_ATOMIC1_PREOP_HI … #define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX … #define mmCP_ME_MC_WADDR_LO … #define mmCP_ME_MC_WADDR_LO_BASE_IDX … #define mmCP_ME_MC_WADDR_HI … #define mmCP_ME_MC_WADDR_HI_BASE_IDX … #define mmCP_ME_MC_WDATA_LO … #define mmCP_ME_MC_WDATA_LO_BASE_IDX … #define mmCP_ME_MC_WDATA_HI … #define mmCP_ME_MC_WDATA_HI_BASE_IDX … #define mmCP_ME_MC_RADDR_LO … #define mmCP_ME_MC_RADDR_LO_BASE_IDX … #define mmCP_ME_MC_RADDR_HI … #define mmCP_ME_MC_RADDR_HI_BASE_IDX … #define mmCP_SEM_WAIT_TIMER … #define mmCP_SEM_WAIT_TIMER_BASE_IDX … #define mmCP_SIG_SEM_ADDR_LO … #define mmCP_SIG_SEM_ADDR_LO_BASE_IDX … #define mmCP_SIG_SEM_ADDR_HI … #define mmCP_SIG_SEM_ADDR_HI_BASE_IDX … #define mmCP_WAIT_REG_MEM_TIMEOUT … #define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX … #define mmCP_WAIT_SEM_ADDR_LO … #define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX … #define mmCP_WAIT_SEM_ADDR_HI … #define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX … #define mmCP_DMA_PFP_CONTROL … #define mmCP_DMA_PFP_CONTROL_BASE_IDX … #define mmCP_DMA_ME_CONTROL … #define mmCP_DMA_ME_CONTROL_BASE_IDX … #define mmCP_COHER_BASE_HI … #define mmCP_COHER_BASE_HI_BASE_IDX … #define mmCP_COHER_START_DELAY … #define mmCP_COHER_START_DELAY_BASE_IDX … #define mmCP_COHER_CNTL … #define mmCP_COHER_CNTL_BASE_IDX … #define mmCP_COHER_SIZE … #define mmCP_COHER_SIZE_BASE_IDX … #define mmCP_COHER_BASE … #define mmCP_COHER_BASE_BASE_IDX … #define mmCP_COHER_STATUS … #define mmCP_COHER_STATUS_BASE_IDX … #define mmCP_DMA_ME_SRC_ADDR … #define mmCP_DMA_ME_SRC_ADDR_BASE_IDX … #define mmCP_DMA_ME_SRC_ADDR_HI … #define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX … #define mmCP_DMA_ME_DST_ADDR … #define mmCP_DMA_ME_DST_ADDR_BASE_IDX … #define mmCP_DMA_ME_DST_ADDR_HI … #define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX … #define mmCP_DMA_ME_COMMAND … #define mmCP_DMA_ME_COMMAND_BASE_IDX … #define mmCP_DMA_PFP_SRC_ADDR … #define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX … #define mmCP_DMA_PFP_SRC_ADDR_HI … #define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX … #define mmCP_DMA_PFP_DST_ADDR … #define mmCP_DMA_PFP_DST_ADDR_BASE_IDX … #define mmCP_DMA_PFP_DST_ADDR_HI … #define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX … #define mmCP_DMA_PFP_COMMAND … #define mmCP_DMA_PFP_COMMAND_BASE_IDX … #define mmCP_DMA_CNTL … #define mmCP_DMA_CNTL_BASE_IDX … #define mmCP_DMA_READ_TAGS … #define mmCP_DMA_READ_TAGS_BASE_IDX … #define mmCP_COHER_SIZE_HI … #define mmCP_COHER_SIZE_HI_BASE_IDX … #define mmCP_PFP_IB_CONTROL … #define mmCP_PFP_IB_CONTROL_BASE_IDX … #define mmCP_PFP_LOAD_CONTROL … #define mmCP_PFP_LOAD_CONTROL_BASE_IDX … #define mmCP_SCRATCH_INDEX … #define mmCP_SCRATCH_INDEX_BASE_IDX … #define mmCP_SCRATCH_DATA … #define mmCP_SCRATCH_DATA_BASE_IDX … #define mmCP_RB_OFFSET … #define mmCP_RB_OFFSET_BASE_IDX … #define mmCP_IB1_OFFSET … #define mmCP_IB1_OFFSET_BASE_IDX … #define mmCP_IB2_OFFSET … #define mmCP_IB2_OFFSET_BASE_IDX … #define mmCP_IB1_PREAMBLE_BEGIN … #define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX … #define mmCP_IB1_PREAMBLE_END … #define mmCP_IB1_PREAMBLE_END_BASE_IDX … #define mmCP_IB2_PREAMBLE_BEGIN … #define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX … #define mmCP_IB2_PREAMBLE_END … #define mmCP_IB2_PREAMBLE_END_BASE_IDX … #define mmCP_CE_IB1_OFFSET … #define mmCP_CE_IB1_OFFSET_BASE_IDX … #define mmCP_CE_IB2_OFFSET … #define mmCP_CE_IB2_OFFSET_BASE_IDX … #define mmCP_CE_COUNTER … #define mmCP_CE_COUNTER_BASE_IDX … #define mmCP_DMA_ME_CMD_ADDR_LO … #define mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX … #define mmCP_DMA_ME_CMD_ADDR_HI … #define mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX … #define mmCP_DMA_PFP_CMD_ADDR_LO … #define mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX … #define mmCP_DMA_PFP_CMD_ADDR_HI … #define mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX … #define mmCP_APPEND_CMD_ADDR_LO … #define mmCP_APPEND_CMD_ADDR_LO_BASE_IDX … #define mmCP_APPEND_CMD_ADDR_HI … #define mmCP_APPEND_CMD_ADDR_HI_BASE_IDX … #define mmCP_CE_INIT_CMD_BUFSZ … #define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX … #define mmCP_CE_IB1_CMD_BUFSZ … #define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX … #define mmCP_CE_IB2_CMD_BUFSZ … #define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX … #define mmCP_IB1_CMD_BUFSZ … #define mmCP_IB1_CMD_BUFSZ_BASE_IDX … #define mmCP_IB2_CMD_BUFSZ … #define mmCP_IB2_CMD_BUFSZ_BASE_IDX … #define mmCP_ST_CMD_BUFSZ … #define mmCP_ST_CMD_BUFSZ_BASE_IDX … #define mmCP_CE_INIT_BASE_LO … #define mmCP_CE_INIT_BASE_LO_BASE_IDX … #define mmCP_CE_INIT_BASE_HI … #define mmCP_CE_INIT_BASE_HI_BASE_IDX … #define mmCP_CE_INIT_BUFSZ … #define mmCP_CE_INIT_BUFSZ_BASE_IDX … #define mmCP_CE_IB1_BASE_LO … #define mmCP_CE_IB1_BASE_LO_BASE_IDX … #define mmCP_CE_IB1_BASE_HI … #define mmCP_CE_IB1_BASE_HI_BASE_IDX … #define mmCP_CE_IB1_BUFSZ … #define mmCP_CE_IB1_BUFSZ_BASE_IDX … #define mmCP_CE_IB2_BASE_LO … #define mmCP_CE_IB2_BASE_LO_BASE_IDX … #define mmCP_CE_IB2_BASE_HI … #define mmCP_CE_IB2_BASE_HI_BASE_IDX … #define mmCP_CE_IB2_BUFSZ … #define mmCP_CE_IB2_BUFSZ_BASE_IDX … #define mmCP_IB1_BASE_LO … #define mmCP_IB1_BASE_LO_BASE_IDX … #define mmCP_IB1_BASE_HI … #define mmCP_IB1_BASE_HI_BASE_IDX … #define mmCP_IB1_BUFSZ … #define mmCP_IB1_BUFSZ_BASE_IDX … #define mmCP_IB2_BASE_LO … #define mmCP_IB2_BASE_LO_BASE_IDX … #define mmCP_IB2_BASE_HI … #define mmCP_IB2_BASE_HI_BASE_IDX … #define mmCP_IB2_BUFSZ … #define mmCP_IB2_BUFSZ_BASE_IDX … #define mmCP_ST_BASE_LO … #define mmCP_ST_BASE_LO_BASE_IDX … #define mmCP_ST_BASE_HI … #define mmCP_ST_BASE_HI_BASE_IDX … #define mmCP_ST_BUFSZ … #define mmCP_ST_BUFSZ_BASE_IDX … #define mmCP_EOP_DONE_EVENT_CNTL … #define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX … #define mmCP_EOP_DONE_DATA_CNTL … #define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX … #define mmCP_EOP_DONE_CNTX_ID … #define mmCP_EOP_DONE_CNTX_ID_BASE_IDX … #define mmCP_DB_BASE_LO … #define mmCP_DB_BASE_LO_BASE_IDX … #define mmCP_DB_BASE_HI … #define mmCP_DB_BASE_HI_BASE_IDX … #define mmCP_DB_BUFSZ … #define mmCP_DB_BUFSZ_BASE_IDX … #define mmCP_DB_CMD_BUFSZ … #define mmCP_DB_CMD_BUFSZ_BASE_IDX … #define mmCP_CE_DB_BASE_LO … #define mmCP_CE_DB_BASE_LO_BASE_IDX … #define mmCP_CE_DB_BASE_HI … #define mmCP_CE_DB_BASE_HI_BASE_IDX … #define mmCP_CE_DB_BUFSZ … #define mmCP_CE_DB_BUFSZ_BASE_IDX … #define mmCP_CE_DB_CMD_BUFSZ … #define mmCP_CE_DB_CMD_BUFSZ_BASE_IDX … #define mmCP_PFP_COMPLETION_STATUS … #define mmCP_PFP_COMPLETION_STATUS_BASE_IDX … #define mmCP_CE_COMPLETION_STATUS … #define mmCP_CE_COMPLETION_STATUS_BASE_IDX … #define mmCP_PRED_NOT_VISIBLE … #define mmCP_PRED_NOT_VISIBLE_BASE_IDX … #define mmCP_PFP_METADATA_BASE_ADDR … #define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX … #define mmCP_PFP_METADATA_BASE_ADDR_HI … #define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX … #define mmCP_CE_METADATA_BASE_ADDR … #define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX … #define mmCP_CE_METADATA_BASE_ADDR_HI … #define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX … #define mmCP_DRAW_INDX_INDR_ADDR … #define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX … #define mmCP_DRAW_INDX_INDR_ADDR_HI … #define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX … #define mmCP_DISPATCH_INDR_ADDR … #define mmCP_DISPATCH_INDR_ADDR_BASE_IDX … #define mmCP_DISPATCH_INDR_ADDR_HI … #define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX … #define mmCP_INDEX_BASE_ADDR … #define mmCP_INDEX_BASE_ADDR_BASE_IDX … #define mmCP_INDEX_BASE_ADDR_HI … #define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX … #define mmCP_INDEX_TYPE … #define mmCP_INDEX_TYPE_BASE_IDX … #define mmCP_GDS_BKUP_ADDR … #define mmCP_GDS_BKUP_ADDR_BASE_IDX … #define mmCP_GDS_BKUP_ADDR_HI … #define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX … #define mmCP_SAMPLE_STATUS … #define mmCP_SAMPLE_STATUS_BASE_IDX … #define mmCP_ME_COHER_CNTL … #define mmCP_ME_COHER_CNTL_BASE_IDX … #define mmCP_ME_COHER_SIZE … #define mmCP_ME_COHER_SIZE_BASE_IDX … #define mmCP_ME_COHER_SIZE_HI … #define mmCP_ME_COHER_SIZE_HI_BASE_IDX … #define mmCP_ME_COHER_BASE … #define mmCP_ME_COHER_BASE_BASE_IDX … #define mmCP_ME_COHER_BASE_HI … #define mmCP_ME_COHER_BASE_HI_BASE_IDX … #define mmCP_ME_COHER_STATUS … #define mmCP_ME_COHER_STATUS_BASE_IDX … #define mmRLC_GPM_PERF_COUNT_0 … #define mmRLC_GPM_PERF_COUNT_0_BASE_IDX … #define mmRLC_GPM_PERF_COUNT_1 … #define mmRLC_GPM_PERF_COUNT_1_BASE_IDX … #define mmGRBM_GFX_INDEX … #define mmGRBM_GFX_INDEX_BASE_IDX … #define mmVGT_ESGS_RING_SIZE_UMD … #define mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX … #define mmVGT_GSVS_RING_SIZE_UMD … #define mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX … #define mmVGT_PRIMITIVE_TYPE … #define mmVGT_PRIMITIVE_TYPE_BASE_IDX … #define mmVGT_INDEX_TYPE … #define mmVGT_INDEX_TYPE_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 … #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 … #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 … #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX … #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 … #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX … #define mmGE_MIN_VTX_INDX … #define mmGE_MIN_VTX_INDX_BASE_IDX … #define mmGE_INDX_OFFSET … #define mmGE_INDX_OFFSET_BASE_IDX … #define mmGE_MULTI_PRIM_IB_RESET_EN … #define mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX … #define mmVGT_NUM_INDICES … #define mmVGT_NUM_INDICES_BASE_IDX … #define mmVGT_NUM_INSTANCES … #define mmVGT_NUM_INSTANCES_BASE_IDX … #define mmVGT_TF_RING_SIZE_UMD … #define mmVGT_TF_RING_SIZE_UMD_BASE_IDX … #define mmVGT_HS_OFFCHIP_PARAM_UMD … #define mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX … #define mmVGT_TF_MEMORY_BASE_UMD … #define mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX … #define mmGE_DMA_FIRST_INDEX … #define mmGE_DMA_FIRST_INDEX_BASE_IDX … #define mmWD_POS_BUF_BASE … #define mmWD_POS_BUF_BASE_BASE_IDX … #define mmWD_POS_BUF_BASE_HI … #define mmWD_POS_BUF_BASE_HI_BASE_IDX … #define mmWD_CNTL_SB_BUF_BASE … #define mmWD_CNTL_SB_BUF_BASE_BASE_IDX … #define mmWD_CNTL_SB_BUF_BASE_HI … #define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX … #define mmWD_INDEX_BUF_BASE … #define mmWD_INDEX_BUF_BASE_BASE_IDX … #define mmWD_INDEX_BUF_BASE_HI … #define mmWD_INDEX_BUF_BASE_HI_BASE_IDX … #define mmIA_MULTI_VGT_PARAM_PIPED … #define mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX … #define mmGE_MAX_VTX_INDX … #define mmGE_MAX_VTX_INDX_BASE_IDX … #define mmVGT_INSTANCE_BASE_ID … #define mmVGT_INSTANCE_BASE_ID_BASE_IDX … #define mmGE_CNTL … #define mmGE_CNTL_BASE_IDX … #define mmGE_USER_VGPR1 … #define mmGE_USER_VGPR1_BASE_IDX … #define mmGE_USER_VGPR2 … #define mmGE_USER_VGPR2_BASE_IDX … #define mmGE_USER_VGPR3 … #define mmGE_USER_VGPR3_BASE_IDX … #define mmGE_STEREO_CNTL … #define mmGE_STEREO_CNTL_BASE_IDX … #define mmGE_PC_ALLOC … #define mmGE_PC_ALLOC_BASE_IDX … #define mmVGT_TF_MEMORY_BASE_HI_UMD … #define mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX … #define mmGE_USER_VGPR_EN … #define mmGE_USER_VGPR_EN_BASE_IDX … #define mmPA_SU_LINE_STIPPLE_VALUE … #define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX … #define mmPA_SC_LINE_STIPPLE_STATE … #define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX … #define mmPA_SC_SCREEN_EXTENT_MIN_0 … #define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX … #define mmPA_SC_SCREEN_EXTENT_MAX_0 … #define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX … #define mmPA_SC_SCREEN_EXTENT_MIN_1 … #define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX … #define mmPA_SC_SCREEN_EXTENT_MAX_1 … #define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX … #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN … #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX … #define mmPA_SC_P3D_TRAP_SCREEN_H … #define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX … #define mmPA_SC_P3D_TRAP_SCREEN_V … #define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX … #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE … #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define mmPA_SC_P3D_TRAP_SCREEN_COUNT … #define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX … #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN … #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX … #define mmPA_SC_HP3D_TRAP_SCREEN_H … #define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX … #define mmPA_SC_HP3D_TRAP_SCREEN_V … #define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX … #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE … #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT … #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX … #define mmPA_SC_TRAP_SCREEN_HV_EN … #define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX … #define mmPA_SC_TRAP_SCREEN_H … #define mmPA_SC_TRAP_SCREEN_H_BASE_IDX … #define mmPA_SC_TRAP_SCREEN_V … #define mmPA_SC_TRAP_SCREEN_V_BASE_IDX … #define mmPA_SC_TRAP_SCREEN_OCCURRENCE … #define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define mmPA_SC_TRAP_SCREEN_COUNT … #define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX … #define mmSQ_THREAD_TRACE_USERDATA_0 … #define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX … #define mmSQ_THREAD_TRACE_USERDATA_1 … #define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX … #define mmSQ_THREAD_TRACE_USERDATA_2 … #define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX … #define mmSQ_THREAD_TRACE_USERDATA_3 … #define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX … #define mmSQ_THREAD_TRACE_USERDATA_4 … #define mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX … #define mmSQ_THREAD_TRACE_USERDATA_5 … #define mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX … #define mmSQ_THREAD_TRACE_USERDATA_6 … #define mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX … #define mmSQ_THREAD_TRACE_USERDATA_7 … #define mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX … #define mmSQC_CACHES … #define mmSQC_CACHES_BASE_IDX … #define mmSQC_WRITEBACK … #define mmSQC_WRITEBACK_BASE_IDX … #define mmTA_CS_BC_BASE_ADDR … #define mmTA_CS_BC_BASE_ADDR_BASE_IDX … #define mmTA_CS_BC_BASE_ADDR_HI … #define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX … #define mmDB_OCCLUSION_COUNT0_LOW … #define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX … #define mmDB_OCCLUSION_COUNT0_HI … #define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX … #define mmDB_OCCLUSION_COUNT1_LOW … #define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX … #define mmDB_OCCLUSION_COUNT1_HI … #define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX … #define mmDB_OCCLUSION_COUNT2_LOW … #define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX … #define mmDB_OCCLUSION_COUNT2_HI … #define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX … #define mmDB_OCCLUSION_COUNT3_LOW … #define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX … #define mmDB_OCCLUSION_COUNT3_HI … #define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX … #define mmDB_ZPASS_COUNT_LOW … #define mmDB_ZPASS_COUNT_LOW_BASE_IDX … #define mmDB_ZPASS_COUNT_HI … #define mmDB_ZPASS_COUNT_HI_BASE_IDX … #define mmGDS_RD_ADDR … #define mmGDS_RD_ADDR_BASE_IDX … #define mmGDS_RD_DATA … #define mmGDS_RD_DATA_BASE_IDX … #define mmGDS_RD_BURST_ADDR … #define mmGDS_RD_BURST_ADDR_BASE_IDX … #define mmGDS_RD_BURST_COUNT … #define mmGDS_RD_BURST_COUNT_BASE_IDX … #define mmGDS_RD_BURST_DATA … #define mmGDS_RD_BURST_DATA_BASE_IDX … #define mmGDS_WR_ADDR … #define mmGDS_WR_ADDR_BASE_IDX … #define mmGDS_WR_DATA … #define mmGDS_WR_DATA_BASE_IDX … #define mmGDS_WR_BURST_ADDR … #define mmGDS_WR_BURST_ADDR_BASE_IDX … #define mmGDS_WR_BURST_DATA … #define mmGDS_WR_BURST_DATA_BASE_IDX … #define mmGDS_WRITE_COMPLETE … #define mmGDS_WRITE_COMPLETE_BASE_IDX … #define mmGDS_ATOM_CNTL … #define mmGDS_ATOM_CNTL_BASE_IDX … #define mmGDS_ATOM_COMPLETE … #define mmGDS_ATOM_COMPLETE_BASE_IDX … #define mmGDS_ATOM_BASE … #define mmGDS_ATOM_BASE_BASE_IDX … #define mmGDS_ATOM_SIZE … #define mmGDS_ATOM_SIZE_BASE_IDX … #define mmGDS_ATOM_OFFSET0 … #define mmGDS_ATOM_OFFSET0_BASE_IDX … #define mmGDS_ATOM_OFFSET1 … #define mmGDS_ATOM_OFFSET1_BASE_IDX … #define mmGDS_ATOM_DST … #define mmGDS_ATOM_DST_BASE_IDX … #define mmGDS_ATOM_OP … #define mmGDS_ATOM_OP_BASE_IDX … #define mmGDS_ATOM_SRC0 … #define mmGDS_ATOM_SRC0_BASE_IDX … #define mmGDS_ATOM_SRC0_U … #define mmGDS_ATOM_SRC0_U_BASE_IDX … #define mmGDS_ATOM_SRC1 … #define mmGDS_ATOM_SRC1_BASE_IDX … #define mmGDS_ATOM_SRC1_U … #define mmGDS_ATOM_SRC1_U_BASE_IDX … #define mmGDS_ATOM_READ0 … #define mmGDS_ATOM_READ0_BASE_IDX … #define mmGDS_ATOM_READ0_U … #define mmGDS_ATOM_READ0_U_BASE_IDX … #define mmGDS_ATOM_READ1 … #define mmGDS_ATOM_READ1_BASE_IDX … #define mmGDS_ATOM_READ1_U … #define mmGDS_ATOM_READ1_U_BASE_IDX … #define mmGDS_GWS_RESOURCE_CNTL … #define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX … #define mmGDS_GWS_RESOURCE … #define mmGDS_GWS_RESOURCE_BASE_IDX … #define mmGDS_GWS_RESOURCE_CNT … #define mmGDS_GWS_RESOURCE_CNT_BASE_IDX … #define mmGDS_OA_CNTL … #define mmGDS_OA_CNTL_BASE_IDX … #define mmGDS_OA_COUNTER … #define mmGDS_OA_COUNTER_BASE_IDX … #define mmGDS_OA_ADDRESS … #define mmGDS_OA_ADDRESS_BASE_IDX … #define mmGDS_OA_INCDEC … #define mmGDS_OA_INCDEC_BASE_IDX … #define mmGDS_OA_RING_SIZE … #define mmGDS_OA_RING_SIZE_BASE_IDX … #define mmSPI_CONFIG_CNTL_REMAP … #define mmSPI_CONFIG_CNTL_REMAP_BASE_IDX … #define mmSPI_CONFIG_CNTL_1_REMAP … #define mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX … #define mmSPI_CONFIG_CNTL_2_REMAP … #define mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX … #define mmSPI_WAVE_LIMIT_CNTL_REMAP … #define mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX … // addressBlock: gc_cprs64dec // base address: 0x32000 #define mmCP_MES_PRGRM_CNTR_START … #define mmCP_MES_PRGRM_CNTR_START_BASE_IDX … #define mmCP_MES_INTR_ROUTINE_START … #define mmCP_MES_INTR_ROUTINE_START_BASE_IDX … #define mmCP_MES_MTVEC_LO … #define mmCP_MES_MTVEC_LO_BASE_IDX … #define mmCP_MES_MTVEC_HI … #define mmCP_MES_MTVEC_HI_BASE_IDX … #define mmCP_MES_CNTL … #define mmCP_MES_CNTL_BASE_IDX … #define mmCP_MES_PIPE_PRIORITY_CNTS … #define mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX … #define mmCP_MES_PIPE0_PRIORITY … #define mmCP_MES_PIPE0_PRIORITY_BASE_IDX … #define mmCP_MES_PIPE1_PRIORITY … #define mmCP_MES_PIPE1_PRIORITY_BASE_IDX … #define mmCP_MES_PIPE2_PRIORITY … #define mmCP_MES_PIPE2_PRIORITY_BASE_IDX … #define mmCP_MES_PIPE3_PRIORITY … #define mmCP_MES_PIPE3_PRIORITY_BASE_IDX … #define mmCP_MES_HEADER_DUMP … #define mmCP_MES_HEADER_DUMP_BASE_IDX … #define mmCP_MES_MIE_LO … #define mmCP_MES_MIE_LO_BASE_IDX … #define mmCP_MES_MIE_HI … #define mmCP_MES_MIE_HI_BASE_IDX … #define mmCP_MES_INTERRUPT … #define mmCP_MES_INTERRUPT_BASE_IDX … #define mmCP_MES_SCRATCH_INDEX … #define mmCP_MES_SCRATCH_INDEX_BASE_IDX … #define mmCP_MES_SCRATCH_DATA … #define mmCP_MES_SCRATCH_DATA_BASE_IDX … #define mmCP_MES_INSTR_PNTR … #define mmCP_MES_INSTR_PNTR_BASE_IDX … #define mmCP_MES_MSCRATCH_HI … #define mmCP_MES_MSCRATCH_HI_BASE_IDX … #define mmCP_MES_MSCRATCH_LO … #define mmCP_MES_MSCRATCH_LO_BASE_IDX … #define mmCP_MES_MSTATUS_LO … #define mmCP_MES_MSTATUS_LO_BASE_IDX … #define mmCP_MES_MSTATUS_HI … #define mmCP_MES_MSTATUS_HI_BASE_IDX … #define mmCP_MES_MEPC_LO … #define mmCP_MES_MEPC_LO_BASE_IDX … #define mmCP_MES_MEPC_HI … #define mmCP_MES_MEPC_HI_BASE_IDX … #define mmCP_MES_MCAUSE_LO … #define mmCP_MES_MCAUSE_LO_BASE_IDX … #define mmCP_MES_MCAUSE_HI … #define mmCP_MES_MCAUSE_HI_BASE_IDX … #define mmCP_MES_MBADADDR_LO … #define mmCP_MES_MBADADDR_LO_BASE_IDX … #define mmCP_MES_MBADADDR_HI … #define mmCP_MES_MBADADDR_HI_BASE_IDX … #define mmCP_MES_MIP_LO … #define mmCP_MES_MIP_LO_BASE_IDX … #define mmCP_MES_MIP_HI … #define mmCP_MES_MIP_HI_BASE_IDX … #define mmCP_MES_MCYCLE_LO … #define mmCP_MES_MCYCLE_LO_BASE_IDX … #define mmCP_MES_MCYCLE_HI … #define mmCP_MES_MCYCLE_HI_BASE_IDX … #define mmCP_MES_MTIME_LO … #define mmCP_MES_MTIME_LO_BASE_IDX … #define mmCP_MES_MTIME_HI … #define mmCP_MES_MTIME_HI_BASE_IDX … #define mmCP_MES_MINSTRET_LO … #define mmCP_MES_MINSTRET_LO_BASE_IDX … #define mmCP_MES_MINSTRET_HI … #define mmCP_MES_MINSTRET_HI_BASE_IDX … #define mmCP_MES_MISA_LO … #define mmCP_MES_MISA_LO_BASE_IDX … #define mmCP_MES_MISA_HI … #define mmCP_MES_MISA_HI_BASE_IDX … #define mmCP_MES_MVENDORID_LO … #define mmCP_MES_MVENDORID_LO_BASE_IDX … #define mmCP_MES_MVENDORID_HI … #define mmCP_MES_MVENDORID_HI_BASE_IDX … #define mmCP_MES_MARCHID_LO … #define mmCP_MES_MARCHID_LO_BASE_IDX … #define mmCP_MES_MARCHID_HI … #define mmCP_MES_MARCHID_HI_BASE_IDX … #define mmCP_MES_MIMPID_LO … #define mmCP_MES_MIMPID_LO_BASE_IDX … #define mmCP_MES_MIMPID_HI … #define mmCP_MES_MIMPID_HI_BASE_IDX … #define mmCP_MES_MHARTID_LO … #define mmCP_MES_MHARTID_LO_BASE_IDX … #define mmCP_MES_MHARTID_HI … #define mmCP_MES_MHARTID_HI_BASE_IDX … #define mmCP_MES_DC_BASE_CNTL … #define mmCP_MES_DC_BASE_CNTL_BASE_IDX … #define mmCP_MES_DC_OP_CNTL … #define mmCP_MES_DC_OP_CNTL_BASE_IDX … #define mmCP_MES_MTIMECMP_LO … #define mmCP_MES_MTIMECMP_LO_BASE_IDX … #define mmCP_MES_MTIMECMP_HI … #define mmCP_MES_MTIMECMP_HI_BASE_IDX … #define mmCP_MES_PROCESS_QUANTUM_PIPE0 … #define mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX … #define mmCP_MES_PROCESS_QUANTUM_PIPE1 … #define mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX … #define mmCP_MES_DOORBELL_CONTROL1 … #define mmCP_MES_DOORBELL_CONTROL1_BASE_IDX … #define mmCP_MES_DOORBELL_CONTROL2 … #define mmCP_MES_DOORBELL_CONTROL2_BASE_IDX … #define mmCP_MES_DOORBELL_CONTROL3 … #define mmCP_MES_DOORBELL_CONTROL3_BASE_IDX … #define mmCP_MES_DOORBELL_CONTROL4 … #define mmCP_MES_DOORBELL_CONTROL4_BASE_IDX … #define mmCP_MES_DOORBELL_CONTROL5 … #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX … #define mmCP_MES_DOORBELL_CONTROL6 … #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX … #define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR … #define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX … #define mmCP_MES_GP0_LO … #define mmCP_MES_GP0_LO_BASE_IDX … #define mmCP_MES_GP0_HI … #define mmCP_MES_GP0_HI_BASE_IDX … #define mmCP_MES_GP1_LO … #define mmCP_MES_GP1_LO_BASE_IDX … #define mmCP_MES_GP1_HI … #define mmCP_MES_GP1_HI_BASE_IDX … #define mmCP_MES_GP2_LO … #define mmCP_MES_GP2_LO_BASE_IDX … #define mmCP_MES_GP2_HI … #define mmCP_MES_GP2_HI_BASE_IDX … #define mmCP_MES_GP3_LO … #define mmCP_MES_GP3_LO_BASE_IDX … #define mmCP_MES_GP3_HI … #define mmCP_MES_GP3_HI_BASE_IDX … #define mmCP_MES_GP4_LO … #define mmCP_MES_GP4_LO_BASE_IDX … #define mmCP_MES_GP4_HI … #define mmCP_MES_GP4_HI_BASE_IDX … #define mmCP_MES_GP5_LO … #define mmCP_MES_GP5_LO_BASE_IDX … #define mmCP_MES_GP5_HI … #define mmCP_MES_GP5_HI_BASE_IDX … #define mmCP_MES_GP6_LO … #define mmCP_MES_GP6_LO_BASE_IDX … #define mmCP_MES_GP6_HI … #define mmCP_MES_GP6_HI_BASE_IDX … #define mmCP_MES_GP7_LO … #define mmCP_MES_GP7_LO_BASE_IDX … #define mmCP_MES_GP7_HI … #define mmCP_MES_GP7_HI_BASE_IDX … #define mmCP_MES_GP8_LO … #define mmCP_MES_GP8_LO_BASE_IDX … #define mmCP_MES_GP8_HI … #define mmCP_MES_GP8_HI_BASE_IDX … #define mmCP_MES_GP9_LO … #define mmCP_MES_GP9_LO_BASE_IDX … #define mmCP_MES_GP9_HI … #define mmCP_MES_GP9_HI_BASE_IDX … #define mmCP_MES_DM_INDEX_ADDR … #define mmCP_MES_DM_INDEX_ADDR_BASE_IDX … #define mmCP_MES_DM_INDEX_DATA … #define mmCP_MES_DM_INDEX_DATA_BASE_IDX … #define mmCP_MES_DMCONTROL … #define mmCP_MES_DMCONTROL_BASE_IDX … #define mmCP_MES_DMINFO … #define mmCP_MES_DMINFO_BASE_IDX … #define mmCP_MES_SETHALTNOTIFICATION … #define mmCP_MES_SETHALTNOTIFICATION_BASE_IDX … #define mmCP_MES_TSELCT_LOW … #define mmCP_MES_TSELCT_LOW_BASE_IDX … #define mmCP_MES_TSELCT_HIGH … #define mmCP_MES_TSELCT_HIGH_BASE_IDX … #define mmCP_MES_TDATA1_LOW … #define mmCP_MES_TDATA1_LOW_BASE_IDX … #define mmCP_MES_TDATA1_HIGH … #define mmCP_MES_TDATA1_HIGH_BASE_IDX … #define mmCP_MES_TDATA2_LOW … #define mmCP_MES_TDATA2_LOW_BASE_IDX … #define mmCP_MES_TDATA2_HIGH … #define mmCP_MES_TDATA2_HIGH_BASE_IDX … #define mmCP_MES_TDATA3_LOW … #define mmCP_MES_TDATA3_LOW_BASE_IDX … #define mmCP_MES_TDATA3_HIH … #define mmCP_MES_TDATA3_HIH_BASE_IDX … #define mmCP_MES_DCSR … #define mmCP_MES_DCSR_BASE_IDX … #define mmCP_MES_DPC_LOW … #define mmCP_MES_DPC_LOW_BASE_IDX … #define mmCP_MES_DPC_HIGH … #define mmCP_MES_DPC_HIGH_BASE_IDX … #define mmCP_MES_DSCRATCH_LOW … #define mmCP_MES_DSCRATCH_LOW_BASE_IDX … #define mmCP_MES_DSCRATCH_HIGH … #define mmCP_MES_DSCRATCH_HIGH_BASE_IDX … #define mmCP_MES_PERFCOUNT_CNTL … #define mmCP_MES_PERFCOUNT_CNTL_BASE_IDX … // addressBlock: gc_gusdec // base address: 0x33000 #define mmGUS_IO_RD_COMBINE_FLUSH … #define mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmGUS_IO_WR_COMBINE_FLUSH … #define mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmGUS_IO_RD_PRI_AGE_RATE … #define mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX … #define mmGUS_IO_WR_PRI_AGE_RATE … #define mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX … #define mmGUS_IO_RD_PRI_AGE_COEFF … #define mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX … #define mmGUS_IO_WR_PRI_AGE_COEFF … #define mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX … #define mmGUS_IO_RD_PRI_QUEUING … #define mmGUS_IO_RD_PRI_QUEUING_BASE_IDX … #define mmGUS_IO_WR_PRI_QUEUING … #define mmGUS_IO_WR_PRI_QUEUING_BASE_IDX … #define mmGUS_IO_RD_PRI_FIXED … #define mmGUS_IO_RD_PRI_FIXED_BASE_IDX … #define mmGUS_IO_WR_PRI_FIXED … #define mmGUS_IO_WR_PRI_FIXED_BASE_IDX … #define mmGUS_IO_RD_PRI_URGENCY_COEFF … #define mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX … #define mmGUS_IO_WR_PRI_URGENCY_COEFF … #define mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX … #define mmGUS_IO_RD_PRI_URGENCY_MODE … #define mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX … #define mmGUS_IO_WR_PRI_URGENCY_MODE … #define mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX … #define mmGUS_IO_RD_PRI_QUANT_PRI1 … #define mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmGUS_IO_RD_PRI_QUANT_PRI2 … #define mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmGUS_IO_RD_PRI_QUANT_PRI3 … #define mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmGUS_IO_RD_PRI_QUANT_PRI4 … #define mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX … #define mmGUS_IO_WR_PRI_QUANT_PRI1 … #define mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmGUS_IO_WR_PRI_QUANT_PRI2 … #define mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmGUS_IO_WR_PRI_QUANT_PRI3 … #define mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmGUS_IO_WR_PRI_QUANT_PRI4 … #define mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX … #define mmGUS_IO_RD_PRI_QUANT1_PRI1 … #define mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX … #define mmGUS_IO_RD_PRI_QUANT1_PRI2 … #define mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX … #define mmGUS_IO_RD_PRI_QUANT1_PRI3 … #define mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX … #define mmGUS_IO_RD_PRI_QUANT1_PRI4 … #define mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX … #define mmGUS_IO_WR_PRI_QUANT1_PRI1 … #define mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX … #define mmGUS_IO_WR_PRI_QUANT1_PRI2 … #define mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX … #define mmGUS_IO_WR_PRI_QUANT1_PRI3 … #define mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX … #define mmGUS_IO_WR_PRI_QUANT1_PRI4 … #define mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX … #define mmGUS_DRAM_COMBINE_FLUSH … #define mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX … #define mmGUS_DRAM_COMBINE_RD_WR_EN … #define mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX … #define mmGUS_DRAM_PRI_AGE_RATE … #define mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX … #define mmGUS_DRAM_PRI_AGE_COEFF … #define mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX … #define mmGUS_DRAM_PRI_QUEUING … #define mmGUS_DRAM_PRI_QUEUING_BASE_IDX … #define mmGUS_DRAM_PRI_FIXED … #define mmGUS_DRAM_PRI_FIXED_BASE_IDX … #define mmGUS_DRAM_PRI_URGENCY_COEFF … #define mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX … #define mmGUS_DRAM_PRI_URGENCY_MODE … #define mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT_PRI1 … #define mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT_PRI2 … #define mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT_PRI3 … #define mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT_PRI4 … #define mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT_PRI5 … #define mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT1_PRI1 … #define mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT1_PRI2 … #define mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT1_PRI3 … #define mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT1_PRI4 … #define mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX … #define mmGUS_DRAM_PRI_QUANT1_PRI5 … #define mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX … #define mmGUS_IO_GROUP_BURST … #define mmGUS_IO_GROUP_BURST_BASE_IDX … #define mmGUS_DRAM_GROUP_BURST … #define mmGUS_DRAM_GROUP_BURST_BASE_IDX … #define mmGUS_SDP_ARB_FINAL … #define mmGUS_SDP_ARB_FINAL_BASE_IDX … #define mmGUS_SDP_QOS_VC_PRIORITY … #define mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX … #define mmGUS_SDP_CREDITS … #define mmGUS_SDP_CREDITS_BASE_IDX … #define mmGUS_SDP_TAG_RESERVE0 … #define mmGUS_SDP_TAG_RESERVE0_BASE_IDX … #define mmGUS_SDP_TAG_RESERVE1 … #define mmGUS_SDP_TAG_RESERVE1_BASE_IDX … #define mmGUS_SDP_VCC_RESERVE0 … #define mmGUS_SDP_VCC_RESERVE0_BASE_IDX … #define mmGUS_SDP_VCC_RESERVE1 … #define mmGUS_SDP_VCC_RESERVE1_BASE_IDX … #define mmGUS_SDP_VCD_RESERVE0 … #define mmGUS_SDP_VCD_RESERVE0_BASE_IDX … #define mmGUS_SDP_VCD_RESERVE1 … #define mmGUS_SDP_VCD_RESERVE1_BASE_IDX … #define mmGUS_SDP_REQ_CNTL … #define mmGUS_SDP_REQ_CNTL_BASE_IDX … #define mmGUS_MISC … #define mmGUS_MISC_BASE_IDX … #define mmGUS_LATENCY_SAMPLING … #define mmGUS_LATENCY_SAMPLING_BASE_IDX … #define mmGUS_PERFCOUNTER_LO … #define mmGUS_PERFCOUNTER_LO_BASE_IDX … #define mmGUS_PERFCOUNTER_HI … #define mmGUS_PERFCOUNTER_HI_BASE_IDX … #define mmGUS_PERFCOUNTER0_CFG … #define mmGUS_PERFCOUNTER0_CFG_BASE_IDX … #define mmGUS_PERFCOUNTER1_CFG … #define mmGUS_PERFCOUNTER1_CFG_BASE_IDX … #define mmGUS_PERFCOUNTER_RSLT_CNTL … #define mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmGUS_ERR_STATUS … #define mmGUS_ERR_STATUS_BASE_IDX … #define mmGUS_MISC2 … #define mmGUS_MISC2_BASE_IDX … #define mmGUS_SDP_BACKDOOR_CMDCREDITS0 … #define mmGUS_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX … #define mmGUS_SDP_BACKDOOR_CMDCREDITS1 … #define mmGUS_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX … #define mmGUS_SDP_BACKDOOR_DATACREDITS0 … #define mmGUS_SDP_BACKDOOR_DATACREDITS0_BASE_IDX … #define mmGUS_SDP_BACKDOOR_DATACREDITS1 … #define mmGUS_SDP_BACKDOOR_DATACREDITS1_BASE_IDX … #define mmGUS_SDP_BACKDOOR_MISCCREDITS … #define mmGUS_SDP_BACKDOOR_MISCCREDITS_BASE_IDX … #define mmGUS_SDP_ENABLE … #define mmGUS_SDP_ENABLE_BASE_IDX … #define mmGUS_L1_CH0_CMD_IN … #define mmGUS_L1_CH0_CMD_IN_BASE_IDX … #define mmGUS_L1_CH0_CMD_OUT … #define mmGUS_L1_CH0_CMD_OUT_BASE_IDX … #define mmGUS_L1_CH0_DATA_IN … #define mmGUS_L1_CH0_DATA_IN_BASE_IDX … #define mmGUS_L1_CH0_DATA_OUT … #define mmGUS_L1_CH0_DATA_OUT_BASE_IDX … #define mmGUS_L1_CH1_CMD_IN … #define mmGUS_L1_CH1_CMD_IN_BASE_IDX … #define mmGUS_L1_CH1_CMD_OUT … #define mmGUS_L1_CH1_CMD_OUT_BASE_IDX … #define mmGUS_L1_CH1_DATA_IN … #define mmGUS_L1_CH1_DATA_IN_BASE_IDX … #define mmGUS_L1_CH1_DATA_OUT … #define mmGUS_L1_CH1_DATA_OUT_BASE_IDX … #define mmGUS_L1_SA0_CMD_IN … #define mmGUS_L1_SA0_CMD_IN_BASE_IDX … #define mmGUS_L1_SA0_CMD_OUT … #define mmGUS_L1_SA0_CMD_OUT_BASE_IDX … #define mmGUS_L1_SA0_DATA_IN … #define mmGUS_L1_SA0_DATA_IN_BASE_IDX … #define mmGUS_L1_SA0_DATA_OUT … #define mmGUS_L1_SA0_DATA_OUT_BASE_IDX … #define mmGUS_L1_SA0_DATA_U_IN … #define mmGUS_L1_SA0_DATA_U_IN_BASE_IDX … #define mmGUS_L1_SA0_DATA_U_OUT … #define mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX … #define mmGUS_L1_SA1_CMD_IN … #define mmGUS_L1_SA1_CMD_IN_BASE_IDX … #define mmGUS_L1_SA1_CMD_OUT … #define mmGUS_L1_SA1_CMD_OUT_BASE_IDX … #define mmGUS_L1_SA1_DATA_IN … #define mmGUS_L1_SA1_DATA_IN_BASE_IDX … #define mmGUS_L1_SA1_DATA_OUT … #define mmGUS_L1_SA1_DATA_OUT_BASE_IDX … #define mmGUS_L1_SA1_DATA_U_IN … #define mmGUS_L1_SA1_DATA_U_IN_BASE_IDX … #define mmGUS_L1_SA1_DATA_U_OUT … #define mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX … #define mmGUS_L1_SA2_CMD_IN … #define mmGUS_L1_SA2_CMD_IN_BASE_IDX … #define mmGUS_L1_SA2_CMD_OUT … #define mmGUS_L1_SA2_CMD_OUT_BASE_IDX … #define mmGUS_L1_SA2_DATA_IN … #define mmGUS_L1_SA2_DATA_IN_BASE_IDX … #define mmGUS_L1_SA2_DATA_OUT … #define mmGUS_L1_SA2_DATA_OUT_BASE_IDX … #define mmGUS_L1_SA2_DATA_U_IN … #define mmGUS_L1_SA2_DATA_U_IN_BASE_IDX … #define mmGUS_L1_SA2_DATA_U_OUT … #define mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX … #define mmGUS_L1_SA3_CMD_IN … #define mmGUS_L1_SA3_CMD_IN_BASE_IDX … #define mmGUS_L1_SA3_CMD_OUT … #define mmGUS_L1_SA3_CMD_OUT_BASE_IDX … #define mmGUS_L1_SA3_DATA_IN … #define mmGUS_L1_SA3_DATA_IN_BASE_IDX … #define mmGUS_L1_SA3_DATA_OUT … #define mmGUS_L1_SA3_DATA_OUT_BASE_IDX … #define mmGUS_L1_SA3_DATA_U_IN … #define mmGUS_L1_SA3_DATA_U_IN_BASE_IDX … #define mmGUS_L1_SA3_DATA_U_OUT … #define mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX … #define mmGUS_MISC3 … #define mmGUS_MISC3_BASE_IDX … #define mmGUS_WRRSP_FIFO_CNTL … #define mmGUS_WRRSP_FIFO_CNTL_BASE_IDX … // addressBlock: gc_gl1dec // base address: 0x33400 #define mmGL1_ARB_CTRL … #define mmGL1_ARB_CTRL_BASE_IDX … #define mmGL1_DRAM_BURST_MASK … #define mmGL1_DRAM_BURST_MASK_BASE_IDX … #define mmGL1_ARB_STATUS … #define mmGL1_ARB_STATUS_BASE_IDX … #define mmGL1_DRAM_BURST_CTRL … #define mmGL1_DRAM_BURST_CTRL_BASE_IDX … #define mmGL1_PIPE_STEER … #define mmGL1_PIPE_STEER_BASE_IDX … #define mmGL1C_CTRL … #define mmGL1C_CTRL_BASE_IDX … #define mmGL1C_STATUS … #define mmGL1C_STATUS_BASE_IDX … // addressBlock: gc_chdec // base address: 0x33600 #define mmCH_ARB_CTRL … #define mmCH_ARB_CTRL_BASE_IDX … #define mmCH_DRAM_BURST_MASK … #define mmCH_DRAM_BURST_MASK_BASE_IDX … #define mmCH_ARB_STATUS … #define mmCH_ARB_STATUS_BASE_IDX … #define mmCH_DRAM_BURST_CTRL … #define mmCH_DRAM_BURST_CTRL_BASE_IDX … #define mmCH_PIPE_STEER … #define mmCH_PIPE_STEER_BASE_IDX … #define mmCH_VC5_ENABLE … #define mmCH_VC5_ENABLE_BASE_IDX … #define mmCHC_CTRL … #define mmCHC_CTRL_BASE_IDX … #define mmCHC_STATUS … #define mmCHC_STATUS_BASE_IDX … #define mmCHCG_CTRL … #define mmCHCG_CTRL_BASE_IDX … #define mmCHCG_STATUS … #define mmCHCG_STATUS_BASE_IDX … // addressBlock: gc_gl2dec // base address: 0x33800 #define mmGL2C_CTRL … #define mmGL2C_CTRL_BASE_IDX … #define mmGL2C_CTRL2 … #define mmGL2C_CTRL2_BASE_IDX … #define mmGL2C_STATUS … #define mmGL2C_STATUS_BASE_IDX … #define mmGL2C_ADDR_MATCH_MASK … #define mmGL2C_ADDR_MATCH_MASK_BASE_IDX … #define mmGL2C_ADDR_MATCH_SIZE … #define mmGL2C_ADDR_MATCH_SIZE_BASE_IDX … #define mmGL2C_WBINVL2 … #define mmGL2C_WBINVL2_BASE_IDX … #define mmGL2C_SOFT_RESET … #define mmGL2C_SOFT_RESET_BASE_IDX … #define mmGL2C_CM_CTRL0 … #define mmGL2C_CM_CTRL0_BASE_IDX … #define mmGL2C_CM_CTRL1 … #define mmGL2C_CM_CTRL1_BASE_IDX … #define mmGL2C_CM_STALL … #define mmGL2C_CM_STALL_BASE_IDX … #define mmGL2C_MDC_PF_FLAG_CTRL … #define mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX … #define mmGL2C_CM_CTRL2 … #define mmGL2C_CM_CTRL2_BASE_IDX … #define mmGL2C_CTRL3 … #define mmGL2C_CTRL3_BASE_IDX … #define mmGL2C_LB_CTR_CTRL … #define mmGL2C_LB_CTR_CTRL_BASE_IDX … #define mmGL2C_LB_DATA0 … #define mmGL2C_LB_DATA0_BASE_IDX … #define mmGL2C_LB_DATA1 … #define mmGL2C_LB_DATA1_BASE_IDX … #define mmGL2C_LB_DATA2 … #define mmGL2C_LB_DATA2_BASE_IDX … #define mmGL2C_LB_DATA3 … #define mmGL2C_LB_DATA3_BASE_IDX … #define mmGL2C_LB_CTR_SEL0 … #define mmGL2C_LB_CTR_SEL0_BASE_IDX … #define mmGL2C_LB_CTR_SEL1 … #define mmGL2C_LB_CTR_SEL1_BASE_IDX … #define mmGL2A_ADDR_MATCH_CTRL … #define mmGL2A_ADDR_MATCH_CTRL_BASE_IDX … #define mmGL2A_ADDR_MATCH_MASK … #define mmGL2A_ADDR_MATCH_MASK_BASE_IDX … #define mmGL2A_ADDR_MATCH_SIZE … #define mmGL2A_ADDR_MATCH_SIZE_BASE_IDX … #define mmGL2A_PRIORITY_CTRL … #define mmGL2A_PRIORITY_CTRL_BASE_IDX … #define mmGL2A_CTRL … #define mmGL2A_CTRL_BASE_IDX … #define mmGL2_PIPE_STEER_0 … #define mmGL2_PIPE_STEER_0_BASE_IDX … #define mmGL2_PIPE_STEER_1 … #define mmGL2_PIPE_STEER_1_BASE_IDX … // addressBlock: gc_perfddec // base address: 0x34000 #define mmCPG_PERFCOUNTER1_LO … #define mmCPG_PERFCOUNTER1_LO_BASE_IDX … #define mmCPG_PERFCOUNTER1_HI … #define mmCPG_PERFCOUNTER1_HI_BASE_IDX … #define mmCPG_PERFCOUNTER0_LO … #define mmCPG_PERFCOUNTER0_LO_BASE_IDX … #define mmCPG_PERFCOUNTER0_HI … #define mmCPG_PERFCOUNTER0_HI_BASE_IDX … #define mmCPC_PERFCOUNTER1_LO … #define mmCPC_PERFCOUNTER1_LO_BASE_IDX … #define mmCPC_PERFCOUNTER1_HI … #define mmCPC_PERFCOUNTER1_HI_BASE_IDX … #define mmCPC_PERFCOUNTER0_LO … #define mmCPC_PERFCOUNTER0_LO_BASE_IDX … #define mmCPC_PERFCOUNTER0_HI … #define mmCPC_PERFCOUNTER0_HI_BASE_IDX … #define mmCPF_PERFCOUNTER1_LO … #define mmCPF_PERFCOUNTER1_LO_BASE_IDX … #define mmCPF_PERFCOUNTER1_HI … #define mmCPF_PERFCOUNTER1_HI_BASE_IDX … #define mmCPF_PERFCOUNTER0_LO … #define mmCPF_PERFCOUNTER0_LO_BASE_IDX … #define mmCPF_PERFCOUNTER0_HI … #define mmCPF_PERFCOUNTER0_HI_BASE_IDX … #define mmCPF_LATENCY_STATS_DATA … #define mmCPF_LATENCY_STATS_DATA_BASE_IDX … #define mmCPG_LATENCY_STATS_DATA … #define mmCPG_LATENCY_STATS_DATA_BASE_IDX … #define mmCPC_LATENCY_STATS_DATA … #define mmCPC_LATENCY_STATS_DATA_BASE_IDX … #define mmGRBM_PERFCOUNTER0_LO … #define mmGRBM_PERFCOUNTER0_LO_BASE_IDX … #define mmGRBM_PERFCOUNTER0_HI … #define mmGRBM_PERFCOUNTER0_HI_BASE_IDX … #define mmGRBM_PERFCOUNTER1_LO … #define mmGRBM_PERFCOUNTER1_LO_BASE_IDX … #define mmGRBM_PERFCOUNTER1_HI … #define mmGRBM_PERFCOUNTER1_HI_BASE_IDX … #define mmGRBM_SE0_PERFCOUNTER_LO … #define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX … #define mmGRBM_SE0_PERFCOUNTER_HI … #define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX … #define mmGRBM_SE1_PERFCOUNTER_LO … #define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX … #define mmGRBM_SE1_PERFCOUNTER_HI … #define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX … #define mmGRBM_SE2_PERFCOUNTER_LO … #define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX … #define mmGRBM_SE2_PERFCOUNTER_HI … #define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX … #define mmGRBM_SE3_PERFCOUNTER_LO … #define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX … #define mmGRBM_SE3_PERFCOUNTER_HI … #define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX … #define mmGE_PERFCOUNTER0_LO … #define mmGE_PERFCOUNTER0_LO_BASE_IDX … #define mmGE_PERFCOUNTER0_HI … #define mmGE_PERFCOUNTER0_HI_BASE_IDX … #define mmGE_PERFCOUNTER1_LO … #define mmGE_PERFCOUNTER1_LO_BASE_IDX … #define mmGE_PERFCOUNTER1_HI … #define mmGE_PERFCOUNTER1_HI_BASE_IDX … #define mmGE_PERFCOUNTER2_LO … #define mmGE_PERFCOUNTER2_LO_BASE_IDX … #define mmGE_PERFCOUNTER2_HI … #define mmGE_PERFCOUNTER2_HI_BASE_IDX … #define mmGE_PERFCOUNTER3_LO … #define mmGE_PERFCOUNTER3_LO_BASE_IDX … #define mmGE_PERFCOUNTER3_HI … #define mmGE_PERFCOUNTER3_HI_BASE_IDX … #define mmGE_PERFCOUNTER4_LO … #define mmGE_PERFCOUNTER4_LO_BASE_IDX … #define mmGE_PERFCOUNTER4_HI … #define mmGE_PERFCOUNTER4_HI_BASE_IDX … #define mmGE_PERFCOUNTER5_LO … #define mmGE_PERFCOUNTER5_LO_BASE_IDX … #define mmGE_PERFCOUNTER5_HI … #define mmGE_PERFCOUNTER5_HI_BASE_IDX … #define mmGE_PERFCOUNTER6_LO … #define mmGE_PERFCOUNTER6_LO_BASE_IDX … #define mmGE_PERFCOUNTER6_HI … #define mmGE_PERFCOUNTER6_HI_BASE_IDX … #define mmGE_PERFCOUNTER7_LO … #define mmGE_PERFCOUNTER7_LO_BASE_IDX … #define mmGE_PERFCOUNTER7_HI … #define mmGE_PERFCOUNTER7_HI_BASE_IDX … #define mmGE_PERFCOUNTER8_LO … #define mmGE_PERFCOUNTER8_LO_BASE_IDX … #define mmGE_PERFCOUNTER8_HI … #define mmGE_PERFCOUNTER8_HI_BASE_IDX … #define mmGE_PERFCOUNTER9_LO … #define mmGE_PERFCOUNTER9_LO_BASE_IDX … #define mmGE_PERFCOUNTER9_HI … #define mmGE_PERFCOUNTER9_HI_BASE_IDX … #define mmGE_PERFCOUNTER10_LO … #define mmGE_PERFCOUNTER10_LO_BASE_IDX … #define mmGE_PERFCOUNTER10_HI … #define mmGE_PERFCOUNTER10_HI_BASE_IDX … #define mmGE_PERFCOUNTER11_LO … #define mmGE_PERFCOUNTER11_LO_BASE_IDX … #define mmGE_PERFCOUNTER11_HI … #define mmGE_PERFCOUNTER11_HI_BASE_IDX … #define mmPA_SU_PERFCOUNTER0_LO … #define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX … #define mmPA_SU_PERFCOUNTER0_HI … #define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX … #define mmPA_SU_PERFCOUNTER1_LO … #define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX … #define mmPA_SU_PERFCOUNTER1_HI … #define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX … #define mmPA_SU_PERFCOUNTER2_LO … #define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX … #define mmPA_SU_PERFCOUNTER2_HI … #define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX … #define mmPA_SU_PERFCOUNTER3_LO … #define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX … #define mmPA_SU_PERFCOUNTER3_HI … #define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX … #define mmPA_SC_PERFCOUNTER0_LO … #define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX … #define mmPA_SC_PERFCOUNTER0_HI … #define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX … #define mmPA_SC_PERFCOUNTER1_LO … #define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX … #define mmPA_SC_PERFCOUNTER1_HI … #define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX … #define mmPA_SC_PERFCOUNTER2_LO … #define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX … #define mmPA_SC_PERFCOUNTER2_HI … #define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX … #define mmPA_SC_PERFCOUNTER3_LO … #define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX … #define mmPA_SC_PERFCOUNTER3_HI … #define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX … #define mmPA_SC_PERFCOUNTER4_LO … #define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX … #define mmPA_SC_PERFCOUNTER4_HI … #define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX … #define mmPA_SC_PERFCOUNTER5_LO … #define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX … #define mmPA_SC_PERFCOUNTER5_HI … #define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX … #define mmPA_SC_PERFCOUNTER6_LO … #define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX … #define mmPA_SC_PERFCOUNTER6_HI … #define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX … #define mmPA_SC_PERFCOUNTER7_LO … #define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX … #define mmPA_SC_PERFCOUNTER7_HI … #define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX … #define mmSPI_PERFCOUNTER0_HI … #define mmSPI_PERFCOUNTER0_HI_BASE_IDX … #define mmSPI_PERFCOUNTER0_LO … #define mmSPI_PERFCOUNTER0_LO_BASE_IDX … #define mmSPI_PERFCOUNTER1_HI … #define mmSPI_PERFCOUNTER1_HI_BASE_IDX … #define mmSPI_PERFCOUNTER1_LO … #define mmSPI_PERFCOUNTER1_LO_BASE_IDX … #define mmSPI_PERFCOUNTER2_HI … #define mmSPI_PERFCOUNTER2_HI_BASE_IDX … #define mmSPI_PERFCOUNTER2_LO … #define mmSPI_PERFCOUNTER2_LO_BASE_IDX … #define mmSPI_PERFCOUNTER3_HI … #define mmSPI_PERFCOUNTER3_HI_BASE_IDX … #define mmSPI_PERFCOUNTER3_LO … #define mmSPI_PERFCOUNTER3_LO_BASE_IDX … #define mmSPI_PERFCOUNTER4_HI … #define mmSPI_PERFCOUNTER4_HI_BASE_IDX … #define mmSPI_PERFCOUNTER4_LO … #define mmSPI_PERFCOUNTER4_LO_BASE_IDX … #define mmSPI_PERFCOUNTER5_HI … #define mmSPI_PERFCOUNTER5_HI_BASE_IDX … #define mmSPI_PERFCOUNTER5_LO … #define mmSPI_PERFCOUNTER5_LO_BASE_IDX … #define mmSQ_PERFCOUNTER0_LO … #define mmSQ_PERFCOUNTER0_LO_BASE_IDX … #define mmSQ_PERFCOUNTER0_HI … #define mmSQ_PERFCOUNTER0_HI_BASE_IDX … #define mmSQ_PERFCOUNTER1_LO … #define mmSQ_PERFCOUNTER1_LO_BASE_IDX … #define mmSQ_PERFCOUNTER1_HI … #define mmSQ_PERFCOUNTER1_HI_BASE_IDX … #define mmSQ_PERFCOUNTER2_LO … #define mmSQ_PERFCOUNTER2_LO_BASE_IDX … #define mmSQ_PERFCOUNTER2_HI … #define mmSQ_PERFCOUNTER2_HI_BASE_IDX … #define mmSQ_PERFCOUNTER3_LO … #define mmSQ_PERFCOUNTER3_LO_BASE_IDX … #define mmSQ_PERFCOUNTER3_HI … #define mmSQ_PERFCOUNTER3_HI_BASE_IDX … #define mmSQ_PERFCOUNTER4_LO … #define mmSQ_PERFCOUNTER4_LO_BASE_IDX … #define mmSQ_PERFCOUNTER4_HI … #define mmSQ_PERFCOUNTER4_HI_BASE_IDX … #define mmSQ_PERFCOUNTER5_LO … #define mmSQ_PERFCOUNTER5_LO_BASE_IDX … #define mmSQ_PERFCOUNTER5_HI … #define mmSQ_PERFCOUNTER5_HI_BASE_IDX … #define mmSQ_PERFCOUNTER6_LO … #define mmSQ_PERFCOUNTER6_LO_BASE_IDX … #define mmSQ_PERFCOUNTER6_HI … #define mmSQ_PERFCOUNTER6_HI_BASE_IDX … #define mmSQ_PERFCOUNTER7_LO … #define mmSQ_PERFCOUNTER7_LO_BASE_IDX … #define mmSQ_PERFCOUNTER7_HI … #define mmSQ_PERFCOUNTER7_HI_BASE_IDX … #define mmSQ_PERFCOUNTER8_LO … #define mmSQ_PERFCOUNTER8_LO_BASE_IDX … #define mmSQ_PERFCOUNTER8_HI … #define mmSQ_PERFCOUNTER8_HI_BASE_IDX … #define mmSQ_PERFCOUNTER9_LO … #define mmSQ_PERFCOUNTER9_LO_BASE_IDX … #define mmSQ_PERFCOUNTER9_HI … #define mmSQ_PERFCOUNTER9_HI_BASE_IDX … #define mmSQ_PERFCOUNTER10_LO … #define mmSQ_PERFCOUNTER10_LO_BASE_IDX … #define mmSQ_PERFCOUNTER10_HI … #define mmSQ_PERFCOUNTER10_HI_BASE_IDX … #define mmSQ_PERFCOUNTER11_LO … #define mmSQ_PERFCOUNTER11_LO_BASE_IDX … #define mmSQ_PERFCOUNTER11_HI … #define mmSQ_PERFCOUNTER11_HI_BASE_IDX … #define mmSQ_PERFCOUNTER12_LO … #define mmSQ_PERFCOUNTER12_LO_BASE_IDX … #define mmSQ_PERFCOUNTER12_HI … #define mmSQ_PERFCOUNTER12_HI_BASE_IDX … #define mmSQ_PERFCOUNTER13_LO … #define mmSQ_PERFCOUNTER13_LO_BASE_IDX … #define mmSQ_PERFCOUNTER13_HI … #define mmSQ_PERFCOUNTER13_HI_BASE_IDX … #define mmSQ_PERFCOUNTER14_LO … #define mmSQ_PERFCOUNTER14_LO_BASE_IDX … #define mmSQ_PERFCOUNTER14_HI … #define mmSQ_PERFCOUNTER14_HI_BASE_IDX … #define mmSQ_PERFCOUNTER15_LO … #define mmSQ_PERFCOUNTER15_LO_BASE_IDX … #define mmSQ_PERFCOUNTER15_HI … #define mmSQ_PERFCOUNTER15_HI_BASE_IDX … #define mmSX_PERFCOUNTER0_LO … #define mmSX_PERFCOUNTER0_LO_BASE_IDX … #define mmSX_PERFCOUNTER0_HI … #define mmSX_PERFCOUNTER0_HI_BASE_IDX … #define mmSX_PERFCOUNTER1_LO … #define mmSX_PERFCOUNTER1_LO_BASE_IDX … #define mmSX_PERFCOUNTER1_HI … #define mmSX_PERFCOUNTER1_HI_BASE_IDX … #define mmSX_PERFCOUNTER2_LO … #define mmSX_PERFCOUNTER2_LO_BASE_IDX … #define mmSX_PERFCOUNTER2_HI … #define mmSX_PERFCOUNTER2_HI_BASE_IDX … #define mmSX_PERFCOUNTER3_LO … #define mmSX_PERFCOUNTER3_LO_BASE_IDX … #define mmSX_PERFCOUNTER3_HI … #define mmSX_PERFCOUNTER3_HI_BASE_IDX … #define mmGCEA_PERFCOUNTER2_LO … #define mmGCEA_PERFCOUNTER2_LO_BASE_IDX … #define mmGCEA_PERFCOUNTER2_HI … #define mmGCEA_PERFCOUNTER2_HI_BASE_IDX … #define mmGDS_PERFCOUNTER0_LO … #define mmGDS_PERFCOUNTER0_LO_BASE_IDX … #define mmGDS_PERFCOUNTER0_HI … #define mmGDS_PERFCOUNTER0_HI_BASE_IDX … #define mmGDS_PERFCOUNTER1_LO … #define mmGDS_PERFCOUNTER1_LO_BASE_IDX … #define mmGDS_PERFCOUNTER1_HI … #define mmGDS_PERFCOUNTER1_HI_BASE_IDX … #define mmGDS_PERFCOUNTER2_LO … #define mmGDS_PERFCOUNTER2_LO_BASE_IDX … #define mmGDS_PERFCOUNTER2_HI … #define mmGDS_PERFCOUNTER2_HI_BASE_IDX … #define mmGDS_PERFCOUNTER3_LO … #define mmGDS_PERFCOUNTER3_LO_BASE_IDX … #define mmGDS_PERFCOUNTER3_HI … #define mmGDS_PERFCOUNTER3_HI_BASE_IDX … #define mmTA_PERFCOUNTER0_LO … #define mmTA_PERFCOUNTER0_LO_BASE_IDX … #define mmTA_PERFCOUNTER0_HI … #define mmTA_PERFCOUNTER0_HI_BASE_IDX … #define mmTA_PERFCOUNTER1_LO … #define mmTA_PERFCOUNTER1_LO_BASE_IDX … #define mmTA_PERFCOUNTER1_HI … #define mmTA_PERFCOUNTER1_HI_BASE_IDX … #define mmTD_PERFCOUNTER0_LO … #define mmTD_PERFCOUNTER0_LO_BASE_IDX … #define mmTD_PERFCOUNTER0_HI … #define mmTD_PERFCOUNTER0_HI_BASE_IDX … #define mmTD_PERFCOUNTER1_LO … #define mmTD_PERFCOUNTER1_LO_BASE_IDX … #define mmTD_PERFCOUNTER1_HI … #define mmTD_PERFCOUNTER1_HI_BASE_IDX … #define mmTCP_PERFCOUNTER0_LO … #define mmTCP_PERFCOUNTER0_LO_BASE_IDX … #define mmTCP_PERFCOUNTER0_HI … #define mmTCP_PERFCOUNTER0_HI_BASE_IDX … #define mmTCP_PERFCOUNTER1_LO … #define mmTCP_PERFCOUNTER1_LO_BASE_IDX … #define mmTCP_PERFCOUNTER1_HI … #define mmTCP_PERFCOUNTER1_HI_BASE_IDX … #define mmTCP_PERFCOUNTER2_LO … #define mmTCP_PERFCOUNTER2_LO_BASE_IDX … #define mmTCP_PERFCOUNTER2_HI … #define mmTCP_PERFCOUNTER2_HI_BASE_IDX … #define mmTCP_PERFCOUNTER3_LO … #define mmTCP_PERFCOUNTER3_LO_BASE_IDX … #define mmTCP_PERFCOUNTER3_HI … #define mmTCP_PERFCOUNTER3_HI_BASE_IDX … #define mmGL2C_PERFCOUNTER0_LO … #define mmGL2C_PERFCOUNTER0_LO_BASE_IDX … #define mmGL2C_PERFCOUNTER0_HI … #define mmGL2C_PERFCOUNTER0_HI_BASE_IDX … #define mmGL2C_PERFCOUNTER1_LO … #define mmGL2C_PERFCOUNTER1_LO_BASE_IDX … #define mmGL2C_PERFCOUNTER1_HI … #define mmGL2C_PERFCOUNTER1_HI_BASE_IDX … #define mmGL2C_PERFCOUNTER2_LO … #define mmGL2C_PERFCOUNTER2_LO_BASE_IDX … #define mmGL2C_PERFCOUNTER2_HI … #define mmGL2C_PERFCOUNTER2_HI_BASE_IDX … #define mmGL2C_PERFCOUNTER3_LO … #define mmGL2C_PERFCOUNTER3_LO_BASE_IDX … #define mmGL2C_PERFCOUNTER3_HI … #define mmGL2C_PERFCOUNTER3_HI_BASE_IDX … #define mmGL2A_PERFCOUNTER0_LO … #define mmGL2A_PERFCOUNTER0_LO_BASE_IDX … #define mmGL2A_PERFCOUNTER0_HI … #define mmGL2A_PERFCOUNTER0_HI_BASE_IDX … #define mmGL2A_PERFCOUNTER1_LO … #define mmGL2A_PERFCOUNTER1_LO_BASE_IDX … #define mmGL2A_PERFCOUNTER1_HI … #define mmGL2A_PERFCOUNTER1_HI_BASE_IDX … #define mmGL2A_PERFCOUNTER2_LO … #define mmGL2A_PERFCOUNTER2_LO_BASE_IDX … #define mmGL2A_PERFCOUNTER2_HI … #define mmGL2A_PERFCOUNTER2_HI_BASE_IDX … #define mmGL2A_PERFCOUNTER3_LO … #define mmGL2A_PERFCOUNTER3_LO_BASE_IDX … #define mmGL2A_PERFCOUNTER3_HI … #define mmGL2A_PERFCOUNTER3_HI_BASE_IDX … #define mmGL1C_PERFCOUNTER0_LO … #define mmGL1C_PERFCOUNTER0_LO_BASE_IDX … #define mmGL1C_PERFCOUNTER0_HI … #define mmGL1C_PERFCOUNTER0_HI_BASE_IDX … #define mmGL1C_PERFCOUNTER1_LO … #define mmGL1C_PERFCOUNTER1_LO_BASE_IDX … #define mmGL1C_PERFCOUNTER1_HI … #define mmGL1C_PERFCOUNTER1_HI_BASE_IDX … #define mmGL1C_PERFCOUNTER2_LO … #define mmGL1C_PERFCOUNTER2_LO_BASE_IDX … #define mmGL1C_PERFCOUNTER2_HI … #define mmGL1C_PERFCOUNTER2_HI_BASE_IDX … #define mmGL1C_PERFCOUNTER3_LO … #define mmGL1C_PERFCOUNTER3_LO_BASE_IDX … #define mmGL1C_PERFCOUNTER3_HI … #define mmGL1C_PERFCOUNTER3_HI_BASE_IDX … #define mmCHC_PERFCOUNTER0_LO … #define mmCHC_PERFCOUNTER0_LO_BASE_IDX … #define mmCHC_PERFCOUNTER0_HI … #define mmCHC_PERFCOUNTER0_HI_BASE_IDX … #define mmCHC_PERFCOUNTER1_LO … #define mmCHC_PERFCOUNTER1_LO_BASE_IDX … #define mmCHC_PERFCOUNTER1_HI … #define mmCHC_PERFCOUNTER1_HI_BASE_IDX … #define mmCHC_PERFCOUNTER2_LO … #define mmCHC_PERFCOUNTER2_LO_BASE_IDX … #define mmCHC_PERFCOUNTER2_HI … #define mmCHC_PERFCOUNTER2_HI_BASE_IDX … #define mmCHC_PERFCOUNTER3_LO … #define mmCHC_PERFCOUNTER3_LO_BASE_IDX … #define mmCHC_PERFCOUNTER3_HI … #define mmCHC_PERFCOUNTER3_HI_BASE_IDX … #define mmCHCG_PERFCOUNTER0_LO … #define mmCHCG_PERFCOUNTER0_LO_BASE_IDX … #define mmCHCG_PERFCOUNTER0_HI … #define mmCHCG_PERFCOUNTER0_HI_BASE_IDX … #define mmCHCG_PERFCOUNTER1_LO … #define mmCHCG_PERFCOUNTER1_LO_BASE_IDX … #define mmCHCG_PERFCOUNTER1_HI … #define mmCHCG_PERFCOUNTER1_HI_BASE_IDX … #define mmCHCG_PERFCOUNTER2_LO … #define mmCHCG_PERFCOUNTER2_LO_BASE_IDX … #define mmCHCG_PERFCOUNTER2_HI … #define mmCHCG_PERFCOUNTER2_HI_BASE_IDX … #define mmCHCG_PERFCOUNTER3_LO … #define mmCHCG_PERFCOUNTER3_LO_BASE_IDX … #define mmCHCG_PERFCOUNTER3_HI … #define mmCHCG_PERFCOUNTER3_HI_BASE_IDX … #define mmCB_PERFCOUNTER0_LO … #define mmCB_PERFCOUNTER0_LO_BASE_IDX … #define mmCB_PERFCOUNTER0_HI … #define mmCB_PERFCOUNTER0_HI_BASE_IDX … #define mmCB_PERFCOUNTER1_LO … #define mmCB_PERFCOUNTER1_LO_BASE_IDX … #define mmCB_PERFCOUNTER1_HI … #define mmCB_PERFCOUNTER1_HI_BASE_IDX … #define mmCB_PERFCOUNTER2_LO … #define mmCB_PERFCOUNTER2_LO_BASE_IDX … #define mmCB_PERFCOUNTER2_HI … #define mmCB_PERFCOUNTER2_HI_BASE_IDX … #define mmCB_PERFCOUNTER3_LO … #define mmCB_PERFCOUNTER3_LO_BASE_IDX … #define mmCB_PERFCOUNTER3_HI … #define mmCB_PERFCOUNTER3_HI_BASE_IDX … #define mmDB_PERFCOUNTER0_LO … #define mmDB_PERFCOUNTER0_LO_BASE_IDX … #define mmDB_PERFCOUNTER0_HI … #define mmDB_PERFCOUNTER0_HI_BASE_IDX … #define mmDB_PERFCOUNTER1_LO … #define mmDB_PERFCOUNTER1_LO_BASE_IDX … #define mmDB_PERFCOUNTER1_HI … #define mmDB_PERFCOUNTER1_HI_BASE_IDX … #define mmDB_PERFCOUNTER2_LO … #define mmDB_PERFCOUNTER2_LO_BASE_IDX … #define mmDB_PERFCOUNTER2_HI … #define mmDB_PERFCOUNTER2_HI_BASE_IDX … #define mmDB_PERFCOUNTER3_LO … #define mmDB_PERFCOUNTER3_LO_BASE_IDX … #define mmDB_PERFCOUNTER3_HI … #define mmDB_PERFCOUNTER3_HI_BASE_IDX … #define mmRLC_PERFCOUNTER0_LO … #define mmRLC_PERFCOUNTER0_LO_BASE_IDX … #define mmRLC_PERFCOUNTER0_HI … #define mmRLC_PERFCOUNTER0_HI_BASE_IDX … #define mmRLC_PERFCOUNTER1_LO … #define mmRLC_PERFCOUNTER1_LO_BASE_IDX … #define mmRLC_PERFCOUNTER1_HI … #define mmRLC_PERFCOUNTER1_HI_BASE_IDX … #define mmRMI_PERFCOUNTER0_LO … #define mmRMI_PERFCOUNTER0_LO_BASE_IDX … #define mmRMI_PERFCOUNTER0_HI … #define mmRMI_PERFCOUNTER0_HI_BASE_IDX … #define mmRMI_PERFCOUNTER1_LO … #define mmRMI_PERFCOUNTER1_LO_BASE_IDX … #define mmRMI_PERFCOUNTER1_HI … #define mmRMI_PERFCOUNTER1_HI_BASE_IDX … #define mmRMI_PERFCOUNTER2_LO … #define mmRMI_PERFCOUNTER2_LO_BASE_IDX … #define mmRMI_PERFCOUNTER2_HI … #define mmRMI_PERFCOUNTER2_HI_BASE_IDX … #define mmRMI_PERFCOUNTER3_LO … #define mmRMI_PERFCOUNTER3_LO_BASE_IDX … #define mmRMI_PERFCOUNTER3_HI … #define mmRMI_PERFCOUNTER3_HI_BASE_IDX … #define mmUTCL1_PERFCOUNTER0_LO … #define mmUTCL1_PERFCOUNTER0_LO_BASE_IDX … #define mmUTCL1_PERFCOUNTER0_HI … #define mmUTCL1_PERFCOUNTER0_HI_BASE_IDX … #define mmUTCL1_PERFCOUNTER1_LO … #define mmUTCL1_PERFCOUNTER1_LO_BASE_IDX … #define mmUTCL1_PERFCOUNTER1_HI … #define mmUTCL1_PERFCOUNTER1_HI_BASE_IDX … #define mmGCR_PERFCOUNTER0_LO … #define mmGCR_PERFCOUNTER0_LO_BASE_IDX … #define mmGCR_PERFCOUNTER0_HI … #define mmGCR_PERFCOUNTER0_HI_BASE_IDX … #define mmGCR_PERFCOUNTER1_LO … #define mmGCR_PERFCOUNTER1_LO_BASE_IDX … #define mmGCR_PERFCOUNTER1_HI … #define mmGCR_PERFCOUNTER1_HI_BASE_IDX … #define mmPA_PH_PERFCOUNTER0_LO … #define mmPA_PH_PERFCOUNTER0_LO_BASE_IDX … #define mmPA_PH_PERFCOUNTER0_HI … #define mmPA_PH_PERFCOUNTER0_HI_BASE_IDX … #define mmPA_PH_PERFCOUNTER1_LO … #define mmPA_PH_PERFCOUNTER1_LO_BASE_IDX … #define mmPA_PH_PERFCOUNTER1_HI … #define mmPA_PH_PERFCOUNTER1_HI_BASE_IDX … #define mmPA_PH_PERFCOUNTER2_LO … #define mmPA_PH_PERFCOUNTER2_LO_BASE_IDX … #define mmPA_PH_PERFCOUNTER2_HI … #define mmPA_PH_PERFCOUNTER2_HI_BASE_IDX … #define mmPA_PH_PERFCOUNTER3_LO … #define mmPA_PH_PERFCOUNTER3_LO_BASE_IDX … #define mmPA_PH_PERFCOUNTER3_HI … #define mmPA_PH_PERFCOUNTER3_HI_BASE_IDX … #define mmPA_PH_PERFCOUNTER4_LO … #define mmPA_PH_PERFCOUNTER4_LO_BASE_IDX … #define mmPA_PH_PERFCOUNTER4_HI … #define mmPA_PH_PERFCOUNTER4_HI_BASE_IDX … #define mmPA_PH_PERFCOUNTER5_LO … #define mmPA_PH_PERFCOUNTER5_LO_BASE_IDX … #define mmPA_PH_PERFCOUNTER5_HI … #define mmPA_PH_PERFCOUNTER5_HI_BASE_IDX … #define mmPA_PH_PERFCOUNTER6_LO … #define mmPA_PH_PERFCOUNTER6_LO_BASE_IDX … #define mmPA_PH_PERFCOUNTER6_HI … #define mmPA_PH_PERFCOUNTER6_HI_BASE_IDX … #define mmPA_PH_PERFCOUNTER7_LO … #define mmPA_PH_PERFCOUNTER7_LO_BASE_IDX … #define mmPA_PH_PERFCOUNTER7_HI … #define mmPA_PH_PERFCOUNTER7_HI_BASE_IDX … #define mmGL1A_PERFCOUNTER0_LO … #define mmGL1A_PERFCOUNTER0_LO_BASE_IDX … #define mmGL1A_PERFCOUNTER0_HI … #define mmGL1A_PERFCOUNTER0_HI_BASE_IDX … #define mmGL1A_PERFCOUNTER1_LO … #define mmGL1A_PERFCOUNTER1_LO_BASE_IDX … #define mmGL1A_PERFCOUNTER1_HI … #define mmGL1A_PERFCOUNTER1_HI_BASE_IDX … #define mmGL1A_PERFCOUNTER2_LO … #define mmGL1A_PERFCOUNTER2_LO_BASE_IDX … #define mmGL1A_PERFCOUNTER2_HI … #define mmGL1A_PERFCOUNTER2_HI_BASE_IDX … #define mmGL1A_PERFCOUNTER3_LO … #define mmGL1A_PERFCOUNTER3_LO_BASE_IDX … #define mmGL1A_PERFCOUNTER3_HI … #define mmGL1A_PERFCOUNTER3_HI_BASE_IDX … #define mmCHA_PERFCOUNTER0_LO … #define mmCHA_PERFCOUNTER0_LO_BASE_IDX … #define mmCHA_PERFCOUNTER0_HI … #define mmCHA_PERFCOUNTER0_HI_BASE_IDX … #define mmCHA_PERFCOUNTER1_LO … #define mmCHA_PERFCOUNTER1_LO_BASE_IDX … #define mmCHA_PERFCOUNTER1_HI … #define mmCHA_PERFCOUNTER1_HI_BASE_IDX … #define mmCHA_PERFCOUNTER2_LO … #define mmCHA_PERFCOUNTER2_LO_BASE_IDX … #define mmCHA_PERFCOUNTER2_HI … #define mmCHA_PERFCOUNTER2_HI_BASE_IDX … #define mmCHA_PERFCOUNTER3_LO … #define mmCHA_PERFCOUNTER3_LO_BASE_IDX … #define mmCHA_PERFCOUNTER3_HI … #define mmCHA_PERFCOUNTER3_HI_BASE_IDX … #define mmGUS_PERFCOUNTER2_LO … #define mmGUS_PERFCOUNTER2_LO_BASE_IDX … #define mmGUS_PERFCOUNTER2_HI … #define mmGUS_PERFCOUNTER2_HI_BASE_IDX … // addressBlock: gc_gcatcl2pfcntrdec // base address: 0x35380 #define mmGC_ATC_L2_PERFCOUNTER_LO … #define mmGC_ATC_L2_PERFCOUNTER_LO_BASE_IDX … #define mmGC_ATC_L2_PERFCOUNTER_HI … #define mmGC_ATC_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: gc_gcvml2prdec // base address: 0x353a0 #define mmGCMC_VM_L2_PERFCOUNTER_LO … #define mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER_HI … #define mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: gc_gcvml2perfddec // base address: 0x353e0 #define mmGCVML2_PERFCOUNTER2_0_LO … #define mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX … #define mmGCVML2_PERFCOUNTER2_1_LO … #define mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX … #define mmGCVML2_PERFCOUNTER2_0_HI … #define mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX … #define mmGCVML2_PERFCOUNTER2_1_HI … #define mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX … // addressBlock: gc_gcatcl2perfddec // base address: 0x353f0 #define mmGC_ATC_L2_PERFCOUNTER2_LO … #define mmGC_ATC_L2_PERFCOUNTER2_LO_BASE_IDX … #define mmGC_ATC_L2_PERFCOUNTER2_HI … #define mmGC_ATC_L2_PERFCOUNTER2_HI_BASE_IDX … // addressBlock: gc_perfsdec // base address: 0x36000 #define mmCPG_PERFCOUNTER1_SELECT … #define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX … #define mmCPG_PERFCOUNTER0_SELECT1 … #define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmCPG_PERFCOUNTER0_SELECT … #define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX … #define mmCPC_PERFCOUNTER1_SELECT … #define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX … #define mmCPC_PERFCOUNTER0_SELECT1 … #define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmCPF_PERFCOUNTER1_SELECT … #define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX … #define mmCPF_PERFCOUNTER0_SELECT1 … #define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmCPF_PERFCOUNTER0_SELECT … #define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX … #define mmCP_PERFMON_CNTL … #define mmCP_PERFMON_CNTL_BASE_IDX … #define mmCPC_PERFCOUNTER0_SELECT … #define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX … #define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT … #define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX … #define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT … #define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX … #define mmCPF_LATENCY_STATS_SELECT … #define mmCPF_LATENCY_STATS_SELECT_BASE_IDX … #define mmCPG_LATENCY_STATS_SELECT … #define mmCPG_LATENCY_STATS_SELECT_BASE_IDX … #define mmCPC_LATENCY_STATS_SELECT … #define mmCPC_LATENCY_STATS_SELECT_BASE_IDX … #define mmCP_DRAW_OBJECT … #define mmCP_DRAW_OBJECT_BASE_IDX … #define mmCP_DRAW_OBJECT_COUNTER … #define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX … #define mmCP_DRAW_WINDOW_MASK_HI … #define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX … #define mmCP_DRAW_WINDOW_HI … #define mmCP_DRAW_WINDOW_HI_BASE_IDX … #define mmCP_DRAW_WINDOW_LO … #define mmCP_DRAW_WINDOW_LO_BASE_IDX … #define mmCP_DRAW_WINDOW_CNTL … #define mmCP_DRAW_WINDOW_CNTL_BASE_IDX … #define mmGRBM_PERFCOUNTER0_SELECT … #define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX … #define mmGRBM_PERFCOUNTER1_SELECT … #define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX … #define mmGRBM_SE0_PERFCOUNTER_SELECT … #define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX … #define mmGRBM_SE1_PERFCOUNTER_SELECT … #define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX … #define mmGRBM_SE2_PERFCOUNTER_SELECT … #define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX … #define mmGRBM_SE3_PERFCOUNTER_SELECT … #define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX … #define mmGRBM_PERFCOUNTER0_SELECT_HI … #define mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX … #define mmGRBM_PERFCOUNTER1_SELECT_HI … #define mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX … #define mmGE_PERFCOUNTER0_SELECT … #define mmGE_PERFCOUNTER0_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER0_SELECT1 … #define mmGE_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmGE_PERFCOUNTER1_SELECT … #define mmGE_PERFCOUNTER1_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER1_SELECT1 … #define mmGE_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmGE_PERFCOUNTER2_SELECT … #define mmGE_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER2_SELECT1 … #define mmGE_PERFCOUNTER2_SELECT1_BASE_IDX … #define mmGE_PERFCOUNTER3_SELECT … #define mmGE_PERFCOUNTER3_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER3_SELECT1 … #define mmGE_PERFCOUNTER3_SELECT1_BASE_IDX … #define mmGE_PERFCOUNTER4_SELECT … #define mmGE_PERFCOUNTER4_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER5_SELECT … #define mmGE_PERFCOUNTER5_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER6_SELECT … #define mmGE_PERFCOUNTER6_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER7_SELECT … #define mmGE_PERFCOUNTER7_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER8_SELECT … #define mmGE_PERFCOUNTER8_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER9_SELECT … #define mmGE_PERFCOUNTER9_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER10_SELECT … #define mmGE_PERFCOUNTER10_SELECT_BASE_IDX … #define mmGE_PERFCOUNTER11_SELECT … #define mmGE_PERFCOUNTER11_SELECT_BASE_IDX … #define mmPA_SU_PERFCOUNTER0_SELECT … #define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX … #define mmPA_SU_PERFCOUNTER0_SELECT1 … #define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmPA_SU_PERFCOUNTER1_SELECT … #define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX … #define mmPA_SU_PERFCOUNTER1_SELECT1 … #define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmPA_SU_PERFCOUNTER2_SELECT … #define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX … #define mmPA_SU_PERFCOUNTER2_SELECT1 … #define mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX … #define mmPA_SU_PERFCOUNTER3_SELECT … #define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX … #define mmPA_SU_PERFCOUNTER3_SELECT1 … #define mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX … #define mmPA_SC_PERFCOUNTER0_SELECT … #define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX … #define mmPA_SC_PERFCOUNTER0_SELECT1 … #define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmPA_SC_PERFCOUNTER1_SELECT … #define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX … #define mmPA_SC_PERFCOUNTER2_SELECT … #define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX … #define mmPA_SC_PERFCOUNTER3_SELECT … #define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX … #define mmPA_SC_PERFCOUNTER4_SELECT … #define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX … #define mmPA_SC_PERFCOUNTER5_SELECT … #define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX … #define mmPA_SC_PERFCOUNTER6_SELECT … #define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX … #define mmPA_SC_PERFCOUNTER7_SELECT … #define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX … #define mmSPI_PERFCOUNTER0_SELECT … #define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX … #define mmSPI_PERFCOUNTER1_SELECT … #define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX … #define mmSPI_PERFCOUNTER2_SELECT … #define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX … #define mmSPI_PERFCOUNTER3_SELECT … #define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX … #define mmSPI_PERFCOUNTER0_SELECT1 … #define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmSPI_PERFCOUNTER1_SELECT1 … #define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmSPI_PERFCOUNTER2_SELECT1 … #define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX … #define mmSPI_PERFCOUNTER3_SELECT1 … #define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX … #define mmSPI_PERFCOUNTER4_SELECT … #define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX … #define mmSPI_PERFCOUNTER5_SELECT … #define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX … #define mmSPI_PERFCOUNTER_BINS … #define mmSPI_PERFCOUNTER_BINS_BASE_IDX … #define mmSQ_PERFCOUNTER0_SELECT … #define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER1_SELECT … #define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER2_SELECT … #define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER3_SELECT … #define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER4_SELECT … #define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER5_SELECT … #define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER6_SELECT … #define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER7_SELECT … #define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER8_SELECT … #define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER9_SELECT … #define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER10_SELECT … #define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER11_SELECT … #define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER12_SELECT … #define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER13_SELECT … #define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER14_SELECT … #define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER15_SELECT … #define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX … #define mmSQ_PERFCOUNTER_CTRL … #define mmSQ_PERFCOUNTER_CTRL_BASE_IDX … #define mmSQ_PERFCOUNTER_CTRL2 … #define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX … #define mmGCEA_PERFCOUNTER2_SELECT … #define mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGCEA_PERFCOUNTER2_SELECT1 … #define mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX … #define mmGCEA_PERFCOUNTER2_MODE … #define mmGCEA_PERFCOUNTER2_MODE_BASE_IDX … #define mmSX_PERFCOUNTER0_SELECT … #define mmSX_PERFCOUNTER0_SELECT_BASE_IDX … #define mmSX_PERFCOUNTER1_SELECT … #define mmSX_PERFCOUNTER1_SELECT_BASE_IDX … #define mmSX_PERFCOUNTER2_SELECT … #define mmSX_PERFCOUNTER2_SELECT_BASE_IDX … #define mmSX_PERFCOUNTER3_SELECT … #define mmSX_PERFCOUNTER3_SELECT_BASE_IDX … #define mmSX_PERFCOUNTER0_SELECT1 … #define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmSX_PERFCOUNTER1_SELECT1 … #define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmGDS_PERFCOUNTER0_SELECT … #define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX … #define mmGDS_PERFCOUNTER1_SELECT … #define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX … #define mmGDS_PERFCOUNTER2_SELECT … #define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGDS_PERFCOUNTER3_SELECT … #define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX … #define mmGDS_PERFCOUNTER0_SELECT1 … #define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmTA_PERFCOUNTER0_SELECT … #define mmTA_PERFCOUNTER0_SELECT_BASE_IDX … #define mmTA_PERFCOUNTER0_SELECT1 … #define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmTA_PERFCOUNTER1_SELECT … #define mmTA_PERFCOUNTER1_SELECT_BASE_IDX … #define mmTD_PERFCOUNTER0_SELECT … #define mmTD_PERFCOUNTER0_SELECT_BASE_IDX … #define mmTD_PERFCOUNTER0_SELECT1 … #define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmTD_PERFCOUNTER1_SELECT … #define mmTD_PERFCOUNTER1_SELECT_BASE_IDX … #define mmTCP_PERFCOUNTER0_SELECT … #define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX … #define mmTCP_PERFCOUNTER0_SELECT1 … #define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmTCP_PERFCOUNTER1_SELECT … #define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX … #define mmTCP_PERFCOUNTER1_SELECT1 … #define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmTCP_PERFCOUNTER2_SELECT … #define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX … #define mmTCP_PERFCOUNTER3_SELECT … #define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX … #define mmGL2C_PERFCOUNTER0_SELECT … #define mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX … #define mmGL2C_PERFCOUNTER0_SELECT1 … #define mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmGL2C_PERFCOUNTER1_SELECT … #define mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX … #define mmGL2C_PERFCOUNTER1_SELECT1 … #define mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmGL2C_PERFCOUNTER2_SELECT … #define mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGL2C_PERFCOUNTER3_SELECT … #define mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX … #define mmGL2A_PERFCOUNTER0_SELECT … #define mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX … #define mmGL2A_PERFCOUNTER0_SELECT1 … #define mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmGL2A_PERFCOUNTER1_SELECT … #define mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX … #define mmGL2A_PERFCOUNTER1_SELECT1 … #define mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmGL2A_PERFCOUNTER2_SELECT … #define mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGL2A_PERFCOUNTER3_SELECT … #define mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX … #define mmGL1C_PERFCOUNTER0_SELECT … #define mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX … #define mmGL1C_PERFCOUNTER0_SELECT1 … #define mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmGL1C_PERFCOUNTER1_SELECT … #define mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX … #define mmGL1C_PERFCOUNTER2_SELECT … #define mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGL1C_PERFCOUNTER3_SELECT … #define mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX … #define mmCHC_PERFCOUNTER0_SELECT … #define mmCHC_PERFCOUNTER0_SELECT_BASE_IDX … #define mmCHC_PERFCOUNTER0_SELECT1 … #define mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmCHC_PERFCOUNTER1_SELECT … #define mmCHC_PERFCOUNTER1_SELECT_BASE_IDX … #define mmCHC_PERFCOUNTER2_SELECT … #define mmCHC_PERFCOUNTER2_SELECT_BASE_IDX … #define mmCHC_PERFCOUNTER3_SELECT … #define mmCHC_PERFCOUNTER3_SELECT_BASE_IDX … #define mmCHCG_PERFCOUNTER0_SELECT … #define mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX … #define mmCHCG_PERFCOUNTER0_SELECT1 … #define mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmCHCG_PERFCOUNTER1_SELECT … #define mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX … #define mmCHCG_PERFCOUNTER2_SELECT … #define mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX … #define mmCHCG_PERFCOUNTER3_SELECT … #define mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX … #define mmCB_PERFCOUNTER_FILTER … #define mmCB_PERFCOUNTER_FILTER_BASE_IDX … #define mmCB_PERFCOUNTER0_SELECT … #define mmCB_PERFCOUNTER0_SELECT_BASE_IDX … #define mmCB_PERFCOUNTER0_SELECT1 … #define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmCB_PERFCOUNTER1_SELECT … #define mmCB_PERFCOUNTER1_SELECT_BASE_IDX … #define mmCB_PERFCOUNTER2_SELECT … #define mmCB_PERFCOUNTER2_SELECT_BASE_IDX … #define mmCB_PERFCOUNTER3_SELECT … #define mmCB_PERFCOUNTER3_SELECT_BASE_IDX … #define mmDB_PERFCOUNTER0_SELECT … #define mmDB_PERFCOUNTER0_SELECT_BASE_IDX … #define mmDB_PERFCOUNTER0_SELECT1 … #define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmDB_PERFCOUNTER1_SELECT … #define mmDB_PERFCOUNTER1_SELECT_BASE_IDX … #define mmDB_PERFCOUNTER1_SELECT1 … #define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmDB_PERFCOUNTER2_SELECT … #define mmDB_PERFCOUNTER2_SELECT_BASE_IDX … #define mmDB_PERFCOUNTER3_SELECT … #define mmDB_PERFCOUNTER3_SELECT_BASE_IDX … #define mmRLC_SPM_PERFMON_CNTL … #define mmRLC_SPM_PERFMON_CNTL_BASE_IDX … #define mmRLC_SPM_PERFMON_RING_BASE_LO … #define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX … #define mmRLC_SPM_PERFMON_RING_BASE_HI … #define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX … #define mmRLC_SPM_PERFMON_RING_SIZE … #define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX … #define mmRLC_SPM_PERFMON_SEGMENT_SIZE … #define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX … #define mmRLC_SPM_RING_RDPTR … #define mmRLC_SPM_RING_RDPTR_BASE_IDX … #define mmRLC_SPM_SEGMENT_THRESHOLD … #define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX … #define mmRLC_SPM_SE_MUXSEL_ADDR … #define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX … #define mmRLC_SPM_SE_MUXSEL_DATA … #define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX … #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR … #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX … #define mmRLC_SPM_GLOBAL_MUXSEL_DATA … #define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX … #define mmRLC_SPM_DESER_START_SKEW … #define mmRLC_SPM_DESER_START_SKEW_BASE_IDX … #define mmRLC_SPM_GLOBALS_SAMPLE_SKEW … #define mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX … #define mmRLC_SPM_GLOBALS_MUXSEL_SKEW … #define mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX … #define mmRLC_SPM_SE_SAMPLE_SKEW … #define mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX … #define mmRLC_SPM_SE_MUXSEL_SKEW … #define mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX … #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR … #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX … #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA … #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX … #define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR … #define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX … #define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA … #define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX … #define mmRLC_SPM_RING_WRPTR … #define mmRLC_SPM_RING_WRPTR_BASE_IDX … #define mmRLC_SPM_ACCUM_DATARAM_ADDR … #define mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX … #define mmRLC_SPM_ACCUM_DATARAM_DATA … #define mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX … #define mmRLC_SPM_ACCUM_CTRLRAM_ADDR … #define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX … #define mmRLC_SPM_ACCUM_CTRLRAM_DATA … #define mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX … #define mmRLC_SPM_ACCUM_STATUS … #define mmRLC_SPM_ACCUM_STATUS_BASE_IDX … #define mmRLC_SPM_ACCUM_CTRL … #define mmRLC_SPM_ACCUM_CTRL_BASE_IDX … #define mmRLC_SPM_ACCUM_MODE … #define mmRLC_SPM_ACCUM_MODE_BASE_IDX … #define mmRLC_SPM_ACCUM_THRESHOLD … #define mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX … #define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED … #define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX … #define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT … #define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX … #define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE … #define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX … #define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE … #define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX … #define mmRLC_SPM_VIRT_CTRL … #define mmRLC_SPM_VIRT_CTRL_BASE_IDX … #define mmRLC_SPM_VIRT_STATUS … #define mmRLC_SPM_VIRT_STATUS_BASE_IDX … #define mmRLC_PERFMON_CNTL … #define mmRLC_PERFMON_CNTL_BASE_IDX … #define mmRLC_PERFCOUNTER0_SELECT … #define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX … #define mmRLC_PERFCOUNTER1_SELECT … #define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX … #define mmRLC_GPU_IOV_PERF_CNT_CNTL … #define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX … #define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR … #define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX … #define mmRLC_GPU_IOV_PERF_CNT_WR_DATA … #define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX … #define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR … #define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX … #define mmRLC_GPU_IOV_PERF_CNT_RD_DATA … #define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX … #define mmRLC_PERFMON_CLK_CNTL … #define mmRLC_PERFMON_CLK_CNTL_BASE_IDX … #define mmRLC_PERFMON_CLK_CNTL_UCODE … #define mmRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX … #define mmRMI_PERFCOUNTER0_SELECT … #define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX … #define mmRMI_PERFCOUNTER0_SELECT1 … #define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmRMI_PERFCOUNTER1_SELECT … #define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX … #define mmRMI_PERFCOUNTER2_SELECT … #define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX … #define mmRMI_PERFCOUNTER2_SELECT1 … #define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX … #define mmRMI_PERFCOUNTER3_SELECT … #define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX … #define mmRMI_PERF_COUNTER_CNTL … #define mmRMI_PERF_COUNTER_CNTL_BASE_IDX … #define mmGCR_PERFCOUNTER0_SELECT … #define mmGCR_PERFCOUNTER0_SELECT_BASE_IDX … #define mmGCR_PERFCOUNTER0_SELECT1 … #define mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmGCR_PERFCOUNTER1_SELECT … #define mmGCR_PERFCOUNTER1_SELECT_BASE_IDX … #define mmUTCL1_PERFCOUNTER0_SELECT … #define mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX … #define mmUTCL1_PERFCOUNTER1_SELECT … #define mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER0_SELECT … #define mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER0_SELECT1 … #define mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmPA_PH_PERFCOUNTER1_SELECT … #define mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER2_SELECT … #define mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER3_SELECT … #define mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER4_SELECT … #define mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER5_SELECT … #define mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER6_SELECT … #define mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER7_SELECT … #define mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX … #define mmPA_PH_PERFCOUNTER1_SELECT1 … #define mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX … #define mmPA_PH_PERFCOUNTER2_SELECT1 … #define mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX … #define mmPA_PH_PERFCOUNTER3_SELECT1 … #define mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX … #define mmGL1A_PERFCOUNTER0_SELECT … #define mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX … #define mmGL1A_PERFCOUNTER0_SELECT1 … #define mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmGL1A_PERFCOUNTER1_SELECT … #define mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX … #define mmGL1A_PERFCOUNTER2_SELECT … #define mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGL1A_PERFCOUNTER3_SELECT … #define mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX … #define mmCHA_PERFCOUNTER0_SELECT … #define mmCHA_PERFCOUNTER0_SELECT_BASE_IDX … #define mmCHA_PERFCOUNTER0_SELECT1 … #define mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX … #define mmCHA_PERFCOUNTER1_SELECT … #define mmCHA_PERFCOUNTER1_SELECT_BASE_IDX … #define mmCHA_PERFCOUNTER2_SELECT … #define mmCHA_PERFCOUNTER2_SELECT_BASE_IDX … #define mmCHA_PERFCOUNTER3_SELECT … #define mmCHA_PERFCOUNTER3_SELECT_BASE_IDX … #define mmGUS_PERFCOUNTER2_SELECT … #define mmGUS_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGUS_PERFCOUNTER2_SELECT1 … #define mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX … #define mmGUS_PERFCOUNTER2_MODE … #define mmGUS_PERFCOUNTER2_MODE_BASE_IDX … // addressBlock: gc_gcatcl2pfcntldec // base address: 0x37480 #define mmGC_ATC_L2_PERFCOUNTER0_CFG … #define mmGC_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmGC_ATC_L2_PERFCOUNTER1_CFG … #define mmGC_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmGC_ATC_L2_PERFCOUNTER_RSLT_CNTL … #define mmGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: gc_gcvml2pldec // base address: 0x374b0 #define mmGCMC_VM_L2_PERFCOUNTER0_CFG … #define mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER1_CFG … #define mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER2_CFG … #define mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER3_CFG … #define mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER4_CFG … #define mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER5_CFG … #define mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER6_CFG … #define mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER7_CFG … #define mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: gc_gcvml2perfsdec // base address: 0x374f0 #define mmGCVML2_PERFCOUNTER2_0_SELECT … #define mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX … #define mmGCVML2_PERFCOUNTER2_1_SELECT … #define mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX … #define mmGCVML2_PERFCOUNTER2_0_SELECT1 … #define mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX … #define mmGCVML2_PERFCOUNTER2_1_SELECT1 … #define mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX … #define mmGCVML2_PERFCOUNTER2_0_MODE … #define mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX … #define mmGCVML2_PERFCOUNTER2_1_MODE … #define mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX … // addressBlock: gc_gcatcl2perfsdec // base address: 0x37530 #define mmGC_ATC_L2_PERFCOUNTER2_SELECT … #define mmGC_ATC_L2_PERFCOUNTER2_SELECT_BASE_IDX … #define mmGC_ATC_L2_PERFCOUNTER2_SELECT1 … #define mmGC_ATC_L2_PERFCOUNTER2_SELECT1_BASE_IDX … #define mmGC_ATC_L2_PERFCOUNTER2_MODE … #define mmGC_ATC_L2_PERFCOUNTER2_MODE_BASE_IDX … // addressBlock: gc_rlcdec // base address: 0x3b000 #define mmRLC_CNTL … #define mmRLC_CNTL_BASE_IDX … #define mmRLC_F32_UCODE_VERSION … #define mmRLC_F32_UCODE_VERSION_BASE_IDX … #define mmRLC_STAT … #define mmRLC_STAT_BASE_IDX … #define mmRLC_SAFE_MODE … #define mmRLC_SAFE_MODE_BASE_IDX … #define mmRLC_MEM_SLP_CNTL … #define mmRLC_MEM_SLP_CNTL_BASE_IDX … #define mmSMU_RLC_RESPONSE … #define mmSMU_RLC_RESPONSE_BASE_IDX … #define mmRLC_RLCV_SAFE_MODE … #define mmRLC_RLCV_SAFE_MODE_BASE_IDX … #define mmRLC_SMU_SAFE_MODE … #define mmRLC_SMU_SAFE_MODE_BASE_IDX … #define mmRLC_RLCV_COMMAND … #define mmRLC_RLCV_COMMAND_BASE_IDX … #define mmRLC_REFCLOCK_TIMESTAMP_LSB … #define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX … #define mmRLC_REFCLOCK_TIMESTAMP_MSB … #define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX … #define mmRLC_GPM_TIMER_INT_0 … #define mmRLC_GPM_TIMER_INT_0_BASE_IDX … #define mmRLC_GPM_TIMER_INT_1 … #define mmRLC_GPM_TIMER_INT_1_BASE_IDX … #define mmRLC_GPM_TIMER_INT_2 … #define mmRLC_GPM_TIMER_INT_2_BASE_IDX … #define mmRLC_GPM_TIMER_CTRL … #define mmRLC_GPM_TIMER_CTRL_BASE_IDX … #define mmRLC_LB_CNTR_MAX_1 … #define mmRLC_LB_CNTR_MAX_1_BASE_IDX … #define mmRLC_GPM_TIMER_STAT … #define mmRLC_GPM_TIMER_STAT_BASE_IDX … #define mmRLC_GPM_TIMER_INT_3 … #define mmRLC_GPM_TIMER_INT_3_BASE_IDX … #define mmRLC_INT_STAT … #define mmRLC_INT_STAT_BASE_IDX … #define mmRLC_LB_CNTL … #define mmRLC_LB_CNTL_BASE_IDX … #define mmRLC_MGCG_CTRL … #define mmRLC_MGCG_CTRL_BASE_IDX … #define mmRLC_LB_CNTR_INIT_1 … #define mmRLC_LB_CNTR_INIT_1_BASE_IDX … #define mmRLC_LB_CNTR_1 … #define mmRLC_LB_CNTR_1_BASE_IDX … #define mmRLC_GPM_DEBUG_INST_ADDR … #define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX … #define mmRLC_JUMP_TABLE_RESTORE … #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX … #define mmRLC_PG_DELAY_2 … #define mmRLC_PG_DELAY_2_BASE_IDX … #define mmRLC_GPM_DEBUG_INST_A … #define mmRLC_GPM_DEBUG_INST_A_BASE_IDX … #define mmRLC_GPM_DEBUG_INST_B … #define mmRLC_GPM_DEBUG_INST_B_BASE_IDX … #define mmRLC_GPU_CLOCK_COUNT_LSB … #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX … #define mmRLC_GPU_CLOCK_COUNT_MSB … #define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX … #define mmRLC_CAPTURE_GPU_CLOCK_COUNT … #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX … #define mmRLC_UCODE_CNTL … #define mmRLC_UCODE_CNTL_BASE_IDX … #define mmRLC_GPM_THREAD_RESET … #define mmRLC_GPM_THREAD_RESET_BASE_IDX … #define mmRLC_GPM_CP_DMA_COMPLETE_T0 … #define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX … #define mmRLC_GPM_CP_DMA_COMPLETE_T1 … #define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX … #define mmRLC_LB_CNTR_INIT_2 … #define mmRLC_LB_CNTR_INIT_2_BASE_IDX … #define mmRLC_LB_CNTR_MAX_2 … #define mmRLC_LB_CNTR_MAX_2_BASE_IDX … #define mmRLC_LB_CONFIG_5 … #define mmRLC_LB_CONFIG_5_BASE_IDX … #define mmRLC_CLK_COUNT_GFXCLK_LSB … #define mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX … #define mmRLC_CLK_COUNT_GFXCLK_MSB … #define mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX … #define mmRLC_CLK_COUNT_REFCLK_LSB … #define mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX … #define mmRLC_CLK_COUNT_REFCLK_MSB … #define mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX … #define mmRLC_CLK_COUNT_CTRL … #define mmRLC_CLK_COUNT_CTRL_BASE_IDX … #define mmRLC_CLK_COUNT_STAT … #define mmRLC_CLK_COUNT_STAT_BASE_IDX … #define mmRLC_GPU_CLOCK_32_RES_SEL … #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … #define mmRLC_GPU_CLOCK_32 … #define mmRLC_GPU_CLOCK_32_BASE_IDX … #define mmRLC_PG_CNTL … #define mmRLC_PG_CNTL_BASE_IDX … #define mmRLC_GPM_THREAD_PRIORITY … #define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX … #define mmRLC_GPM_THREAD_ENABLE … #define mmRLC_GPM_THREAD_ENABLE_BASE_IDX … #define mmRLC_CGTT_MGCG_OVERRIDE … #define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX … #define mmRLC_CGCG_CGLS_CTRL … #define mmRLC_CGCG_CGLS_CTRL_BASE_IDX … #define mmRLC_CGCG_RAMP_CTRL … #define mmRLC_CGCG_RAMP_CTRL_BASE_IDX … #define mmRLC_DYN_PG_STATUS … #define mmRLC_DYN_PG_STATUS_BASE_IDX … #define mmRLC_DYN_PG_REQUEST … #define mmRLC_DYN_PG_REQUEST_BASE_IDX … #define mmRLC_PG_DELAY … #define mmRLC_PG_DELAY_BASE_IDX … #define mmRLC_WGP_STATUS … #define mmRLC_WGP_STATUS_BASE_IDX … #define mmRLC_LB_INIT_WGP_MASK … #define mmRLC_LB_INIT_WGP_MASK_BASE_IDX … #define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK … #define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX … #define mmRLC_LB_PARAMS … #define mmRLC_LB_PARAMS_BASE_IDX … #define mmRLC_LB_DELAY … #define mmRLC_LB_DELAY_BASE_IDX … #define mmRLC_PG_ALWAYS_ON_WGP_MASK … #define mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX … #define mmRLC_MAX_PG_WGP … #define mmRLC_MAX_PG_WGP_BASE_IDX … #define mmRLC_AUTO_PG_CTRL … #define mmRLC_AUTO_PG_CTRL_BASE_IDX … #define mmRLC_SMU_GRBM_REG_SAVE_CTRL … #define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX … #define mmRLC_SERDES_RD_INDEX … #define mmRLC_SERDES_RD_INDEX_BASE_IDX … #define mmRLC_SERDES_RD_DATA_0 … #define mmRLC_SERDES_RD_DATA_0_BASE_IDX … #define mmRLC_SERDES_RD_DATA_1 … #define mmRLC_SERDES_RD_DATA_1_BASE_IDX … #define mmRLC_SERDES_RD_DATA_2 … #define mmRLC_SERDES_RD_DATA_2_BASE_IDX … #define mmRLC_SERDES_RD_DATA_3 … #define mmRLC_SERDES_RD_DATA_3_BASE_IDX … #define mmRLC_SERDES_MASK … #define mmRLC_SERDES_MASK_BASE_IDX … #define mmRLC_SERDES_CTRL … #define mmRLC_SERDES_CTRL_BASE_IDX … #define mmRLC_SERDES_DATA … #define mmRLC_SERDES_DATA_BASE_IDX … #define mmRLC_SERDES_BUSY … #define mmRLC_SERDES_BUSY_BASE_IDX … #define mmRLC_GPM_GENERAL_0 … #define mmRLC_GPM_GENERAL_0_BASE_IDX … #define mmRLC_GPM_GENERAL_1 … #define mmRLC_GPM_GENERAL_1_BASE_IDX … #define mmRLC_GPM_GENERAL_2 … #define mmRLC_GPM_GENERAL_2_BASE_IDX … #define mmRLC_GPM_GENERAL_3 … #define mmRLC_GPM_GENERAL_3_BASE_IDX … #define mmRLC_GPM_GENERAL_4 … #define mmRLC_GPM_GENERAL_4_BASE_IDX … #define mmRLC_GPM_GENERAL_5 … #define mmRLC_GPM_GENERAL_5_BASE_IDX … #define mmRLC_GPM_GENERAL_6 … #define mmRLC_GPM_GENERAL_6_BASE_IDX … #define mmRLC_GPM_GENERAL_7 … #define mmRLC_GPM_GENERAL_7_BASE_IDX … #define mmRLC_STATIC_PG_STATUS … #define mmRLC_STATIC_PG_STATUS_BASE_IDX … #define mmRLC_SPM_INT_INFO_1 … #define mmRLC_SPM_INT_INFO_1_BASE_IDX … #define mmRLC_SPM_INT_INFO_2 … #define mmRLC_SPM_INT_INFO_2_BASE_IDX … #define mmRLC_SPM_MC_CNTL … #define mmRLC_SPM_MC_CNTL_BASE_IDX … #define mmRLC_SPM_INT_CNTL … #define mmRLC_SPM_INT_CNTL_BASE_IDX … #define mmRLC_SPM_INT_STATUS … #define mmRLC_SPM_INT_STATUS_BASE_IDX … #define mmRLC_SMU_MESSAGE … #define mmRLC_SMU_MESSAGE_BASE_IDX … #define mmRLC_GPM_LOG_SIZE … #define mmRLC_GPM_LOG_SIZE_BASE_IDX … #define mmRLC_PG_DELAY_3 … #define mmRLC_PG_DELAY_3_BASE_IDX … #define mmRLC_GPR_REG1 … #define mmRLC_GPR_REG1_BASE_IDX … #define mmRLC_GPR_REG2 … #define mmRLC_GPR_REG2_BASE_IDX … #define mmRLC_GPM_LOG_CONT … #define mmRLC_GPM_LOG_CONT_BASE_IDX … #define mmRLC_GPM_INT_DISABLE_TH0 … #define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX … #define mmRLC_GPM_INT_FORCE_TH0 … #define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX … #define mmRLC_SRM_CNTL … #define mmRLC_SRM_CNTL_BASE_IDX … #define mmRLC_SRM_GPM_COMMAND … #define mmRLC_SRM_GPM_COMMAND_BASE_IDX … #define mmRLC_SRM_GPM_COMMAND_STATUS … #define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX … #define mmRLC_SRM_RLCV_COMMAND … #define mmRLC_SRM_RLCV_COMMAND_BASE_IDX … #define mmRLC_SRM_RLCV_COMMAND_STATUS … #define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_ADDR_0 … #define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_ADDR_1 … #define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_ADDR_2 … #define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_ADDR_3 … #define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_ADDR_4 … #define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_ADDR_5 … #define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_ADDR_6 … #define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_ADDR_7 … #define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_DATA_0 … #define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_DATA_1 … #define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_DATA_2 … #define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_DATA_3 … #define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_DATA_4 … #define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_DATA_5 … #define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_DATA_6 … #define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX … #define mmRLC_SRM_INDEX_CNTL_DATA_7 … #define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX … #define mmRLC_SRM_STAT … #define mmRLC_SRM_STAT_BASE_IDX … #define mmRLC_SRM_GPM_ABORT … #define mmRLC_SRM_GPM_ABORT_BASE_IDX … #define mmRLC_CSIB_ADDR_LO … #define mmRLC_CSIB_ADDR_LO_BASE_IDX … #define mmRLC_CSIB_ADDR_HI … #define mmRLC_CSIB_ADDR_HI_BASE_IDX … #define mmRLC_CSIB_LENGTH … #define mmRLC_CSIB_LENGTH_BASE_IDX … #define mmRLC_PACE_INT_STAT … #define mmRLC_PACE_INT_STAT_BASE_IDX … #define mmRLC_SMU_COMMAND … #define mmRLC_SMU_COMMAND_BASE_IDX … #define mmRLC_CP_SCHEDULERS … #define mmRLC_CP_SCHEDULERS_BASE_IDX … #define mmRLC_SMU_ARGUMENT_1 … #define mmRLC_SMU_ARGUMENT_1_BASE_IDX … #define mmRLC_SMU_ARGUMENT_2 … #define mmRLC_SMU_ARGUMENT_2_BASE_IDX … #define mmRLC_GPM_GENERAL_8 … #define mmRLC_GPM_GENERAL_8_BASE_IDX … #define mmRLC_GPM_GENERAL_9 … #define mmRLC_GPM_GENERAL_9_BASE_IDX … #define mmRLC_GPM_GENERAL_10 … #define mmRLC_GPM_GENERAL_10_BASE_IDX … #define mmRLC_GPM_GENERAL_11 … #define mmRLC_GPM_GENERAL_11_BASE_IDX … #define mmRLC_GPM_GENERAL_12 … #define mmRLC_GPM_GENERAL_12_BASE_IDX … #define mmRLC_GPM_UTCL1_CNTL_0 … #define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX … #define mmRLC_GPM_UTCL1_CNTL_1 … #define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX … #define mmRLC_GPM_UTCL1_CNTL_2 … #define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX … #define mmRLC_SPM_UTCL1_CNTL … #define mmRLC_SPM_UTCL1_CNTL_BASE_IDX … #define mmRLC_UTCL1_STATUS_2 … #define mmRLC_UTCL1_STATUS_2_BASE_IDX … #define mmRLC_LB_CONFIG_2 … #define mmRLC_LB_CONFIG_2_BASE_IDX … #define mmRLC_LB_CONFIG_3 … #define mmRLC_LB_CONFIG_3_BASE_IDX … #define mmRLC_LB_CONFIG_4 … #define mmRLC_LB_CONFIG_4_BASE_IDX … #define mmRLC_SPM_UTCL1_ERROR_1 … #define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX … #define mmRLC_SPM_UTCL1_ERROR_2 … #define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX … #define mmRLC_GPM_UTCL1_TH0_ERROR_1 … #define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX … #define mmRLC_LB_CONFIG_1 … #define mmRLC_LB_CONFIG_1_BASE_IDX … #define mmRLC_GPM_UTCL1_TH0_ERROR_2 … #define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX … #define mmRLC_GPM_UTCL1_TH1_ERROR_1 … #define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX … #define mmRLC_GPM_UTCL1_TH1_ERROR_2 … #define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX … #define mmRLC_GPM_UTCL1_TH2_ERROR_1 … #define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX … #define mmRLC_GPM_UTCL1_TH2_ERROR_2 … #define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX … #define mmRLC_CGCG_CGLS_CTRL_3D … #define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX … #define mmRLC_CGCG_RAMP_CTRL_3D … #define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX … #define mmRLC_SEMAPHORE_0 … #define mmRLC_SEMAPHORE_0_BASE_IDX … #define mmRLC_SEMAPHORE_1 … #define mmRLC_SEMAPHORE_1_BASE_IDX … #define mmRLC_CP_EOF_INT … #define mmRLC_CP_EOF_INT_BASE_IDX … #define mmRLC_CP_EOF_INT_CNT … #define mmRLC_CP_EOF_INT_CNT_BASE_IDX … #define mmRLC_SPARE_INT … #define mmRLC_SPARE_INT_BASE_IDX … #define mmRLC_PREWALKER_UTCL1_CNTL … #define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX … #define mmRLC_PREWALKER_UTCL1_TRIG … #define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX … #define mmRLC_PREWALKER_UTCL1_ADDR_LSB … #define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX … #define mmRLC_PREWALKER_UTCL1_ADDR_MSB … #define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX … #define mmRLC_PREWALKER_UTCL1_SIZE_LSB … #define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX … #define mmRLC_PREWALKER_UTCL1_SIZE_MSB … #define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX … #define mmRLC_UTCL1_STATUS … #define mmRLC_UTCL1_STATUS_BASE_IDX … #define mmRLC_R2I_CNTL_0 … #define mmRLC_R2I_CNTL_0_BASE_IDX … #define mmRLC_R2I_CNTL_1 … #define mmRLC_R2I_CNTL_1_BASE_IDX … #define mmRLC_R2I_CNTL_2 … #define mmRLC_R2I_CNTL_2_BASE_IDX … #define mmRLC_R2I_CNTL_3 … #define mmRLC_R2I_CNTL_3_BASE_IDX … #define mmRLC_LB_WGP_STAT … #define mmRLC_LB_WGP_STAT_BASE_IDX … #define mmRLC_GPM_INT_STAT_TH0 … #define mmRLC_GPM_INT_STAT_TH0_BASE_IDX … #define mmRLC_GPM_GENERAL_13 … #define mmRLC_GPM_GENERAL_13_BASE_IDX … #define mmRLC_GPM_GENERAL_14 … #define mmRLC_GPM_GENERAL_14_BASE_IDX … #define mmRLC_GPM_GENERAL_15 … #define mmRLC_GPM_GENERAL_15_BASE_IDX … #define mmRLC_SPARE_INT_1 … #define mmRLC_SPARE_INT_1_BASE_IDX … #define mmRLC_RLCV_SPARE_INT_1 … #define mmRLC_RLCV_SPARE_INT_1_BASE_IDX … #define mmRLC_PACE_SPARE_INT_1 … #define mmRLC_PACE_SPARE_INT_1_BASE_IDX … #define mmRLC_SEMAPHORE_2 … #define mmRLC_SEMAPHORE_2_BASE_IDX … #define mmRLC_SEMAPHORE_3 … #define mmRLC_SEMAPHORE_3_BASE_IDX … #define mmRLC_SMU_ARGUMENT_3 … #define mmRLC_SMU_ARGUMENT_3_BASE_IDX … #define mmRLC_SMU_ARGUMENT_4 … #define mmRLC_SMU_ARGUMENT_4_BASE_IDX … #define mmRLC_GPU_CLOCK_COUNT_LSB_1 … #define mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX … #define mmRLC_GPU_CLOCK_COUNT_MSB_1 … #define mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX … #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 … #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX … #define mmRLC_GPU_CLOCK_COUNT_LSB_2 … #define mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX … #define mmRLC_GPU_CLOCK_COUNT_MSB_2 … #define mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX … #define mmRLC_PACE_INT_DISABLE … #define mmRLC_PACE_INT_DISABLE_BASE_IDX … #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 … #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX … #define mmRLC_RLCV_SPARE_INT … #define mmRLC_RLCV_SPARE_INT_BASE_IDX … #define mmRLC_PACE_TIMER_INT_0 … #define mmRLC_PACE_TIMER_INT_0_BASE_IDX … #define mmRLC_PACE_TIMER_CTRL … #define mmRLC_PACE_TIMER_CTRL_BASE_IDX … #define mmRLC_PACE_TIMER_INT_1 … #define mmRLC_PACE_TIMER_INT_1_BASE_IDX … #define mmRLC_PACE_SPARE_INT … #define mmRLC_PACE_SPARE_INT_BASE_IDX … #define mmRLC_SMU_CLK_REQ … #define mmRLC_SMU_CLK_REQ_BASE_IDX … #define mmRLC_CP_STAT_INVAL_STAT … #define mmRLC_CP_STAT_INVAL_STAT_BASE_IDX … #define mmRLC_CP_STAT_INVAL_CTRL … #define mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX … #define mmRLC_SPP_CTRL … #define mmRLC_SPP_CTRL_BASE_IDX … #define mmRLC_SPP_SHADER_PROFILE_EN … #define mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX … #define mmRLC_SPP_SSF_CAPTURE_EN … #define mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX … #define mmRLC_SPP_SSF_THRESHOLD_0 … #define mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX … #define mmRLC_SPP_SSF_THRESHOLD_1 … #define mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX … #define mmRLC_SPP_SSF_THRESHOLD_2 … #define mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX … #define mmRLC_SPP_INFLIGHT_RD_ADDR … #define mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX … #define mmRLC_SPP_INFLIGHT_RD_DATA … #define mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX … #define mmRLC_SPP_PROF_INFO_1 … #define mmRLC_SPP_PROF_INFO_1_BASE_IDX … #define mmRLC_SPP_PROF_INFO_2 … #define mmRLC_SPP_PROF_INFO_2_BASE_IDX … #define mmRLC_SPP_GLOBAL_SH_ID … #define mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX … #define mmRLC_SPP_GLOBAL_SH_ID_VALID … #define mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX … #define mmRLC_SPP_STATUS … #define mmRLC_SPP_STATUS_BASE_IDX … #define mmRLC_SPP_PVT_STAT_0 … #define mmRLC_SPP_PVT_STAT_0_BASE_IDX … #define mmRLC_SPP_PVT_STAT_1 … #define mmRLC_SPP_PVT_STAT_1_BASE_IDX … #define mmRLC_SPP_PVT_STAT_2 … #define mmRLC_SPP_PVT_STAT_2_BASE_IDX … #define mmRLC_SPP_PVT_STAT_3 … #define mmRLC_SPP_PVT_STAT_3_BASE_IDX … #define mmRLC_SPP_PVT_LEVEL_MAX … #define mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX … #define mmRLC_SPP_STALL_STATE_UPDATE … #define mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX … #define mmRLC_SPP_PBB_INFO … #define mmRLC_SPP_PBB_INFO_BASE_IDX … #define mmRLC_SPP_RESET … #define mmRLC_SPP_RESET_BASE_IDX … #define mmRLC_SPM_SAMPLE_CNT … #define mmRLC_SPM_SAMPLE_CNT_BASE_IDX … #define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL … #define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX … #define mmRLC_GPU_CLOCK_COUNT_SPM_LSB … #define mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX … #define mmRLC_GPU_CLOCK_COUNT_SPM_MSB … #define mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX … #define mmRLC_SPM_THREAD_TRACE_CTRL … #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX … #define mmRLC_LB_CNTR_2 … #define mmRLC_LB_CNTR_2_BASE_IDX … #define mmRLC_LX6_CORE_PDEBUG_INST … #define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX … #define mmRLC_CPAXI_DOORBELL_MON_CTRL … #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX … #define mmRLC_CPAXI_DOORBELL_MON_STAT … #define mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX … #define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB … #define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX … #define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB … #define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX … // addressBlock: gc_rlcrdec // base address: 0x3b800 #define mmRLC_SPP_CAM_ADDR … #define mmRLC_SPP_CAM_ADDR_BASE_IDX … #define mmRLC_SPP_CAM_DATA … #define mmRLC_SPP_CAM_DATA_BASE_IDX … #define mmRLC_SPP_CAM_EXT_ADDR … #define mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX … #define mmRLC_SPP_CAM_EXT_DATA … #define mmRLC_SPP_CAM_EXT_DATA_BASE_IDX … #define mmRLC_PACE_SCRATCH_ADDR … #define mmRLC_PACE_SCRATCH_ADDR_BASE_IDX … #define mmRLC_PACE_SCRATCH_DATA … #define mmRLC_PACE_SCRATCH_DATA_BASE_IDX … // addressBlock: gc_rlcsdec // base address: 0x3b980 #define mmRLC_RLCS_DEC_START … #define mmRLC_RLCS_DEC_START_BASE_IDX … #define mmRLC_RLCS_DEC_DUMP_ADDR … #define mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX … #define mmRLC_RLCS_EXCEPTION_REG_1 … #define mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX … #define mmRLC_RLCS_EXCEPTION_REG_2 … #define mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX … #define mmRLC_RLCS_EXCEPTION_REG_3 … #define mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX … #define mmRLC_RLCS_EXCEPTION_REG_4 … #define mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX … #define mmRLC_RLCS_GENERAL_6 … #define mmRLC_RLCS_GENERAL_6_BASE_IDX … #define mmRLC_RLCS_GENERAL_7 … #define mmRLC_RLCS_GENERAL_7_BASE_IDX … #define mmRLC_RLCS_CGCG_REQUEST … #define mmRLC_RLCS_CGCG_REQUEST_BASE_IDX … #define mmRLC_RLCS_CGCG_STATUS … #define mmRLC_RLCS_CGCG_STATUS_BASE_IDX … #define mmRLC_RLCS_SMU_GFXCLK_STATUS … #define mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX … #define mmRLC_RLCS_SMU_GFXCLK_CONTROL … #define mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX … #define mmRLC_RLCS_SOC_DS_CNTL … #define mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX … #define mmRLC_RLCS_GFX_DS_CNTL … #define mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX … #define mmRLC_GPM_STAT … #define mmRLC_GPM_STAT_BASE_IDX … #define mmRLC_RLCS_GPM_STAT … #define mmRLC_RLCS_GPM_STAT_BASE_IDX … #define mmRLC_RLCS_ABORTED_PD_SEQUENCE … #define mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX … #define mmRLC_RLCS_DIDT_FORCE_STALL … #define mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX … #define mmRLC_RLCS_IOV_CMD_STATUS … #define mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX … #define mmRLC_RLCS_IOV_CNTX_LOC_SIZE … #define mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX … #define mmRLC_RLCS_IOV_SCH_BLOCK … #define mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX … #define mmRLC_RLCS_IOV_VM_BUSY_STATUS … #define mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX … #define mmRLC_RLCS_GPM_STAT_2 … #define mmRLC_RLCS_GPM_STAT_2_BASE_IDX … #define mmRLC_RLCS_GRBM_SOFT_RESET … #define mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX … #define mmRLC_RLCS_PG_CHANGE_STATUS … #define mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX … #define mmRLC_RLCS_PG_CHANGE_READ … #define mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX … #define mmRLC_RLCS_LB_STATUS … #define mmRLC_RLCS_LB_STATUS_BASE_IDX … #define mmRLC_RLCS_LB_READ … #define mmRLC_RLCS_LB_READ_BASE_IDX … #define mmRLC_RLCS_LB_CONTROL … #define mmRLC_RLCS_LB_CONTROL_BASE_IDX … #define mmRLC_RLCS_IH_SEMAPHORE … #define mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX … #define mmRLC_RLCS_IH_COOKIE_SEMAPHORE … #define mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX … #define mmRLC_RLCS_IH_CTRL_1 … #define mmRLC_RLCS_IH_CTRL_1_BASE_IDX … #define mmRLC_RLCS_IH_CTRL_2 … #define mmRLC_RLCS_IH_CTRL_2_BASE_IDX … #define mmRLC_RLCS_IH_CTRL_3 … #define mmRLC_RLCS_IH_CTRL_3_BASE_IDX … #define mmRLC_RLCS_IH_STATUS … #define mmRLC_RLCS_IH_STATUS_BASE_IDX … #define mmRLC_RLCS_WGP_STATUS … #define mmRLC_RLCS_WGP_STATUS_BASE_IDX … #define mmRLC_RLCS_WGP_READ … #define mmRLC_RLCS_WGP_READ_BASE_IDX … #define mmRLC_RLCS_CP_INT_CTRL_1 … #define mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX … #define mmRLC_RLCS_CP_INT_CTRL_2 … #define mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX … #define mmRLC_RLCS_CP_INT_INFO_1 … #define mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX … #define mmRLC_RLCS_CP_INT_INFO_2 … #define mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX … #define mmRLC_RLCS_SPM_INT_CTRL … #define mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX … #define mmRLC_RLCS_SPM_INT_INFO_1 … #define mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX … #define mmRLC_RLCS_SPM_INT_INFO_2 … #define mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX … #define mmRLC_RLCS_DSM_TRIG … #define mmRLC_RLCS_DSM_TRIG_BASE_IDX … #define mmRLC_RLCS_GE_FAST_CLOCK … #define mmRLC_RLCS_GE_FAST_CLOCK_BASE_IDX … #define mmRLC_RLCS_BOOTLOAD_STATUS … #define mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX … #define mmRLC_RLCS_POWER_BRAKE_CNTL … #define mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX … #define mmRLC_RLCS_GENERAL_0 … #define mmRLC_RLCS_GENERAL_0_BASE_IDX … #define mmRLC_RLCS_GENERAL_1 … #define mmRLC_RLCS_GENERAL_1_BASE_IDX … #define mmRLC_RLCS_GENERAL_2 … #define mmRLC_RLCS_GENERAL_2_BASE_IDX … #define mmRLC_RLCS_GENERAL_3 … #define mmRLC_RLCS_GENERAL_3_BASE_IDX … #define mmRLC_RLCS_GENERAL_4 … #define mmRLC_RLCS_GENERAL_4_BASE_IDX … #define mmRLC_RLCS_GENERAL_5 … #define mmRLC_RLCS_GENERAL_5_BASE_IDX … #define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT … #define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX … #define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL … #define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX … #define mmRLC_RLCS_CMP_IDLE_CNTL … #define mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX … #define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 … #define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX … #define mmRLC_RLCS_AUXILIARY_REG_1 … #define mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX … #define mmRLC_RLCS_AUXILIARY_REG_2 … #define mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX … #define mmRLC_RLCS_AUXILIARY_REG_3 … #define mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX … #define mmRLC_RLCS_AUXILIARY_REG_4 … #define mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX … #define mmRLC_RLCS_SPM_SQTT_MODE … #define mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX … #define mmRLC_RLCS_CP_DMA_SRCID_OVER … #define mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX … #define mmRLC_RLCS_UTCL2_CNTL … #define mmRLC_RLCS_UTCL2_CNTL_BASE_IDX … #define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL … #define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX … #define mmRLC_RLCS_BOOTLOAD_ID_STATUS1 … #define mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX … #define mmRLC_RLCS_BOOTLOAD_ID_STATUS2 … #define mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX … #define mmRLC_RLCS_EDC_INT_CNTL … #define mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX … #define mmRLC_RLCS_DEC_END … #define mmRLC_RLCS_DEC_END_BASE_IDX … // addressBlock: gc_pwrdec // base address: 0x3c000 #define mmCGTS_SA0_QUAD0_SM_CTRL_REG … #define mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG … #define mmCGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG_BASE_IDX … #define mmCGTS_SA0_QUAD1_SM_CTRL_REG … #define mmCGTS_SA0_QUAD1_SM_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG … #define mmCGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG_BASE_IDX … #define mmCGTS_SA1_QUAD0_SM_CTRL_REG … #define mmCGTS_SA1_QUAD0_SM_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG … #define mmCGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG_BASE_IDX … #define mmCGTS_SA1_QUAD1_SM_CTRL_REG … #define mmCGTS_SA1_QUAD1_SM_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG … #define mmCGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG_BASE_IDX … #define mmCGTS_RD_CTRL_REG … #define mmCGTS_RD_CTRL_REG_BASE_IDX … #define mmCGTS_RD_REG … #define mmCGTS_RD_REG_BASE_IDX … #define mmCGTS_TCC_DISABLE … #define mmCGTS_TCC_DISABLE_BASE_IDX … #define mmCGTS_USER_TCC_DISABLE … #define mmCGTS_USER_TCC_DISABLE_BASE_IDX … #define mmCGTS_STATUS_REG … #define mmCGTS_STATUS_REG_BASE_IDX … #define mmCGTT_SPI_CGTSSM_CLK_CTRL … #define mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX … #define mmCGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP00_CU0_TATD_CTRL_REG … #define mmCGTS_SA0_WGP00_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG … #define mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP00_CU1_TATD_CTRL_REG … #define mmCGTS_SA0_WGP00_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG … #define mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP01_CU0_TATD_CTRL_REG … #define mmCGTS_SA0_WGP01_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG … #define mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP01_CU1_TATD_CTRL_REG … #define mmCGTS_SA0_WGP01_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG … #define mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP02_CU0_TATD_CTRL_REG … #define mmCGTS_SA0_WGP02_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG … #define mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP02_CU1_TATD_CTRL_REG … #define mmCGTS_SA0_WGP02_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG … #define mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP10_CU0_TATD_CTRL_REG … #define mmCGTS_SA0_WGP10_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG … #define mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP10_CU1_TATD_CTRL_REG … #define mmCGTS_SA0_WGP10_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG … #define mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP11_CU0_TATD_CTRL_REG … #define mmCGTS_SA0_WGP11_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG … #define mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP11_CU1_TATD_CTRL_REG … #define mmCGTS_SA0_WGP11_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG … #define mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP00_CU0_TATD_CTRL_REG … #define mmCGTS_SA1_WGP00_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG … #define mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP00_CU1_TATD_CTRL_REG … #define mmCGTS_SA1_WGP00_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG … #define mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP01_CU0_TATD_CTRL_REG … #define mmCGTS_SA1_WGP01_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG … #define mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP01_CU1_TATD_CTRL_REG … #define mmCGTS_SA1_WGP01_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG … #define mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP02_CU0_TATD_CTRL_REG … #define mmCGTS_SA1_WGP02_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG … #define mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP02_CU1_TATD_CTRL_REG … #define mmCGTS_SA1_WGP02_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG … #define mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP10_CU0_TATD_CTRL_REG … #define mmCGTS_SA1_WGP10_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG … #define mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP10_CU1_TATD_CTRL_REG … #define mmCGTS_SA1_WGP10_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG … #define mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP11_CU0_TATD_CTRL_REG … #define mmCGTS_SA1_WGP11_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG … #define mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP11_CU1_TATD_CTRL_REG … #define mmCGTS_SA1_WGP11_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG … #define mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP12_CU0_TATD_CTRL_REG … #define mmCGTS_SA0_WGP12_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG … #define mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP12_CU1_TATD_CTRL_REG … #define mmCGTS_SA0_WGP12_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG … #define mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP12_CU0_TATD_CTRL_REG … #define mmCGTS_SA1_WGP12_CU0_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG … #define mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG … #define mmCGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG … #define mmCGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP12_CU1_TATD_CTRL_REG … #define mmCGTS_SA1_WGP12_CU1_TATD_CTRL_REG_BASE_IDX … #define mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG … #define mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG_BASE_IDX … #define mmCGTT_SPI_PS_CLK_CTRL … #define mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX … #define mmCGTT_SPIS_CLK_CTRL … #define mmCGTT_SPIS_CLK_CTRL_BASE_IDX … #define mmCGTT_SPI_CLK_CTRL … #define mmCGTT_SPI_CLK_CTRL_BASE_IDX … #define mmCGTT_PC_CLK_CTRL … #define mmCGTT_PC_CLK_CTRL_BASE_IDX … #define mmCGTT_BCI_CLK_CTRL … #define mmCGTT_BCI_CLK_CTRL_BASE_IDX … #define mmCGTT_VGT_CLK_CTRL … #define mmCGTT_VGT_CLK_CTRL_BASE_IDX … #define mmCGTT_IA_CLK_CTRL … #define mmCGTT_IA_CLK_CTRL_BASE_IDX … #define mmCGTT_WD_CLK_CTRL … #define mmCGTT_WD_CLK_CTRL_BASE_IDX … #define mmCGTT_GS_NGG_CLK_CTRL … #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX … #define mmCGTT_PA_CLK_CTRL … #define mmCGTT_PA_CLK_CTRL_BASE_IDX … #define mmCGTT_SC_CLK_CTRL0 … #define mmCGTT_SC_CLK_CTRL0_BASE_IDX … #define mmCGTT_SC_CLK_CTRL1 … #define mmCGTT_SC_CLK_CTRL1_BASE_IDX … #define mmCGTT_SC_CLK_CTRL2 … #define mmCGTT_SC_CLK_CTRL2_BASE_IDX … #define mmCGTT_SQ_CLK_CTRL … #define mmCGTT_SQ_CLK_CTRL_BASE_IDX … #define mmCGTT_SQG_CLK_CTRL … #define mmCGTT_SQG_CLK_CTRL_BASE_IDX … #define mmSQ_ALU_CLK_CTRL … #define mmSQ_ALU_CLK_CTRL_BASE_IDX … #define mmSQ_TEX_CLK_CTRL … #define mmSQ_TEX_CLK_CTRL_BASE_IDX … #define mmSQ_LDS_CLK_CTRL … #define mmSQ_LDS_CLK_CTRL_BASE_IDX … #define mmCGTT_SX_CLK_CTRL0 … #define mmCGTT_SX_CLK_CTRL0_BASE_IDX … #define mmCGTT_SX_CLK_CTRL1 … #define mmCGTT_SX_CLK_CTRL1_BASE_IDX … #define mmCGTT_SX_CLK_CTRL2 … #define mmCGTT_SX_CLK_CTRL2_BASE_IDX … #define mmCGTT_SX_CLK_CTRL3 … #define mmCGTT_SX_CLK_CTRL3_BASE_IDX … #define mmCGTT_SX_CLK_CTRL4 … #define mmCGTT_SX_CLK_CTRL4_BASE_IDX … #define mmTD_CGTT_CTRL … #define mmTD_CGTT_CTRL_BASE_IDX … #define mmTA_CGTT_CTRL … #define mmTA_CGTT_CTRL_BASE_IDX … #define mmCGTT_TCPI_CLK_CTRL … #define mmCGTT_TCPI_CLK_CTRL_BASE_IDX … #define mmCGTT_TCI_CLK_CTRL … #define mmCGTT_TCI_CLK_CTRL_BASE_IDX … #define mmCGTT_GDS_CLK_CTRL … #define mmCGTT_GDS_CLK_CTRL_BASE_IDX … #define mmDB_CGTT_CLK_CTRL_0 … #define mmDB_CGTT_CLK_CTRL_0_BASE_IDX … #define mmCB_CGTT_SCLK_CTRL … #define mmCB_CGTT_SCLK_CTRL_BASE_IDX … #define mmGL2C_CGTT_SCLK_CTRL … #define mmGL2C_CGTT_SCLK_CTRL_BASE_IDX … #define mmGL2A_CGTT_SCLK_CTRL … #define mmGL2A_CGTT_SCLK_CTRL_BASE_IDX … #define mmGL2A_CGTT_SCLK_CTRL_1 … #define mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX … #define mmCGTT_CP_CLK_CTRL … #define mmCGTT_CP_CLK_CTRL_BASE_IDX … #define mmCGTT_CPF_CLK_CTRL … #define mmCGTT_CPF_CLK_CTRL_BASE_IDX … #define mmCGTT_CPC_CLK_CTRL … #define mmCGTT_CPC_CLK_CTRL_BASE_IDX … #define mmCGTT_RLC_CLK_CTRL … #define mmCGTT_RLC_CLK_CTRL_BASE_IDX … #define mmRLC_GFX_RM_CNTL … #define mmRLC_GFX_RM_CNTL_BASE_IDX … #define mmRMI_CGTT_SCLK_CTRL … #define mmRMI_CGTT_SCLK_CTRL_BASE_IDX … #define mmCGTT_TCPF_CLK_CTRL … #define mmCGTT_TCPF_CLK_CTRL_BASE_IDX … #define mmGCR_CGTT_SCLK_CTRL … #define mmGCR_CGTT_SCLK_CTRL_BASE_IDX … #define mmUTCL1_CGTT_CLK_CTRL … #define mmUTCL1_CGTT_CLK_CTRL_BASE_IDX … #define mmGCEA_CGTT_CLK_CTRL … #define mmGCEA_CGTT_CLK_CTRL_BASE_IDX … #define mmSE_CAC_CGTT_CLK_CTRL … #define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX … #define mmGC_CAC_CGTT_CLK_CTRL … #define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX … #define mmGRBM_CGTT_CLK_CNTL … #define mmGRBM_CGTT_CLK_CNTL_BASE_IDX … #define mmCGTT_GL1C_CLK_CTRL … #define mmCGTT_GL1C_CLK_CTRL_BASE_IDX … #define mmCGTT_CHC_CLK_CTRL … #define mmCGTT_CHC_CLK_CTRL_BASE_IDX … #define mmCGTT_CHCG_CLK_CTRL … #define mmCGTT_CHCG_CLK_CTRL_BASE_IDX … #define mmCGTT_GL1A_CLK_CTRL … #define mmCGTT_GL1A_CLK_CTRL_BASE_IDX … #define mmCGTT_CHA_CLK_CTRL … #define mmCGTT_CHA_CLK_CTRL_BASE_IDX … #define mmGUS_CGTT_CLK_CTRL … #define mmGUS_CGTT_CLK_CTRL_BASE_IDX … #define mmCGTT_PH_CLK_CTRL0 … #define mmCGTT_PH_CLK_CTRL0_BASE_IDX … #define mmCGTT_PH_CLK_CTRL1 … #define mmCGTT_PH_CLK_CTRL1_BASE_IDX … #define mmCGTT_PH_CLK_CTRL2 … #define mmCGTT_PH_CLK_CTRL2_BASE_IDX … #define mmCGTT_PH_CLK_CTRL3 … #define mmCGTT_PH_CLK_CTRL3_BASE_IDX … // addressBlock: gc_hypdec // base address: 0x3e000 #define mmCP_PFP_UCODE_ADDR … #define mmCP_PFP_UCODE_ADDR_BASE_IDX … #define mmCP_PFP_UCODE_DATA … #define mmCP_PFP_UCODE_DATA_BASE_IDX … #define mmCP_ME_RAM_RADDR … #define mmCP_ME_RAM_RADDR_BASE_IDX … #define mmCP_ME_RAM_WADDR … #define mmCP_ME_RAM_WADDR_BASE_IDX … #define mmCP_ME_RAM_DATA … #define mmCP_ME_RAM_DATA_BASE_IDX … #define mmCP_CE_UCODE_ADDR … #define mmCP_CE_UCODE_ADDR_BASE_IDX … #define mmCP_CE_UCODE_DATA … #define mmCP_CE_UCODE_DATA_BASE_IDX … #define mmCP_MEC_ME1_UCODE_ADDR … #define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX … #define mmCP_MEC_ME1_UCODE_DATA … #define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX … #define mmCP_MEC_ME2_UCODE_ADDR … #define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX … #define mmCP_MEC_ME2_UCODE_DATA … #define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX … #define mmCP_PFP_IC_BASE_LO … #define mmCP_PFP_IC_BASE_LO_BASE_IDX … #define mmCP_PFP_IC_BASE_HI … #define mmCP_PFP_IC_BASE_HI_BASE_IDX … #define mmCP_PFP_IC_BASE_CNTL … #define mmCP_PFP_IC_BASE_CNTL_BASE_IDX … #define mmCP_PFP_IC_OP_CNTL … #define mmCP_PFP_IC_OP_CNTL_BASE_IDX … #define mmCP_ME_IC_BASE_LO … #define mmCP_ME_IC_BASE_LO_BASE_IDX … #define mmCP_ME_IC_BASE_HI … #define mmCP_ME_IC_BASE_HI_BASE_IDX … #define mmCP_ME_IC_BASE_CNTL … #define mmCP_ME_IC_BASE_CNTL_BASE_IDX … #define mmCP_ME_IC_OP_CNTL … #define mmCP_ME_IC_OP_CNTL_BASE_IDX … #define mmCP_CE_IC_BASE_LO … #define mmCP_CE_IC_BASE_LO_BASE_IDX … #define mmCP_CE_IC_BASE_HI … #define mmCP_CE_IC_BASE_HI_BASE_IDX … #define mmCP_CE_IC_BASE_CNTL … #define mmCP_CE_IC_BASE_CNTL_BASE_IDX … #define mmCP_CE_IC_OP_CNTL … #define mmCP_CE_IC_OP_CNTL_BASE_IDX … #define mmCP_CPC_IC_BASE_LO … #define mmCP_CPC_IC_BASE_LO_BASE_IDX … #define mmCP_CPC_IC_BASE_HI … #define mmCP_CPC_IC_BASE_HI_BASE_IDX … #define mmCP_CPC_IC_BASE_CNTL … #define mmCP_CPC_IC_BASE_CNTL_BASE_IDX … #define mmCP_CPC_IC_OP_CNTL … #define mmCP_CPC_IC_OP_CNTL_BASE_IDX … #define mmCP_MES_IC_BASE_LO … #define mmCP_MES_IC_BASE_LO_BASE_IDX … #define mmCP_MES_MIBASE_LO … #define mmCP_MES_MIBASE_LO_BASE_IDX … #define mmCP_MES_IC_BASE_HI … #define mmCP_MES_IC_BASE_HI_BASE_IDX … #define mmCP_MES_MIBASE_HI … #define mmCP_MES_MIBASE_HI_BASE_IDX … #define mmCP_MES_IC_BASE_CNTL … #define mmCP_MES_IC_BASE_CNTL_BASE_IDX … #define mmCP_MES_IC_OP_CNTL … #define mmCP_MES_IC_OP_CNTL_BASE_IDX … #define mmCP_MES_DC_BASE_LO … #define mmCP_MES_DC_BASE_LO_BASE_IDX … #define mmCP_MES_MDBASE_LO … #define mmCP_MES_MDBASE_LO_BASE_IDX … #define mmCP_MES_DC_BASE_HI … #define mmCP_MES_DC_BASE_HI_BASE_IDX … #define mmCP_MES_MDBASE_HI … #define mmCP_MES_MDBASE_HI_BASE_IDX … #define mmCP_MES_LOCAL_BASE0_LO … #define mmCP_MES_LOCAL_BASE0_LO_BASE_IDX … #define mmCP_MES_LOCAL_BASE0_HI … #define mmCP_MES_LOCAL_BASE0_HI_BASE_IDX … #define mmCP_MES_LOCAL_MASK0_LO … #define mmCP_MES_LOCAL_MASK0_LO_BASE_IDX … #define mmCP_MES_LOCAL_MASK0_HI … #define mmCP_MES_LOCAL_MASK0_HI_BASE_IDX … #define mmCP_MES_LOCAL_APERTURE … #define mmCP_MES_LOCAL_APERTURE_BASE_IDX … #define mmCP_MES_MIBOUND_LO … #define mmCP_MES_MIBOUND_LO_BASE_IDX … #define mmCP_MES_MIBOUND_HI … #define mmCP_MES_MIBOUND_HI_BASE_IDX … #define mmCP_MES_MDBOUND_LO … #define mmCP_MES_MDBOUND_LO_BASE_IDX … #define mmCP_MES_MDBOUND_HI … #define mmCP_MES_MDBOUND_HI_BASE_IDX … #define mmGFX_PIPE_PRIORITY … #define mmGFX_PIPE_PRIORITY_BASE_IDX … #define mmGRBM_GFX_INDEX_SR_SELECT … #define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX … #define mmGRBM_GFX_INDEX_SR_DATA … #define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX … #define mmGRBM_GFX_CNTL_SR_SELECT … #define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX … #define mmGRBM_GFX_CNTL_SR_DATA … #define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX … #define mmGRBM_CAM_INDEX … #define mmGRBM_CAM_INDEX_BASE_IDX … #define mmGRBM_HYP_CAM_INDEX … #define mmGRBM_HYP_CAM_INDEX_BASE_IDX … #define mmGRBM_CAM_DATA … #define mmGRBM_CAM_DATA_BASE_IDX … #define mmGRBM_HYP_CAM_DATA … #define mmGRBM_HYP_CAM_DATA_BASE_IDX … #define mmGRBM_CAM_DATA_UPPER … #define mmGRBM_CAM_DATA_UPPER_BASE_IDX … #define mmGRBM_HYP_CAM_DATA_UPPER … #define mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX … #define mmGC_IH_COOKIE_0_PTR … #define mmGC_IH_COOKIE_0_PTR_BASE_IDX … #define mmRLC_GPU_IOV_VF_ENABLE … #define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX … #define mmRLC_GPU_IOV_CFG_REG6 … #define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX … #define mmRLC_GPU_IOV_CFG_REG8 … #define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX … #define mmRLC_RLCV_TIMER_INT_0 … #define mmRLC_RLCV_TIMER_INT_0_BASE_IDX … #define mmRLC_RLCV_TIMER_CTRL … #define mmRLC_RLCV_TIMER_CTRL_BASE_IDX … #define mmRLC_RLCV_TIMER_STAT … #define mmRLC_RLCV_TIMER_STAT_BASE_IDX … #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS … #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX … #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET … #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX … #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR … #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX … #define mmRLC_GPU_IOV_VF_MASK … #define mmRLC_GPU_IOV_VF_MASK_BASE_IDX … #define mmRLC_HYP_SEMAPHORE_0 … #define mmRLC_HYP_SEMAPHORE_0_BASE_IDX … #define mmRLC_HYP_SEMAPHORE_1 … #define mmRLC_HYP_SEMAPHORE_1_BASE_IDX … #define mmRLC_BUSY_CLK_CNTL … #define mmRLC_BUSY_CLK_CNTL_BASE_IDX … #define mmRLC_CLK_CNTL … #define mmRLC_CLK_CNTL_BASE_IDX … #define mmRLC_PACE_TIMER_STAT … #define mmRLC_PACE_TIMER_STAT_BASE_IDX … #define mmRLC_GPU_IOV_SCH_BLOCK … #define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX … #define mmRLC_GPU_IOV_CFG_REG1 … #define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX … #define mmRLC_GPU_IOV_CFG_REG2 … #define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX … #define mmRLC_GPU_IOV_VM_BUSY_STATUS … #define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX … #define mmRLC_GPU_IOV_SCH_0 … #define mmRLC_GPU_IOV_SCH_0_BASE_IDX … #define mmRLC_GPU_IOV_ACTIVE_FCN_ID … #define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX … #define mmRLC_GPU_IOV_SCH_3 … #define mmRLC_GPU_IOV_SCH_3_BASE_IDX … #define mmRLC_GPU_IOV_SCH_1 … #define mmRLC_GPU_IOV_SCH_1_BASE_IDX … #define mmRLC_GPU_IOV_SCH_2 … #define mmRLC_GPU_IOV_SCH_2_BASE_IDX … #define mmRLC_PACE_INT_FORCE … #define mmRLC_PACE_INT_FORCE_BASE_IDX … #define mmRLC_GPU_IOV_INT_STAT … #define mmRLC_GPU_IOV_INT_STAT_BASE_IDX … #define mmRLC_RLCV_TIMER_INT_1 … #define mmRLC_RLCV_TIMER_INT_1_BASE_IDX … #define mmRLC_IH_COOKIE … #define mmRLC_IH_COOKIE_BASE_IDX … #define mmRLC_IH_COOKIE_CNTL … #define mmRLC_IH_COOKIE_CNTL_BASE_IDX … #define mmRLC_HYP_RLCG_UCODE_CHKSUM … #define mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX … #define mmRLC_HYP_RLCP_UCODE_CHKSUM … #define mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX … #define mmRLC_HYP_RLCV_UCODE_CHKSUM … #define mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX … #define mmRLC_GPU_IOV_F32_CNTL … #define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX … #define mmRLC_GPU_IOV_F32_RESET … #define mmRLC_GPU_IOV_F32_RESET_BASE_IDX … #define mmRLC_GPU_IOV_SDMA0_STATUS … #define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX … #define mmRLC_GPU_IOV_SDMA1_STATUS … #define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX … #define mmRLC_GPU_IOV_SMU_RESPONSE … #define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX … #define mmRLC_GPU_IOV_VIRT_RESET_REQ … #define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX … #define mmRLC_GPU_IOV_RLC_RESPONSE … #define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX … #define mmRLC_GPU_IOV_INT_DISABLE … #define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX … #define mmRLC_GPU_IOV_INT_FORCE … #define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX … #define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS … #define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX … #define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS … #define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX … #define mmRLC_HYP_SEMAPHORE_2 … #define mmRLC_HYP_SEMAPHORE_2_BASE_IDX … #define mmRLC_HYP_SEMAPHORE_3 … #define mmRLC_HYP_SEMAPHORE_3_BASE_IDX … #define mmRLC_HYP_RESET_VECTOR … #define mmRLC_HYP_RESET_VECTOR_BASE_IDX … #define mmRLC_HYP_BOOTLOAD_SIZE … #define mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX … #define mmRLC_HYP_BOOTLOAD_ADDR_LO … #define mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX … #define mmRLC_HYP_BOOTLOAD_ADDR_HI … #define mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX … #define mmRLC_GPM_IRAM_ADDR … #define mmRLC_GPM_IRAM_ADDR_BASE_IDX … #define mmRLC_GPM_IRAM_DATA … #define mmRLC_GPM_IRAM_DATA_BASE_IDX … #define mmRLC_GPM_UCODE_ADDR … #define mmRLC_GPM_UCODE_ADDR_BASE_IDX … #define mmRLC_GPM_UCODE_DATA … #define mmRLC_GPM_UCODE_DATA_BASE_IDX … #define mmRLC_PACE_UCODE_ADDR … #define mmRLC_PACE_UCODE_ADDR_BASE_IDX … #define mmRLC_PACE_UCODE_DATA … #define mmRLC_PACE_UCODE_DATA_BASE_IDX … #define mmRLC_GPU_IOV_UCODE_ADDR … #define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX … #define mmRLC_GPU_IOV_UCODE_DATA … #define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX … #define mmRLC_GPU_IOV_SCRATCH_ADDR … #define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX … #define mmRLC_GPU_IOV_SCRATCH_DATA … #define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX … #define mmRLC_RLCV_IRAM_ADDR … #define mmRLC_RLCV_IRAM_ADDR_BASE_IDX … #define mmRLC_RLCV_IRAM_DATA … #define mmRLC_RLCV_IRAM_DATA_BASE_IDX … #define mmRLC_RLCP_IRAM_ADDR … #define mmRLC_RLCP_IRAM_ADDR_BASE_IDX … #define mmRLC_RLCP_IRAM_DATA … #define mmRLC_RLCP_IRAM_DATA_BASE_IDX … #define mmRLC_SRM_DRAM_ADDR … #define mmRLC_SRM_DRAM_ADDR_BASE_IDX … #define mmRLC_SRM_DRAM_DATA … #define mmRLC_SRM_DRAM_DATA_BASE_IDX … #define mmRLC_SRM_ARAM_ADDR … #define mmRLC_SRM_ARAM_ADDR_BASE_IDX … #define mmRLC_SRM_ARAM_DATA … #define mmRLC_SRM_ARAM_DATA_BASE_IDX … #define mmRLC_GPM_SCRATCH_ADDR … #define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX … #define mmRLC_GPM_SCRATCH_DATA … #define mmRLC_GPM_SCRATCH_DATA_BASE_IDX … #define mmRLC_GTS_OFFSET_LSB … #define mmRLC_GTS_OFFSET_LSB_BASE_IDX … #define mmRLC_GTS_OFFSET_MSB … #define mmRLC_GTS_OFFSET_MSB_BASE_IDX … // addressBlock: gc_sdma0_sdma0hypdec // base address: 0x3e200 #define mmSDMA0_UCODE_ADDR … #define mmSDMA0_UCODE_ADDR_BASE_IDX … #define mmSDMA0_UCODE_DATA … #define mmSDMA0_UCODE_DATA_BASE_IDX … #define mmSDMA0_VM_CTX_LO … #define mmSDMA0_VM_CTX_LO_BASE_IDX … #define mmSDMA0_VM_CTX_HI … #define mmSDMA0_VM_CTX_HI_BASE_IDX … #define mmSDMA0_ACTIVE_FCN_ID … #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX … #define mmSDMA0_VM_CTX_CNTL … #define mmSDMA0_VM_CTX_CNTL_BASE_IDX … #define mmSDMA0_VIRT_RESET_REQ … #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX … #define mmSDMA0_VF_ENABLE … #define mmSDMA0_VF_ENABLE_BASE_IDX … #define mmSDMA0_CONTEXT_REG_TYPE0 … #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX … #define mmSDMA0_CONTEXT_REG_TYPE1 … #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX … #define mmSDMA0_CONTEXT_REG_TYPE2 … #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX … #define mmSDMA0_CONTEXT_REG_TYPE3 … #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX … #define mmSDMA0_VM_CNTL … #define mmSDMA0_VM_CNTL_BASE_IDX … // addressBlock: gc_sdma1_sdma1hypdec // base address: 0x3e280 #define mmSDMA1_UCODE_ADDR … #define mmSDMA1_UCODE_ADDR_BASE_IDX … #define mmSDMA1_UCODE_DATA … #define mmSDMA1_UCODE_DATA_BASE_IDX … #define mmSDMA1_VM_CTX_LO … #define mmSDMA1_VM_CTX_LO_BASE_IDX … #define mmSDMA1_VM_CTX_HI … #define mmSDMA1_VM_CTX_HI_BASE_IDX … #define mmSDMA1_ACTIVE_FCN_ID … #define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX … #define mmSDMA1_VM_CTX_CNTL … #define mmSDMA1_VM_CTX_CNTL_BASE_IDX … #define mmSDMA1_VIRT_RESET_REQ … #define mmSDMA1_VIRT_RESET_REQ_BASE_IDX … #define mmSDMA1_VF_ENABLE … #define mmSDMA1_VF_ENABLE_BASE_IDX … #define mmSDMA1_CONTEXT_REG_TYPE0 … #define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX … #define mmSDMA1_CONTEXT_REG_TYPE1 … #define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX … #define mmSDMA1_CONTEXT_REG_TYPE2 … #define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX … #define mmSDMA1_CONTEXT_REG_TYPE3 … #define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX … #define mmSDMA1_VM_CNTL … #define mmSDMA1_VM_CNTL_BASE_IDX … // addressBlock: gc_gcvmsharedhvdec // base address: 0x3ea00 #define mmGCMC_VM_FB_SIZE_OFFSET_VF0 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF1 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF2 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF3 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF4 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF5 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF6 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF7 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF8 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF9 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF10 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF11 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF12 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF13 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF14 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF15 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF16 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF17 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF18 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF19 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF20 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF21 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF22 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF23 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF24 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF25 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF26 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF27 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF28 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF29 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF30 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX … #define mmGCMC_VM_FB_SIZE_OFFSET_VF31 … #define mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX … #define mmGCVM_IOMMU_MMIO_CNTRL_1 … #define mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX … #define mmGCMC_VM_MARC_BASE_LO_0 … #define mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX … #define mmGCMC_VM_MARC_BASE_LO_1 … #define mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX … #define mmGCMC_VM_MARC_BASE_LO_2 … #define mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX … #define mmGCMC_VM_MARC_BASE_LO_3 … #define mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX … #define mmGCMC_VM_MARC_BASE_HI_0 … #define mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX … #define mmGCMC_VM_MARC_BASE_HI_1 … #define mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX … #define mmGCMC_VM_MARC_BASE_HI_2 … #define mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX … #define mmGCMC_VM_MARC_BASE_HI_3 … #define mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX … #define mmGCMC_VM_MARC_RELOC_LO_0 … #define mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX … #define mmGCMC_VM_MARC_RELOC_LO_1 … #define mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX … #define mmGCMC_VM_MARC_RELOC_LO_2 … #define mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX … #define mmGCMC_VM_MARC_RELOC_LO_3 … #define mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX … #define mmGCMC_VM_MARC_RELOC_HI_0 … #define mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX … #define mmGCMC_VM_MARC_RELOC_HI_1 … #define mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX … #define mmGCMC_VM_MARC_RELOC_HI_2 … #define mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX … #define mmGCMC_VM_MARC_RELOC_HI_3 … #define mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX … #define mmGCMC_VM_MARC_LEN_LO_0 … #define mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX … #define mmGCMC_VM_MARC_LEN_LO_1 … #define mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX … #define mmGCMC_VM_MARC_LEN_LO_2 … #define mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX … #define mmGCMC_VM_MARC_LEN_LO_3 … #define mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX … #define mmGCMC_VM_MARC_LEN_HI_0 … #define mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX … #define mmGCMC_VM_MARC_LEN_HI_1 … #define mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX … #define mmGCMC_VM_MARC_LEN_HI_2 … #define mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX … #define mmGCMC_VM_MARC_LEN_HI_3 … #define mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX … #define mmGCVM_IOMMU_CONTROL_REGISTER … #define mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL … #define mmGCVM_PCIE_ATS_CNTL_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_0 … #define mmGCVM_PCIE_ATS_CNTL_VF_0_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_1 … #define mmGCVM_PCIE_ATS_CNTL_VF_1_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_2 … #define mmGCVM_PCIE_ATS_CNTL_VF_2_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_3 … #define mmGCVM_PCIE_ATS_CNTL_VF_3_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_4 … #define mmGCVM_PCIE_ATS_CNTL_VF_4_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_5 … #define mmGCVM_PCIE_ATS_CNTL_VF_5_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_6 … #define mmGCVM_PCIE_ATS_CNTL_VF_6_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_7 … #define mmGCVM_PCIE_ATS_CNTL_VF_7_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_8 … #define mmGCVM_PCIE_ATS_CNTL_VF_8_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_9 … #define mmGCVM_PCIE_ATS_CNTL_VF_9_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_10 … #define mmGCVM_PCIE_ATS_CNTL_VF_10_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_11 … #define mmGCVM_PCIE_ATS_CNTL_VF_11_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_12 … #define mmGCVM_PCIE_ATS_CNTL_VF_12_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_13 … #define mmGCVM_PCIE_ATS_CNTL_VF_13_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_14 … #define mmGCVM_PCIE_ATS_CNTL_VF_14_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_15 … #define mmGCVM_PCIE_ATS_CNTL_VF_15_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_16 … #define mmGCVM_PCIE_ATS_CNTL_VF_16_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_17 … #define mmGCVM_PCIE_ATS_CNTL_VF_17_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_18 … #define mmGCVM_PCIE_ATS_CNTL_VF_18_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_19 … #define mmGCVM_PCIE_ATS_CNTL_VF_19_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_20 … #define mmGCVM_PCIE_ATS_CNTL_VF_20_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_21 … #define mmGCVM_PCIE_ATS_CNTL_VF_21_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_22 … #define mmGCVM_PCIE_ATS_CNTL_VF_22_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_23 … #define mmGCVM_PCIE_ATS_CNTL_VF_23_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_24 … #define mmGCVM_PCIE_ATS_CNTL_VF_24_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_25 … #define mmGCVM_PCIE_ATS_CNTL_VF_25_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_26 … #define mmGCVM_PCIE_ATS_CNTL_VF_26_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_27 … #define mmGCVM_PCIE_ATS_CNTL_VF_27_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_28 … #define mmGCVM_PCIE_ATS_CNTL_VF_28_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_29 … #define mmGCVM_PCIE_ATS_CNTL_VF_29_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_30 … #define mmGCVM_PCIE_ATS_CNTL_VF_30_BASE_IDX … #define mmGCVM_PCIE_ATS_CNTL_VF_31 … #define mmGCVM_PCIE_ATS_CNTL_VF_31_BASE_IDX … #define mmGCUTCL2_CGTT_CLK_CTRL … #define mmGCUTCL2_CGTT_CLK_CTRL_BASE_IDX … #define mmGCMC_SHARED_ACTIVE_FCN_ID … #define mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX … // addressBlock: gccacind // base address: 0x0 #define ixPCC_STALL_PATTERN_CTRL … #define ixPWRBRK_STALL_PATTERN_CTRL … #define ixPCC_STALL_PATTERN_1_2 … #define ixPCC_STALL_PATTERN_3_4 … #define ixPCC_STALL_PATTERN_5_6 … #define ixPCC_STALL_PATTERN_7 … #define ixPWRBRK_STALL_PATTERN_1_2 … #define ixPWRBRK_STALL_PATTERN_3_4 … #define ixPWRBRK_STALL_PATTERN_5_6 … #define ixPWRBRK_STALL_PATTERN_7 … #define ixGC_CAC_ID … #define ixGC_CAC_CNTL … #define ixGC_CAC_OVR_SEL … #define ixGC_CAC_OVR_VAL … #define ixGC_CAC_WEIGHT_BCI_0 … #define ixGC_CAC_WEIGHT_CB_0 … #define ixGC_CAC_WEIGHT_CB_1 … #define ixGC_CAC_WEIGHT_CBR_0 … #define ixGC_CAC_WEIGHT_CBR_1 … #define ixGC_CAC_WEIGHT_CP_0 … #define ixGC_CAC_WEIGHT_CP_1 … #define ixGC_CAC_WEIGHT_DB_0 … #define ixGC_CAC_WEIGHT_DB_1 … #define ixGC_CAC_WEIGHT_DBR_0 … #define ixGC_CAC_WEIGHT_DBR_1 … #define ixGC_CAC_WEIGHT_GDS_0 … #define ixGC_CAC_WEIGHT_GDS_1 … #define ixGC_CAC_WEIGHT_LDS_0 … #define ixGC_CAC_WEIGHT_LDS_1 … #define ixGC_CAC_WEIGHT_PA_0 … #define ixGC_CAC_WEIGHT_PC_0 … #define ixGC_CAC_WEIGHT_SC_0 … #define ixGC_CAC_WEIGHT_SPI_0 … #define ixGC_CAC_WEIGHT_SPI_1 … #define ixGC_CAC_WEIGHT_SPI_2 … #define ixGC_CAC_WEIGHT_SQ_0 … #define ixGC_CAC_WEIGHT_SQ_1 … #define ixGC_CAC_WEIGHT_SQ_2 … #define ixGC_CAC_WEIGHT_SX_0 … #define ixGC_CAC_WEIGHT_SXRB_0 … #define ixGC_CAC_WEIGHT_TA_0 … #define ixGC_CAC_WEIGHT_TCP_0 … #define ixGC_CAC_WEIGHT_TCP_1 … #define ixGC_CAC_WEIGHT_TCP_2 … #define ixGC_CAC_WEIGHT_TD_0 … #define ixGC_CAC_WEIGHT_TD_1 … #define ixGC_CAC_WEIGHT_TD_2 … #define ixGC_CAC_WEIGHT_TD_3 … #define ixGC_CAC_WEIGHT_TD_4 … #define ixGC_CAC_WEIGHT_RMI_0 … #define ixGC_CAC_WEIGHT_EA_0 … #define ixGC_CAC_WEIGHT_EA_1 … #define ixGC_CAC_WEIGHT_EA_2 … #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 … #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 … #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 … #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 … #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 … #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 … #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 … #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 … #define ixGC_CAC_WEIGHT_UTCL2_VML2_0 … #define ixGC_CAC_WEIGHT_UTCL2_VML2_1 … #define ixGC_CAC_WEIGHT_UTCL2_VML2_2 … #define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 … #define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 … #define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 … #define ixGC_CAC_WEIGHT_CU_0 … #define ixGC_CAC_WEIGHT_UTCL1_0 … #define ixGC_CAC_WEIGHT_GE_0 … #define ixGC_CAC_WEIGHT_PMM_0 … #define ixGC_CAC_WEIGHT_GL2C_0 … #define ixGC_CAC_WEIGHT_GL2C_1 … #define ixGC_CAC_WEIGHT_GL2C_2 … #define ixGC_CAC_WEIGHT_GUS_0 … #define ixGC_CAC_WEIGHT_GUS_1 … #define ixGC_CAC_WEIGHT_PH_0 … #define ixGC_CAC_ACC_BCI0 … #define ixGC_CAC_ACC_BCI1 … #define ixGC_CAC_ACC_CB0 … #define ixGC_CAC_ACC_CB1 … #define ixGC_CAC_ACC_CB2 … #define ixGC_CAC_ACC_CB3 … #define ixGC_CAC_ACC_CBR0 … #define ixGC_CAC_ACC_CBR1 … #define ixGC_CAC_ACC_CBR2 … #define ixGC_CAC_ACC_CBR3 … #define ixGC_CAC_ACC_CP0 … #define ixGC_CAC_ACC_CP1 … #define ixGC_CAC_ACC_CP2 … #define ixGC_CAC_ACC_DB0 … #define ixGC_CAC_ACC_DB1 … #define ixGC_CAC_ACC_DB2 … #define ixGC_CAC_ACC_DB3 … #define ixGC_CAC_ACC_DBR0 … #define ixGC_CAC_ACC_DBR1 … #define ixGC_CAC_ACC_DBR2 … #define ixGC_CAC_ACC_DBR3 … #define ixGC_CAC_ACC_GDS0 … #define ixGC_CAC_ACC_GDS1 … #define ixGC_CAC_ACC_GDS2 … #define ixGC_CAC_ACC_GDS3 … #define ixGC_CAC_ACC_LDS0 … #define ixGC_CAC_ACC_LDS1 … #define ixGC_CAC_ACC_LDS2 … #define ixGC_CAC_ACC_LDS3 … #define ixGC_CAC_ACC_PA0 … #define ixGC_CAC_ACC_PA1 … #define ixGC_CAC_ACC_PC0 … #define ixGC_CAC_ACC_SC0 … #define ixGC_CAC_ACC_SPI0 … #define ixGC_CAC_ACC_SPI1 … #define ixGC_CAC_ACC_SPI2 … #define ixGC_CAC_ACC_SPI3 … #define ixGC_CAC_ACC_SPI4 … #define ixGC_CAC_ACC_SPI5 … #define ixGC_CAC_ACC_SQ0_LOWER … #define ixGC_CAC_ACC_SQ0_UPPER … #define ixGC_CAC_ACC_SQ1_LOWER … #define ixGC_CAC_ACC_SQ1_UPPER … #define ixGC_CAC_ACC_SQ2_LOWER … #define ixGC_CAC_ACC_SQ2_UPPER … #define ixGC_CAC_ACC_SQ3_LOWER … #define ixGC_CAC_ACC_SQ3_UPPER … #define ixGC_CAC_ACC_SQ4_LOWER … #define ixGC_CAC_ACC_SQ4_UPPER … #define ixGC_CAC_ACC_SQ5_LOWER … #define ixGC_CAC_ACC_SQ5_UPPER … #define ixGC_CAC_ACC_SQ6_LOWER … #define ixGC_CAC_ACC_SQ6_UPPER … #define ixGC_CAC_ACC_SQ7_LOWER … #define ixGC_CAC_ACC_SQ7_UPPER … #define ixGC_CAC_ACC_SQ8_LOWER … #define ixGC_CAC_ACC_SQ8_UPPER … #define ixGC_CAC_ACC_SX0 … #define ixGC_CAC_ACC_SXRB0 … #define ixGC_CAC_ACC_TA0 … #define ixGC_CAC_ACC_TCP0 … #define ixGC_CAC_ACC_TCP1 … #define ixGC_CAC_ACC_TCP2 … #define ixGC_CAC_ACC_TCP3 … #define ixGC_CAC_ACC_TCP4 … #define ixGC_CAC_ACC_TD0 … #define ixGC_CAC_ACC_TD1 … #define ixGC_CAC_ACC_TD2 … #define ixGC_CAC_ACC_TD3 … #define ixGC_CAC_ACC_TD4 … #define ixGC_CAC_ACC_TD5 … #define ixGC_CAC_ACC_TD6 … #define ixGC_CAC_ACC_TD7 … #define ixGC_CAC_ACC_TD8 … #define ixGC_CAC_ACC_TD9 … #define ixGC_CAC_ACC_RMI0 … #define ixGC_CAC_ACC_EA0 … #define ixGC_CAC_ACC_EA1 … #define ixGC_CAC_ACC_EA2 … #define ixGC_CAC_ACC_EA3 … #define ixGC_CAC_ACC_EA4 … #define ixGC_CAC_ACC_EA5 … #define ixGC_CAC_ACC_UTCL2_ATCL20 … #define ixGC_CAC_ACC_UTCL2_ATCL21 … #define ixGC_CAC_ACC_UTCL2_ATCL22 … #define ixGC_CAC_ACC_UTCL2_ATCL23 … #define ixGC_CAC_ACC_UTCL2_ATCL24 … #define ixGC_CAC_ACC_UTCL2_ROUTER0 … #define ixGC_CAC_ACC_UTCL2_ROUTER1 … #define ixGC_CAC_ACC_UTCL2_ROUTER2 … #define ixGC_CAC_ACC_UTCL2_ROUTER3 … #define ixGC_CAC_ACC_UTCL2_ROUTER4 … #define ixGC_CAC_ACC_UTCL2_ROUTER5 … #define ixGC_CAC_ACC_UTCL2_ROUTER6 … #define ixGC_CAC_ACC_UTCL2_ROUTER7 … #define ixGC_CAC_ACC_UTCL2_ROUTER8 … #define ixGC_CAC_ACC_UTCL2_ROUTER9 … #define ixGC_CAC_ACC_UTCL2_VML20 … #define ixGC_CAC_ACC_UTCL2_VML21 … #define ixGC_CAC_ACC_UTCL2_VML22 … #define ixGC_CAC_ACC_UTCL2_VML23 … #define ixGC_CAC_ACC_UTCL2_VML24 … #define ixGC_CAC_ACC_UTCL2_WALKER0 … #define ixGC_CAC_ACC_UTCL2_WALKER1 … #define ixGC_CAC_ACC_UTCL2_WALKER2 … #define ixGC_CAC_ACC_UTCL2_WALKER3 … #define ixGC_CAC_ACC_UTCL2_WALKER4 … #define ixGC_CAC_ACC_CU0 … #define ixGC_CAC_ACC_UTCL10 … #define ixGC_CAC_ACC_CH0 … #define ixGC_CAC_ACC_GE0 … #define ixGC_CAC_ACC_PMM0 … #define ixGC_CAC_ACC_GL2C0 … #define ixGC_CAC_ACC_GL2C1 … #define ixGC_CAC_ACC_GL2C2 … #define ixGC_CAC_ACC_GL2C3 … #define ixGC_CAC_ACC_GL2C4 … #define ixGC_CAC_ACC_GUS0 … #define ixGC_CAC_ACC_GUS1 … #define ixGC_CAC_ACC_GUS2 … #define ixGC_CAC_ACC_PH0 … #define ixGC_CAC_OVRD_BCI … #define ixGC_CAC_OVRD_CB … #define ixGC_CAC_OVRD_CBR … #define ixGC_CAC_OVRD_CP … #define ixGC_CAC_OVRD_DB … #define ixGC_CAC_OVRD_DBR … #define ixGC_CAC_OVRD_GDS … #define ixGC_CAC_OVRD_LDS … #define ixGC_CAC_OVRD_PA … #define ixGC_CAC_OVRD_PC … #define ixGC_CAC_OVRD_SC … #define ixGC_CAC_OVRD_SPI … #define ixGC_CAC_OVRD_CU … #define ixGC_CAC_OVRD_SQ … #define ixGC_CAC_OVRD_SX … #define ixGC_CAC_OVRD_SXRB … #define ixGC_CAC_OVRD_TA … #define ixGC_CAC_OVRD_TCP … #define ixGC_CAC_OVRD_TD … #define ixGC_CAC_OVRD_RMI … #define ixGC_CAC_OVRD_EA … #define ixGC_CAC_OVRD_UTCL2_ATCL2 … #define ixGC_CAC_OVRD_UTCL2_ROUTER … #define ixGC_CAC_OVRD_UTCL2_VML2 … #define ixGC_CAC_OVRD_UTCL2_WALKER … #define ixGC_CAC_OVRD_UTCL1 … #define ixGC_CAC_OVRD_GE … #define ixGC_CAC_OVRD_PMM … #define ixGC_CAC_OVRD_GL2C … #define ixGC_CAC_OVRD_GUS … #define ixGC_CAC_OVRD_PH … #define ixRELEASE_TO_STALL_LUT_1_8 … #define ixRELEASE_TO_STALL_LUT_9_16 … #define ixRELEASE_TO_STALL_LUT_17_20 … #define ixSTALL_TO_RELEASE_LUT_1_4 … #define ixSTALL_TO_RELEASE_LUT_5_7 … #define ixSTALL_TO_PWRBRK_LUT_1_4 … #define ixSTALL_TO_PWRBRK_LUT_5_7 … #define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 … #define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 … #define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 … #define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 … #define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 … #define ixFIXED_PATTERN_PERF_COUNTER_1 … #define ixFIXED_PATTERN_PERF_COUNTER_2 … #define ixFIXED_PATTERN_PERF_COUNTER_3 … #define ixFIXED_PATTERN_PERF_COUNTER_4 … #define ixFIXED_PATTERN_PERF_COUNTER_5 … #define ixFIXED_PATTERN_PERF_COUNTER_6 … #define ixFIXED_PATTERN_PERF_COUNTER_7 … #define ixFIXED_PATTERN_PERF_COUNTER_8 … #define ixFIXED_PATTERN_PERF_COUNTER_9 … #define ixFIXED_PATTERN_PERF_COUNTER_10 … #define ixHW_LUT_UPDATE_STATUS … // addressBlock: secacind // base address: 0x0 #define ixSE_CAC_ID … #define ixSE_CAC_CNTL … #define ixSE_CAC_OVR_SEL … #define ixSE_CAC_OVR_VAL … // addressBlock: spmglbind // base address: 0x0 #define ixGLB_CPG_SAMPLEDELAY … #define ixGLB_CPC_SAMPLEDELAY … #define ixGLB_CPF_SAMPLEDELAY … #define ixGLB_GDS_SAMPLEDELAY … #define ixGLB_GCR_SAMPLEDELAY … #define ixGLB_PH_SAMPLEDELAY … #define ixGLB_GE_SAMPLEDELAY … #define ixGLB_GUS_SAMPLEDELAY … #define ixGLB_CHA_SAMPLEDELAY … #define ixGLB_CHCG_SAMPLEDELAY … #define ixGLB_ATCL2_SAMPLEDELAY … #define ixGLB_VML2_SAMPLEDELAY … #define ixGLB_SDMA0_SAMPLEDELAY … #define ixGLB_SDMA1_SAMPLEDELAY … #define ixGLB_GL2A0_SAMPLEDELAY … #define ixGLB_GL2A1_SAMPLEDELAY … #define ixGLB_GL2A2_SAMPLEDELAY … #define ixGLB_GL2A3_SAMPLEDELAY … #define ixGLB_GL2C0_SAMPLEDELAY … #define ixGLB_GL2C1_SAMPLEDELAY … #define ixGLB_GL2C2_SAMPLEDELAY … #define ixGLB_GL2C3_SAMPLEDELAY … #define ixGLB_GL2C4_SAMPLEDELAY … #define ixGLB_GL2C5_SAMPLEDELAY … #define ixGLB_GL2C6_SAMPLEDELAY … #define ixGLB_GL2C7_SAMPLEDELAY … #define ixGLB_GL2C8_SAMPLEDELAY … #define ixGLB_GL2C9_SAMPLEDELAY … #define ixGLB_GL2C10_SAMPLEDELAY … #define ixGLB_GL2C11_SAMPLEDELAY … #define ixGLB_GL2C12_SAMPLEDELAY … #define ixGLB_GL2C13_SAMPLEDELAY … #define ixGLB_GL2C14_SAMPLEDELAY … #define ixGLB_GL2C15_SAMPLEDELAY … #define ixGLB_EA0_SAMPLEDELAY … #define ixGLB_EA1_SAMPLEDELAY … #define ixGLB_EA2_SAMPLEDELAY … #define ixGLB_EA3_SAMPLEDELAY … #define ixGLB_EA4_SAMPLEDELAY … #define ixGLB_EA5_SAMPLEDELAY … #define ixGLB_EA6_SAMPLEDELAY … #define ixGLB_EA7_SAMPLEDELAY … #define ixGLB_EA8_SAMPLEDELAY … #define ixGLB_EA9_SAMPLEDELAY … #define ixGLB_EA10_SAMPLEDELAY … #define ixGLB_EA11_SAMPLEDELAY … #define ixGLB_EA12_SAMPLEDELAY … #define ixGLB_EA13_SAMPLEDELAY … #define ixGLB_EA14_SAMPLEDELAY … #define ixGLB_EA15_SAMPLEDELAY … #define ixGLB_CHC0_SAMPLEDELAY … #define ixGLB_CHC1_SAMPLEDELAY … #define ixGLB_CHC2_SAMPLEDELAY … #define ixGLB_CHC3_SAMPLEDELAY … // addressBlock: spmind // base address: 0x0 #define ixSE_SPI_SAMPLEDELAY … #define ixSE_SQG_SAMPLEDELAY … #define ixSE_CBR_SAMPLEDELAY … #define ixSE_DBR_SAMPLEDELAY … #define ixSE_SA0SX_SAMPLEDELAY … #define ixSE_SA0PA_SAMPLEDELAY … #define ixSE_SA0GL1A_SAMPLEDELAY … #define ixSE_SA0GL1CG_SAMPLEDELAY … #define ixSE_SA0CB0_SAMPLEDELAY … #define ixSE_SA0CB1_SAMPLEDELAY … #define ixSE_SA0CB2_SAMPLEDELAY … #define ixSE_SA0CB3_SAMPLEDELAY … #define ixSE_SA0DB0_SAMPLEDELAY … #define ixSE_SA0DB1_SAMPLEDELAY … #define ixSE_SA0DB2_SAMPLEDELAY … #define ixSE_SA0DB3_SAMPLEDELAY … #define ixSE_SA0SC0_SAMPLEDELAY … #define ixSE_SA0SC1_SAMPLEDELAY … #define ixSE_SA0RMI0_SAMPLEDELAY … #define ixSE_SA0RMI1_SAMPLEDELAY … #define ixSE_SA0GL1C0_SAMPLEDELAY … #define ixSE_SA0GL1C1_SAMPLEDELAY … #define ixSE_SA0GL1C2_SAMPLEDELAY … #define ixSE_SA0GL1C3_SAMPLEDELAY … #define ixSE_SA0WGP00TA0_SAMPLEDELAY … #define ixSE_SA0WGP00TA1_SAMPLEDELAY … #define ixSE_SA0WGP00TD0_SAMPLEDELAY … #define ixSE_SA0WGP00TD1_SAMPLEDELAY … #define ixSE_SA0WGP00TCP0_SAMPLEDELAY … #define ixSE_SA0WGP00TCP1_SAMPLEDELAY … #define ixSE_SA0WGP01TA0_SAMPLEDELAY … #define ixSE_SA0WGP01TA1_SAMPLEDELAY … #define ixSE_SA0WGP01TD0_SAMPLEDELAY … #define ixSE_SA0WGP01TD1_SAMPLEDELAY … #define ixSE_SA0WGP01TCP0_SAMPLEDELAY … #define ixSE_SA0WGP01TCP1_SAMPLEDELAY … #define ixSE_SA0WGP02TA0_SAMPLEDELAY … #define ixSE_SA0WGP02TA1_SAMPLEDELAY … #define ixSE_SA0WGP02TD0_SAMPLEDELAY … #define ixSE_SA0WGP02TD1_SAMPLEDELAY … #define ixSE_SA0WGP02TCP0_SAMPLEDELAY … #define ixSE_SA0WGP02TCP1_SAMPLEDELAY … #define ixSE_SA0WGP10TA0_SAMPLEDELAY … #define ixSE_SA0WGP10TA1_SAMPLEDELAY … #define ixSE_SA0WGP10TD0_SAMPLEDELAY … #define ixSE_SA0WGP10TD1_SAMPLEDELAY … #define ixSE_SA0WGP10TCP0_SAMPLEDELAY … #define ixSE_SA0WGP10TCP1_SAMPLEDELAY … #define ixSE_SA0WGP11TA0_SAMPLEDELAY … #define ixSE_SA0WGP11TA1_SAMPLEDELAY … #define ixSE_SA0WGP11TD0_SAMPLEDELAY … #define ixSE_SA0WGP11TD1_SAMPLEDELAY … #define ixSE_SA0WGP11TCP0_SAMPLEDELAY … #define ixSE_SA0WGP11TCP1_SAMPLEDELAY … #define ixSE_SA1SX_SAMPLEDELAY … #define ixSE_SA1PA_SAMPLEDELAY … #define ixSE_SA1GL1A_SAMPLEDELAY … #define ixSE_SA1GL1CG_SAMPLEDELAY … #define ixSE_SA1CB0_SAMPLEDELAY … #define ixSE_SA1CB1_SAMPLEDELAY … #define ixSE_SA1CB2_SAMPLEDELAY … #define ixSE_SA1CB3_SAMPLEDELAY … #define ixSE_SA1DB0_SAMPLEDELAY … #define ixSE_SA1DB1_SAMPLEDELAY … #define ixSE_SA1DB2_SAMPLEDELAY … #define ixSE_SA1DB3_SAMPLEDELAY … #define ixSE_SA1SC0_SAMPLEDELAY … #define ixSE_SA1SC1_SAMPLEDELAY … #define ixSE_SA1RMI0_SAMPLEDELAY … #define ixSE_SA1RMI1_SAMPLEDELAY … #define ixSE_SA1GL1C0_SAMPLEDELAY … #define ixSE_SA1GL1C1_SAMPLEDELAY … #define ixSE_SA1GL1C2_SAMPLEDELAY … #define ixSE_SA1GL1C3_SAMPLEDELAY … #define ixSE_SA1WGP00TA0_SAMPLEDELAY … #define ixSE_SA1WGP00TA1_SAMPLEDELAY … #define ixSE_SA1WGP00TD0_SAMPLEDELAY … #define ixSE_SA1WGP00TD1_SAMPLEDELAY … #define ixSE_SA1WGP00TCP0_SAMPLEDELAY … #define ixSE_SA1WGP00TCP1_SAMPLEDELAY … #define ixSE_SA1WGP01TA0_SAMPLEDELAY … #define ixSE_SA1WGP01TA1_SAMPLEDELAY … #define ixSE_SA1WGP01TD0_SAMPLEDELAY … #define ixSE_SA1WGP01TD1_SAMPLEDELAY … #define ixSE_SA1WGP01TCP0_SAMPLEDELAY … #define ixSE_SA1WGP01TCP1_SAMPLEDELAY … #define ixSE_SA1WGP02TA0_SAMPLEDELAY … #define ixSE_SA1WGP02TA1_SAMPLEDELAY … #define ixSE_SA1WGP02TD0_SAMPLEDELAY … #define ixSE_SA1WGP02TD1_SAMPLEDELAY … #define ixSE_SA1WGP02TCP0_SAMPLEDELAY … #define ixSE_SA1WGP02TCP1_SAMPLEDELAY … #define ixSE_SA1WGP10TA0_SAMPLEDELAY … #define ixSE_SA1WGP10TA1_SAMPLEDELAY … #define ixSE_SA1WGP10TD0_SAMPLEDELAY … #define ixSE_SA1WGP10TD1_SAMPLEDELAY … #define ixSE_SA1WGP10TCP0_SAMPLEDELAY … #define ixSE_SA1WGP10TCP1_SAMPLEDELAY … #define ixSE_SA1WGP11TA0_SAMPLEDELAY … #define ixSE_SA1WGP11TA1_SAMPLEDELAY … #define ixSE_SA1WGP11TD0_SAMPLEDELAY … #define ixSE_SA1WGP11TD1_SAMPLEDELAY … #define ixSE_SA1WGP11TCP0_SAMPLEDELAY … #define ixSE_SA1WGP11TCP1_SAMPLEDELAY … // addressBlock: sqind // base address: 0x0 #define ixSQ_DEBUG_STS_LOCAL … #define ixSQ_WAVE_MODE … #define ixSQ_WAVE_STATUS … #define ixSQ_WAVE_TRAPSTS … #define ixSQ_WAVE_HW_ID_LEGACY … #define ixSQ_WAVE_GPR_ALLOC … #define ixSQ_WAVE_LDS_ALLOC … #define ixSQ_WAVE_IB_STS … #define ixSQ_WAVE_PC_LO … #define ixSQ_WAVE_PC_HI … #define ixSQ_WAVE_INST_DW0 … #define ixSQ_WAVE_IB_DBG1 … #define ixSQ_WAVE_FLUSH_IB … #define ixSQ_WAVE_HW_ID1 … #define ixSQ_WAVE_HW_ID2 … #define ixSQ_WAVE_POPS_PACKER … #define ixSQ_WAVE_SCHED_MODE … #define ixSQ_WAVE_VGPR_OFFSET … #define ixSQ_WAVE_IB_STS2 … #define ixSQ_WAVE_TTMP0 … #define ixSQ_WAVE_TTMP1 … #define ixSQ_WAVE_TTMP2 … #define ixSQ_WAVE_TTMP3 … #define ixSQ_WAVE_TTMP4 … #define ixSQ_WAVE_TTMP5 … #define ixSQ_WAVE_TTMP6 … #define ixSQ_WAVE_TTMP7 … #define ixSQ_WAVE_TTMP8 … #define ixSQ_WAVE_TTMP9 … #define ixSQ_WAVE_TTMP10 … #define ixSQ_WAVE_TTMP11 … #define ixSQ_WAVE_TTMP12 … #define ixSQ_WAVE_TTMP13 … #define ixSQ_WAVE_TTMP14 … #define ixSQ_WAVE_TTMP15 … #define ixSQ_WAVE_M0 … #define ixSQ_WAVE_EXEC_LO … #define ixSQ_WAVE_EXEC_HI … #define ixSQ_WAVE_FLAT_SCRATCH_LO … #define ixSQ_WAVE_FLAT_SCRATCH_HI … #define ixSQ_WAVE_FLAT_XNACK_MASK … #define ixSQ_INTERRUPT_WORD_AUTO … #define ixSQ_INTERRUPT_WORD_ERROR … #define ixSQ_INTERRUPT_WORD_WAVE … // addressBlock: didtind // base address: 0x0 #define ixDIDT_SQ_CTRL0 … #define ixDIDT_SQ_CTRL1 … #define ixDIDT_SQ_CTRL2 … #define ixDIDT_SQ_CTRL_OCP … #define ixDIDT_SQ_STALL_CTRL … #define ixDIDT_SQ_TUNING_CTRL … #define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL … #define ixDIDT_SQ_CTRL3 … #define ixDIDT_SQ_STALL_PATTERN_1_2 … #define ixDIDT_SQ_STALL_PATTERN_3_4 … #define ixDIDT_SQ_STALL_PATTERN_5_6 … #define ixDIDT_SQ_STALL_PATTERN_7 … #define ixDIDT_SQ_MPD_SCALE_FACTOR … #define ixDIDT_SQ_STALL_RELEASE_CNTL0 … #define ixDIDT_SQ_STALL_RELEASE_CNTL1 … #define ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS … #define ixDIDT_SQ_WEIGHT0_3 … #define ixDIDT_SQ_WEIGHT4_7 … #define ixDIDT_SQ_WEIGHT8_11 … #define ixDIDT_SQ_EDC_CTRL … #define ixDIDT_SQ_EDC_THRESHOLD … #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 … #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 … #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 … #define ixDIDT_SQ_EDC_STALL_PATTERN_7 … #define ixDIDT_SQ_EDC_TIMER_PERIOD … #define ixDIDT_SQ_THROTTLE_CTRL … #define ixDIDT_SQ_EDC_STALL_DELAY_1 … #define ixDIDT_SQ_EDC_STALL_DELAY_2 … #define ixDIDT_SQ_EDC_STALL_DELAY_3 … #define ixDIDT_SQ_EDC_STATUS … #define ixDIDT_SQ_EDC_OVERFLOW … #define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA … #define ixDIDT_SQ_EDC_PCC_PERF_COUNTER … #define ixDIDT_DB_CTRL0 … #define ixDIDT_DB_CTRL1 … #define ixDIDT_DB_CTRL2 … #define ixDIDT_DB_CTRL_OCP … #define ixDIDT_DB_STALL_CTRL … #define ixDIDT_DB_TUNING_CTRL … #define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL … #define ixDIDT_DB_CTRL3 … #define ixDIDT_DB_STALL_PATTERN_1_2 … #define ixDIDT_DB_STALL_PATTERN_3_4 … #define ixDIDT_DB_STALL_PATTERN_5_6 … #define ixDIDT_DB_STALL_PATTERN_7 … #define ixDIDT_DB_MPD_SCALE_FACTOR … #define ixDIDT_DB_STALL_RELEASE_CNTL0 … #define ixDIDT_DB_STALL_RELEASE_CNTL1 … #define ixDIDT_DB_STALL_RELEASE_CNTL_STATUS … #define ixDIDT_DB_WEIGHT0_3 … #define ixDIDT_DB_WEIGHT4_7 … #define ixDIDT_DB_WEIGHT8_11 … #define ixDIDT_DB_EDC_CTRL … #define ixDIDT_DB_EDC_THRESHOLD … #define ixDIDT_DB_EDC_STALL_PATTERN_1_2 … #define ixDIDT_DB_EDC_STALL_PATTERN_3_4 … #define ixDIDT_DB_EDC_STALL_PATTERN_5_6 … #define ixDIDT_DB_EDC_STALL_PATTERN_7 … #define ixDIDT_DB_EDC_TIMER_PERIOD … #define ixDIDT_DB_THROTTLE_CTRL … #define ixDIDT_DB_EDC_STALL_DELAY_1 … #define ixDIDT_DB_EDC_STATUS … #define ixDIDT_DB_EDC_OVERFLOW … #define ixDIDT_DB_EDC_ROLLING_POWER_DELTA … #define ixDIDT_DB_EDC_PCC_PERF_COUNTER … #define ixDIDT_TD_CTRL0 … #define ixDIDT_TD_CTRL1 … #define ixDIDT_TD_CTRL2 … #define ixDIDT_TD_CTRL_OCP … #define ixDIDT_TD_STALL_CTRL … #define ixDIDT_TD_TUNING_CTRL … #define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL … #define ixDIDT_TD_CTRL3 … #define ixDIDT_TD_STALL_PATTERN_1_2 … #define ixDIDT_TD_STALL_PATTERN_3_4 … #define ixDIDT_TD_STALL_PATTERN_5_6 … #define ixDIDT_TD_STALL_PATTERN_7 … #define ixDIDT_TD_MPD_SCALE_FACTOR … #define ixDIDT_TD_STALL_RELEASE_CNTL0 … #define ixDIDT_TD_STALL_RELEASE_CNTL1 … #define ixDIDT_TD_STALL_RELEASE_CNTL_STATUS … #define ixDIDT_TD_WEIGHT0_3 … #define ixDIDT_TD_WEIGHT4_7 … #define ixDIDT_TD_WEIGHT8_11 … #define ixDIDT_TD_EDC_CTRL … #define ixDIDT_TD_EDC_THRESHOLD … #define ixDIDT_TD_EDC_STALL_PATTERN_1_2 … #define ixDIDT_TD_EDC_STALL_PATTERN_3_4 … #define ixDIDT_TD_EDC_STALL_PATTERN_5_6 … #define ixDIDT_TD_EDC_STALL_PATTERN_7 … #define ixDIDT_TD_EDC_TIMER_PERIOD … #define ixDIDT_TD_THROTTLE_CTRL … #define ixDIDT_TD_EDC_STALL_DELAY_1 … #define ixDIDT_TD_EDC_STALL_DELAY_2 … #define ixDIDT_TD_EDC_STALL_DELAY_3 … #define ixDIDT_TD_EDC_STATUS … #define ixDIDT_TD_EDC_OVERFLOW … #define ixDIDT_TD_EDC_ROLLING_POWER_DELTA … #define ixDIDT_TD_EDC_PCC_PERF_COUNTER … #define ixDIDT_TCP_CTRL0 … #define ixDIDT_TCP_CTRL1 … #define ixDIDT_TCP_CTRL2 … #define ixDIDT_TCP_CTRL_OCP … #define ixDIDT_TCP_STALL_CTRL … #define ixDIDT_TCP_TUNING_CTRL … #define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL … #define ixDIDT_TCP_CTRL3 … #define ixDIDT_TCP_STALL_PATTERN_1_2 … #define ixDIDT_TCP_STALL_PATTERN_3_4 … #define ixDIDT_TCP_STALL_PATTERN_5_6 … #define ixDIDT_TCP_STALL_PATTERN_7 … #define ixDIDT_TCP_MPD_SCALE_FACTOR … #define ixDIDT_TCP_STALL_RELEASE_CNTL0 … #define ixDIDT_TCP_STALL_RELEASE_CNTL1 … #define ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS … #define ixDIDT_TCP_WEIGHT0_3 … #define ixDIDT_TCP_WEIGHT4_7 … #define ixDIDT_TCP_WEIGHT8_11 … #define ixDIDT_TCP_EDC_CTRL … #define ixDIDT_TCP_EDC_THRESHOLD … #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 … #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 … #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 … #define ixDIDT_TCP_EDC_STALL_PATTERN_7 … #define ixDIDT_TCP_EDC_TIMER_PERIOD … #define ixDIDT_TCP_THROTTLE_CTRL … #define ixDIDT_TCP_EDC_STALL_DELAY_1 … #define ixDIDT_TCP_EDC_STALL_DELAY_2 … #define ixDIDT_TCP_EDC_STALL_DELAY_3 … #define ixDIDT_TCP_EDC_STATUS … #define ixDIDT_TCP_EDC_OVERFLOW … #define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA … #define ixDIDT_TCP_EDC_PCC_PERF_COUNTER … #define ixDIDT_SQ_STALL_EVENT_COUNTER … #define ixDIDT_DB_STALL_EVENT_COUNTER … #define ixDIDT_TD_STALL_EVENT_COUNTER … #define ixDIDT_TCP_STALL_EVENT_COUNTER … #endif
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