#include <drm/drm_edid.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_modeset_helper.h>
#include <drm/drm_modeset_helper_vtables.h>
#include <drm/drm_vblank.h>
#include "amdgpu.h"
#include "amdgpu_pm.h"
#include "amdgpu_i2c.h"
#include "cikd.h"
#include "atom.h"
#include "amdgpu_atombios.h"
#include "atombios_crtc.h"
#include "atombios_encoders.h"
#include "amdgpu_pll.h"
#include "amdgpu_connectors.h"
#include "amdgpu_display.h"
#include "dce_v8_0.h"
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
#include "gca/gfx_7_2_enum.h"
#include "gmc/gmc_7_1_d.h"
#include "gmc/gmc_7_1_sh_mask.h"
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
static const u32 crtc_offsets[6] = …;
static const u32 hpd_offsets[] = …;
static const uint32_t dig_offsets[] = …;
static const struct { … } interrupt_status_offsets[6] = …;
static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
u32 block_offset, u32 reg)
{ … }
static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
u32 block_offset, u32 reg, u32 v)
{ … }
static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
{ … }
static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_page_flip(struct amdgpu_device *adev,
int crtc_id, u64 crtc_base, bool async)
{ … }
static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
u32 *vbl, u32 *position)
{ … }
static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
enum amdgpu_hpd_id hpd)
{ … }
static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
enum amdgpu_hpd_id hpd)
{ … }
static void dce_v8_0_hpd_int_ack(struct amdgpu_device *adev,
int hpd)
{ … }
static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
{ … }
static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
{ … }
static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
bool render)
{ … }
static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
{ … }
void dce_v8_0_disable_dce(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
{ … }
static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
struct amdgpu_crtc *amdgpu_crtc,
struct drm_display_mode *mode)
{ … }
static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
{ … }
struct dce8_wm_params { … };
static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
{ … }
static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
{ … }
static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
{ … }
static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
{ … }
static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
{ … }
static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
{ … }
static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
{ … }
static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
{ … }
static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
{ … }
static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
{ … }
static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
struct amdgpu_crtc *amdgpu_crtc,
u32 lb_size, u32 num_heads)
{ … }
static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
{ … }
static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
{ … }
static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
struct drm_display_mode *mode)
{ … }
static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
{ … }
static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
{ … }
static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
struct amdgpu_audio_pin *pin,
bool enable)
{ … }
static const u32 pin_offsets[7] = …;
static int dce_v8_0_audio_init(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
{ … }
static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
void *buffer, size_t size)
{ … }
static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
{ … }
static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
struct drm_display_mode *mode)
{ … }
static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
{ … }
static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
{ … }
static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
{ … }
static const u32 vga_control_regs[6] = …;
static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
{ … }
static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
{ … }
static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y, int atomic)
{ … }
static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
struct drm_display_mode *mode)
{ … }
static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
{ … }
static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
{ … }
static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
{ … }
static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
{ … }
static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
{ … }
static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
{ … }
static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
int x, int y)
{ … }
static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
int x, int y)
{ … }
static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
struct drm_file *file_priv,
uint32_t handle,
uint32_t width,
uint32_t height,
int32_t hot_x,
int32_t hot_y)
{ … }
static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
{ … }
static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
u16 *blue, uint32_t size,
struct drm_modeset_acquire_ctx *ctx)
{ … }
static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
{ … }
static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = …;
static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
{ … }
static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
{ … }
static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
{ … }
static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
{ … }
static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
int x, int y, struct drm_framebuffer *old_fb)
{ … }
static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{ … }
static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb)
{ … }
static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y, enum mode_set_atomic state)
{ … }
static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = …;
static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
{ … }
static int dce_v8_0_early_init(void *handle)
{ … }
static int dce_v8_0_sw_init(void *handle)
{ … }
static int dce_v8_0_sw_fini(void *handle)
{ … }
static int dce_v8_0_hw_init(void *handle)
{ … }
static int dce_v8_0_hw_fini(void *handle)
{ … }
static int dce_v8_0_suspend(void *handle)
{ … }
static int dce_v8_0_resume(void *handle)
{ … }
static bool dce_v8_0_is_idle(void *handle)
{ … }
static int dce_v8_0_wait_for_idle(void *handle)
{ … }
static int dce_v8_0_soft_reset(void *handle)
{ … }
static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
int crtc,
enum amdgpu_interrupt_state state)
{ … }
static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
int crtc,
enum amdgpu_interrupt_state state)
{ … }
static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned type,
enum amdgpu_interrupt_state state)
{ … }
static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned type,
enum amdgpu_interrupt_state state)
{ … }
static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{ … }
static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned type,
enum amdgpu_interrupt_state state)
{ … }
static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{ … }
static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{ … }
static int dce_v8_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{ … }
static int dce_v8_0_set_powergating_state(void *handle,
enum amd_powergating_state state)
{ … }
static const struct amd_ip_funcs dce_v8_0_ip_funcs = …;
static void
dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{ … }
static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
{ … }
static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
{ … }
static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
{ … }
static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
{ … }
static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
{ … }
static void
dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{ … }
static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
{ … }
static void
dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
{ … }
static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = …;
static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = …;
static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = …;
static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
{ … }
static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = …;
static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
uint32_t encoder_enum,
uint32_t supported_device,
u16 caps)
{ … }
static const struct amdgpu_display_funcs dce_v8_0_display_funcs = …;
static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
{ … }
static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = …;
static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = …;
static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = …;
static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
{ … }
const struct amdgpu_ip_block_version dce_v8_0_ip_block = …;
const struct amdgpu_ip_block_version dce_v8_1_ip_block = …;
const struct amdgpu_ip_block_version dce_v8_2_ip_block = …;
const struct amdgpu_ip_block_version dce_v8_3_ip_block = …;
const struct amdgpu_ip_block_version dce_v8_5_ip_block = …;